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improved timing, added timing constraints, got rid of CLK_33M

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Design compiles and runs, but still has issues with different screen resolutions and video clocks
This commit is contained in:
Markus Fröschle
2015-09-23 09:49:05 +00:00
parent ad05ca8523
commit 7e2181fbc9
19 changed files with 1631 additions and 1519 deletions
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16
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
View File

@@ -370,7 +370,7 @@ BEGIN
-- ACSI, SCSI UND FLOPPY WD1772 -- ACSI, SCSI UND FLOPPY WD1772
------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo -- daten read fifo
RDF: dcfifo0 i_data_read_fifo: dcfifo0
PORT MAP( PORT MAP(
aclr => CLR_FIFO, aclr => CLR_FIFO,
data => RDF_DIN, data => RDF_DIN,
@@ -390,7 +390,7 @@ BEGIN
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
-- daten write fifo -- daten write fifo
WRF: dcfifo1 i_data_write_fifo: dcfifo1
PORT MAP( PORT MAP(
aclr => CLR_FIFO, aclr => CLR_FIFO,
data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24),
@@ -527,7 +527,7 @@ BEGIN
END CASE; END CASE;
END PROCESS FCF_DECODER; END PROCESS FCF_DECODER;
I_FDC: WF1772IP_TOP_SOC i_fdc : WF1772IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => FDC_CLK, CLK => FDC_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -731,7 +731,7 @@ BEGIN
CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD;
-- SCSI ---------------------------------------------------------------------------------- -- SCSI ----------------------------------------------------------------------------------
I_SCSI: WF5380_TOP_SOC i_scsi : WF5380_TOP_SOC
PORT MAP( PORT MAP(
CLK => FDC_CLK, CLK => FDC_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -810,7 +810,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- ACIA KEYBOARD -- ACIA KEYBOARD
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC i_acia_keyboard : WF6850IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => MAIN_CLK, CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -867,7 +867,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- ACIA MIDI -- ACIA MIDI
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC i_acia_midi : WF6850IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => MAIN_CLK, CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -901,7 +901,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- MFP -- MFP
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC i_mfp : WF68901IP_TOP_SOC
PORT MAP( PORT MAP(
-- System control: -- System control:
CLK => MAIN_CLK, CLK => MAIN_CLK,
@@ -978,7 +978,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Sound -- Sound
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC i_sound : WF2149IP_TOP_SOC
PORT MAP( PORT MAP(
SYS_CLK => MAIN_CLK, SYS_CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,

2
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -552,7 +552,7 @@ BEGIN
-- VIDEO AUSGABE SETZEN -- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M; CLK17M.CLK = MAIN_CLK;
CLK17M = !CLK17M; CLK17M = !CLK17M;
CLK13M.CLK = CLK25M; CLK13M.CLK = CLK25M;
CLK13M = !CLK13M; CLK13M = !CLK13M;

124
FPGA_Quartus_13.1/altpll1.bsf
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@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 328 216) (rect 0 0 272 176)
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 197 31 212)(font "Arial" )) (text "inst" (rect 8 161 26 172)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 64)
(input) (input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1)) (line (pt 0 64)(pt 40 64))
) )
(port (port
(pt 328 72) (pt 272 64)
(output) (output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8))) (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
(line (pt 328 72)(pt 272 72)(line_width 1))
) )
(port (port
(pt 328 96) (pt 272 80)
(output) (output)
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8))) (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
(line (pt 328 96)(pt 272 96)(line_width 1))
) )
(port (port
(pt 328 120) (pt 272 96)
(output) (output)
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8))) (text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
(line (pt 328 120)(pt 272 120)(line_width 1))
) )
(port (port
(pt 328 144) (pt 272 112)
(output) (output)
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8))) (text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
(line (pt 328 144)(pt 272 144)(line_width 1))
) )
(drawing (drawing
(text "Cyclone III" (rect 253 198 301 212)(font "Arial" )) (text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" )) (text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 90 111 114 125)(font "Arial" )) (text "Ratio" (rect 82 91 187 192)(font "Arial" ))
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
(text "DC (%)" (rect 173 111 208 125)(font "Arial" )) (text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" )) (text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "1/66" (rect 92 129 113 143)(font "Arial" )) (text "1/66" (rect 84 104 186 218)(font "Arial" ))
(text "0.00" (rect 136 129 157 143)(font "Arial" )) (text "0.00" (rect 125 104 269 218)(font "Arial" ))
(text "50.00" (rect 178 129 205 143)(font "Arial" )) (text "50.00" (rect 158 104 340 218)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" )) (text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "67/900" (rect 85 147 118 161)(font "Arial" )) (text "512/6875" (rect 74 117 187 244)(font "Arial" ))
(text "0.00" (rect 136 147 157 161)(font "Arial" )) (text "0.00" (rect 125 117 269 244)(font "Arial" ))
(text "50.00" (rect 178 147 205 161)(font "Arial" )) (text "50.00" (rect 158 117 340 244)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "67/90" (rect 89 165 116 179)(font "Arial" )) (text "1024/1375" (rect 71 130 185 270)(font "Arial" ))
(text "0.00" (rect 136 165 157 179)(font "Arial" )) (text "0.00" (rect 125 130 269 270)(font "Arial" ))
(text "50.00" (rect 178 165 205 179)(font "Arial" )) (text "50.00" (rect 158 130 340 270)(font "Arial" ))
(line (pt 0 0)(pt 329 0)(line_width 1)) (line (pt 0 0)(pt 273 0))
(line (pt 329 0)(pt 329 217)(line_width 1)) (line (pt 273 0)(pt 273 177))
(line (pt 0 217)(pt 329 217)(line_width 1)) (line (pt 0 177)(pt 273 177))
(line (pt 0 0)(pt 0 217)(line_width 1)) (line (pt 0 0)(pt 0 177))
(line (pt 56 108)(pt 215 108)(line_width 1)) (line (pt 48 89)(pt 186 89))
(line (pt 56 125)(pt 215 125)(line_width 1)) (line (pt 48 101)(pt 186 101))
(line (pt 56 143)(pt 215 143)(line_width 1)) (line (pt 48 114)(pt 186 114))
(line (pt 56 161)(pt 215 161)(line_width 1)) (line (pt 48 127)(pt 186 127))
(line (pt 56 179)(pt 215 179)(line_width 1)) (line (pt 48 140)(pt 186 140))
(line (pt 56 108)(pt 56 179)(line_width 1)) (line (pt 48 89)(pt 48 140))
(line (pt 82 108)(pt 82 179)(line_width 3)) (line (pt 68 89)(pt 68 140)(line_width 3))
(line (pt 125 108)(pt 125 179)(line_width 3)) (line (pt 116 89)(pt 116 140)(line_width 3))
(line (pt 170 108)(pt 170 179)(line_width 3)) (line (pt 151 89)(pt 151 140)(line_width 3))
(line (pt 214 108)(pt 214 179)(line_width 1)) (line (pt 185 89)(pt 185 140))
(line (pt 48 56)(pt 272 56)(line_width 1)) (line (pt 40 48)(pt 223 48))
(line (pt 272 56)(pt 272 200)(line_width 1)) (line (pt 223 48)(pt 223 159))
(line (pt 48 200)(pt 272 200)(line_width 1)) (line (pt 40 159)(pt 223 159))
(line (pt 48 56)(pt 48 200)(line_width 1)) (line (pt 40 48)(pt 40 159))
(line (pt 271 64)(pt 223 64))
(line (pt 271 80)(pt 223 80))
(line (pt 271 96)(pt 223 96))
(line (pt 271 112)(pt 223 112))
) )
) )

2
FPGA_Quartus_13.1/altpll1.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]

56
FPGA_Quartus_13.1/altpll1.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -131,22 +131,22 @@ ARCHITECTURE SYN OF altpll1 IS
width_clock : NATURAL width_clock : NATURAL
); );
PORT ( PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ; locked : OUT STD_LOGIC
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
BEGIN BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0"; sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv); sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire3 <= sub_wire0(2); sub_wire4 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1); sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(0); sub_wire1 <= sub_wire0(1);
c0 <= sub_wire1; c1 <= sub_wire1;
c1 <= sub_wire2; locked <= sub_wire2;
c2 <= sub_wire3; c0 <= sub_wire3;
locked <= sub_wire4; c2 <= sub_wire4;
sub_wire5 <= inclk0; sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
@@ -157,13 +157,13 @@ BEGIN
clk0_duty_cycle => 50, clk0_duty_cycle => 50,
clk0_multiply_by => 1, clk0_multiply_by => 1,
clk0_phase_shift => "0", clk0_phase_shift => "0",
clk1_divide_by => 900, clk1_divide_by => 6875,
clk1_duty_cycle => 50, clk1_duty_cycle => 50,
clk1_multiply_by => 67, clk1_multiply_by => 512,
clk1_phase_shift => "0", clk1_phase_shift => "0",
clk2_divide_by => 90, clk2_divide_by => 1375,
clk2_duty_cycle => 50, clk2_duty_cycle => 50,
clk2_multiply_by => 67, clk2_multiply_by => 1024,
clk2_phase_shift => "0", clk2_phase_shift => "0",
compensate_clock => "CLK0", compensate_clock => "CLK0",
inclk0_input_frequency => 30303, inclk0_input_frequency => 30303,
@@ -218,7 +218,7 @@ BEGIN
PORT MAP ( PORT MAP (
inclk => sub_wire6, inclk => sub_wire6,
clk => sub_wire0, clk => sub_wire0,
locked => sub_wire4 locked => sub_wire2
); );
@@ -251,8 +251,8 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -270,7 +270,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -287,8 +287,8 @@ END SYN;
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -342,13 +342,13 @@ END SYN;
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
@@ -406,17 +406,17 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE

4
FPGA_Quartus_13.1/altpll3.bsf
View File

@@ -71,11 +71,11 @@ applicable agreement for further details.
(text "0.00" (rect 115 117 249 244)(font "Arial" )) (text "0.00" (rect 115 117 249 244)(font "Arial" ))
(text "50.00" (rect 148 117 320 244)(font "Arial" )) (text "50.00" (rect 148 117 320 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "109/144" (rect 71 130 175 270)(font "Arial" )) (text "227/300" (rect 71 130 176 270)(font "Arial" ))
(text "0.00" (rect 115 130 249 270)(font "Arial" )) (text "0.00" (rect 115 130 249 270)(font "Arial" ))
(text "50.00" (rect 148 130 320 270)(font "Arial" )) (text "50.00" (rect 148 130 320 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" )) (text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "16/11" (rect 77 143 176 296)(font "Arial" )) (text "227/156" (rect 71 143 176 296)(font "Arial" ))
(text "0.00" (rect 115 143 249 296)(font "Arial" )) (text "0.00" (rect 115 143 249 296)(font "Arial" ))
(text "50.00" (rect 148 143 320 296)(font "Arial" )) (text "50.00" (rect 148 143 320 296)(font "Arial" ))
(line (pt 0 0)(pt 257 0)) (line (pt 0 0)(pt 257 0))

38
FPGA_Quartus_13.1/altpll3.vhd
View File

@@ -164,13 +164,13 @@ BEGIN
clk1_duty_cycle => 50, clk1_duty_cycle => 50,
clk1_multiply_by => 16, clk1_multiply_by => 16,
clk1_phase_shift => "0", clk1_phase_shift => "0",
clk2_divide_by => 144, clk2_divide_by => 300,
clk2_duty_cycle => 50, clk2_duty_cycle => 50,
clk2_multiply_by => 109, clk2_multiply_by => 227,
clk2_phase_shift => "0", clk2_phase_shift => "0",
clk3_divide_by => 11, clk3_divide_by => 156,
clk3_duty_cycle => 50, clk3_duty_cycle => 50,
clk3_multiply_by => 16, clk3_multiply_by => 227,
clk3_phase_shift => "0", clk3_phase_shift => "0",
compensate_clock => "CLK1", compensate_clock => "CLK1",
inclk0_input_frequency => 30303, inclk0_input_frequency => 30303,
@@ -249,18 +249,18 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "144" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.979166" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -289,16 +289,16 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" -- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
@@ -365,13 +365,13 @@ END SYN;
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "144" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "109" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
@@ -440,6 +440,6 @@ END SYN;
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

152
FPGA_Quartus_13.1/altpll4.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 376 232) (rect 0 0 312 184)
(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) (text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 213 31 228)(font "Arial" )) (text "inst" (rect 8 168 25 180)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 64)
(input) (input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1)) (line (pt 0 64)(pt 72 64))
)
(port
(pt 0 80)
(input)
(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 72 80))
) )
(port (port
(pt 0 96) (pt 0 96)
(input) (input)
(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) (text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) (text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96)(line_width 1)) (line (pt 0 96)(pt 72 96))
) )
(port (port
(pt 0 120) (pt 0 112)
(input) (input)
(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) (text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) (text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120)(line_width 1)) (line (pt 0 112)(pt 72 112))
)
(port
(pt 0 128)
(input)
(text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 72 128))
) )
(port (port
(pt 0 144) (pt 0 144)
(input) (input)
(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) (text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) (text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144)(line_width 1)) (line (pt 0 144)(pt 72 144))
) )
(port (port
(pt 0 168) (pt 312 64)
(input)
(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192)(line_width 1))
)
(port
(pt 376 72)
(output) (output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) (text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72)(line_width 1))
) )
(port (port
(pt 376 96) (pt 312 80)
(output) (output)
(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) (text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) (text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96)(line_width 1))
) )
(port (port
(pt 376 120) (pt 312 96)
(output) (output)
(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) (text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) (text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8)))
(line (pt 376 120)(pt 288 120)(line_width 1))
) )
(port (port
(pt 376 144) (pt 312 112)
(output) (output)
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) (text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8)))
(line (pt 376 144)(pt 288 144)(line_width 1))
) )
(drawing (drawing
(text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) (text "Cyclone III" (rect 250 169 545 349)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) (text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) (text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" ))
(text "Clk " (rect 99 167 116 181)(font "Arial" )) (text "Clk " (rect 83 126 180 263)(font "Arial" ))
(text "Ratio" (rect 125 167 149 181)(font "Arial" )) (text "Ratio" (rect 104 126 228 263)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) (text "Ph (dg)" (rect 130 126 289 263)(font "Arial" ))
(text "DC (%)" (rect 204 167 239 181)(font "Arial" )) (text "DC (%)" (rect 164 126 358 263)(font "Arial" ))
(text "c0" (rect 103 185 115 199)(font "Arial" )) (text "c0" (rect 86 140 180 291)(font "Arial" ))
(text "2/1" (rect 131 185 146 199)(font "Arial" )) (text "2/1" (rect 109 140 228 291)(font "Arial" ))
(text "0.00" (rect 167 185 188 199)(font "Arial" )) (text "0.00" (rect 136 140 288 291)(font "Arial" ))
(text "50.00" (rect 209 185 236 199)(font "Arial" )) (text "50.00" (rect 168 140 357 291)(font "Arial" ))
(line (pt 0 0)(pt 377 0)(line_width 1)) (line (pt 0 0)(pt 313 0))
(line (pt 377 0)(pt 377 233)(line_width 1)) (line (pt 313 0)(pt 313 186))
(line (pt 0 233)(pt 377 233)(line_width 1)) (line (pt 0 186)(pt 313 186))
(line (pt 0 0)(pt 0 233)(line_width 1)) (line (pt 0 0)(pt 0 186))
(line (pt 96 164)(pt 246 164)(line_width 1)) (line (pt 80 124)(pt 196 124))
(line (pt 96 181)(pt 246 181)(line_width 1)) (line (pt 80 137)(pt 196 137))
(line (pt 96 199)(pt 246 199)(line_width 1)) (line (pt 80 151)(pt 196 151))
(line (pt 96 164)(pt 96 199)(line_width 1)) (line (pt 80 124)(pt 80 151))
(line (pt 122 164)(pt 122 199)(line_width 3)) (line (pt 101 124)(pt 101 151)(line_width 3))
(line (pt 156 164)(pt 156 199)(line_width 3)) (line (pt 127 124)(pt 127 151)(line_width 3))
(line (pt 201 164)(pt 201 199)(line_width 3)) (line (pt 161 124)(pt 161 151)(line_width 3))
(line (pt 245 164)(pt 245 199)(line_width 1)) (line (pt 195 124)(pt 195 151))
(line (pt 88 56)(pt 288 56)(line_width 1)) (line (pt 72 48)(pt 239 48))
(line (pt 288 56)(pt 288 216)(line_width 1)) (line (pt 239 48)(pt 239 168))
(line (pt 88 216)(pt 288 216)(line_width 1)) (line (pt 72 168)(pt 239 168))
(line (pt 88 56)(pt 88 216)(line_width 1)) (line (pt 72 48)(pt 72 168))
(line (pt 311 64)(pt 239 64))
(line (pt 311 80)(pt 239 80))
(line (pt 311 96)(pt 239 96))
(line (pt 311 112)(pt 239 112))
) )
) )

2
FPGA_Quartus_13.1/altpll4.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll4.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

6
FPGA_Quartus_13.1/altpll4.mif
View File

@@ -1,4 +1,4 @@
-- Copyright (C) 1991-2010 Altera Corporation -- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions -- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic -- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing -- functions, and any output files from any of the foregoing
@@ -17,8 +17,8 @@
-- Device Part: - -- Device Part: -
-- Device Speed Grade: 8 -- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits) -- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: C:\FireBee\FPGA\altpll4.mif -- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif
-- Generated: Mon Dec 06 01:47:24 2010 -- Generated: Mon Sep 21 17:50:54 2015
WIDTH=1; WIDTH=1;
DEPTH=144; DEPTH=144;

2
FPGA_Quartus_13.1/altpll4.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]

46
FPGA_Quartus_13.1/altpll4.tdf
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -59,7 +59,7 @@ VARIABLE
CLK0_MULTIPLY_BY = 2, CLK0_MULTIPLY_BY = 2,
CLK0_PHASE_SHIFT = "0", CLK0_PHASE_SHIFT = "0",
COMPENSATE_CLOCK = "CLK0", COMPENSATE_CLOCK = "CLK0",
INCLK0_INPUT_FREQUENCY = 20833, INCLK0_INPUT_FREQUENCY = 20824,
INTENDED_DEVICE_FAMILY = "Cyclone III", INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_TYPE = "altpll", LPM_TYPE = "altpll",
OPERATION_MODE = "NORMAL", OPERATION_MODE = "NORMAL",
@@ -113,16 +113,16 @@ VARIABLE
BEGIN BEGIN
c0 = altpll_component.clk[0..0]; c0 = altpll_component.clk[0..0];
scandone = altpll_component.scandone;
scandataout = altpll_component.scandataout; scandataout = altpll_component.scandataout;
scandone = altpll_component.scandone;
locked = altpll_component.locked; locked = altpll_component.locked;
altpll_component.scanclkena = scanclkena; altpll_component.areset = areset;
altpll_component.configupdate = configupdate;
altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[0..0] = inclk0;
altpll_component.inclk[1..1] = GND; altpll_component.inclk[1..1] = GND;
altpll_component.scandata = scandata;
altpll_component.areset = areset;
altpll_component.scanclk = scanclk; altpll_component.scanclk = scanclk;
altpll_component.configupdate = configupdate; altpll_component.scanclkena = scanclkena;
altpll_component.scandata = scandata;
END; END;
@@ -148,7 +148,7 @@ END;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -156,7 +156,7 @@ END;
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@@ -166,7 +166,7 @@ END;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
@@ -217,7 +217,7 @@ END;
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
@@ -277,22 +277,22 @@ END;
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

270
FPGA_Quartus_13.1/firebee1.bdf
View File

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) )
(symbol
(rect 608 496 984 728)
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(text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" ))
(text "Clk " (rect 99 167 119 178)(font "Arial" ))
(text "Ratio" (rect 125 167 152 178)(font "Arial" ))
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(text "DC (%)" (rect 204 167 241 178)(font "Arial" ))
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(pt 328 120) (pt 328 120)
(output) (output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 311 104 323 117)(font "Arial" (font_size 8))) (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8)))
(line (pt 328 120)(pt 272 120)) (line (pt 328 120)(pt 272 120))
) )
(port (port
(pt 328 144) (pt 328 144)
(output) (output)
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 287 128 318 141)(font "Arial" (font_size 8))) (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8)))
(line (pt 328 144)(pt 272 144)) (line (pt 328 144)(pt 272 144))
) )
(drawing (drawing
@@ -3321,49 +3217,49 @@ applicable agreement for further details.
(pt 216 40) (pt 216 40)
(output) (output)
(text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8)))
(text "busy" (rect 171 32 195 45)(font "Arial" (font_size 8))) (text "busy" (rect 171 32 200 45)(font "Arial" (font_size 8)))
(line (pt 216 40)(pt 200 40)) (line (pt 216 40)(pt 200 40))
) )
(port (port
(pt 216 96) (pt 216 96)
(output) (output)
(text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8)))
(text "data_out[8..0]" (rect 129 88 195 101)(font "Arial" (font_size 8))) (text "data_out[8..0]" (rect 129 88 208 101)(font "Arial" (font_size 8)))
(line (pt 216 96)(pt 200 96)(line_width 3)) (line (pt 216 96)(pt 200 96)(line_width 3))
) )
(port (port
(pt 216 152) (pt 216 152)
(output) (output)
(text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8)))
(text "pll_scandata" (rect 135 144 195 157)(font "Arial" (font_size 8))) (text "pll_scandata" (rect 135 144 206 157)(font "Arial" (font_size 8)))
(line (pt 216 152)(pt 200 152)) (line (pt 216 152)(pt 200 152))
) )
(port (port
(pt 216 168) (pt 216 168)
(output) (output)
(text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "pll_scanclk" (rect 141 160 195 173)(font "Arial" (font_size 8))) (text "pll_scanclk" (rect 141 160 205 173)(font "Arial" (font_size 8)))
(line (pt 216 168)(pt 200 168)) (line (pt 216 168)(pt 200 168))
) )
(port (port
(pt 216 200) (pt 216 200)
(output) (output)
(text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8)))
(text "pll_scanclkena" (rect 125 192 195 205)(font "Arial" (font_size 8))) (text "pll_scanclkena" (rect 125 192 208 205)(font "Arial" (font_size 8)))
(line (pt 216 200)(pt 200 200)) (line (pt 216 200)(pt 200 200))
) )
(port (port
(pt 216 216) (pt 216 216)
(output) (output)
(text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8)))
(text "pll_configupdate" (rect 117 208 195 221)(font "Arial" (font_size 8))) (text "pll_configupdate" (rect 117 208 210 221)(font "Arial" (font_size 8)))
(line (pt 216 216)(pt 200 216)) (line (pt 216 216)(pt 200 216))
) )
(port (port
(pt 216 248) (pt 216 248)
(output) (output)
(text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8)))
(text "pll_areset" (rect 148 240 195 253)(font "Arial" (font_size 8))) (text "pll_areset" (rect 148 240 204 253)(font "Arial" (font_size 8)))
(line (pt 216 248)(pt 200 248)) (line (pt 216 248)(pt 200 248))
) )
(drawing (drawing
@@ -3377,6 +3273,110 @@ applicable agreement for further details.
(line (pt 16 24)(pt 16 273)) (line (pt 16 24)(pt 16 273))
) )
) )
(symbol
(rect 608 496 984 728)
(text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10)))
(text "i_video_clk_pll" (rect 8 213 81 224)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72))
)
(port
(pt 0 96)
(input)
(text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8)))
(text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96))
)
(port
(pt 0 120)
(input)
(text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120))
)
(port
(pt 0 144)
(input)
(text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144))
)
(port
(pt 0 168)
(input)
(text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168))
)
(port
(pt 0 192)
(input)
(text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192))
)
(port
(pt 376 72)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 374 69)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72))
)
(port
(pt 376 96)
(output)
(text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 372 93)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96))
)
(port
(pt 376 120)
(output)
(text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8)))
(text "scandone" (rect 317 104 373 117)(font "Arial" (font_size 8)))
(line (pt 376 120)(pt 288 120))
)
(port
(pt 376 144)
(output)
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 335 128 372 141)(font "Arial" (font_size 8)))
(line (pt 376 144)(pt 288 144))
)
(drawing
(text "Cyclone III" (rect 301 214 352 225)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" ))
(text "Clk " (rect 99 167 119 178)(font "Arial" ))
(text "Ratio" (rect 125 167 152 178)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 196 178)(font "Arial" ))
(text "DC (%)" (rect 204 167 241 178)(font "Arial" ))
(text "c0" (rect 103 185 115 196)(font "Arial" ))
(text "2/1" (rect 131 185 146 196)(font "Arial" ))
(text "0.00" (rect 167 185 190 196)(font "Arial" ))
(text "50.00" (rect 209 185 238 196)(font "Arial" ))
(line (pt 0 0)(pt 377 0))
(line (pt 377 0)(pt 377 233))
(line (pt 0 233)(pt 377 233))
(line (pt 0 0)(pt 0 233))
(line (pt 96 164)(pt 246 164))
(line (pt 96 181)(pt 246 181))
(line (pt 96 199)(pt 246 199))
(line (pt 96 164)(pt 96 199))
(line (pt 122 164)(pt 122 199)(line_width 3))
(line (pt 156 164)(pt 156 199)(line_width 3))
(line (pt 201 164)(pt 201 199)(line_width 3))
(line (pt 245 164)(pt 245 199))
(line (pt 88 56)(pt 288 56))
(line (pt 288 56)(pt 288 216))
(line (pt 88 216)(pt 288 216))
(line (pt 88 56)(pt 88 216))
)
)
(block (block
(rect 1264 2344 1672 2904) (rect 1264 2344 1672 2904)
(text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input))

18
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -368,7 +368,7 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
@@ -573,6 +573,17 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name DISABLE_OCP_HW_EVAL ON set_global_assignment -name DISABLE_OCP_HW_EVAL ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE DSP/DSP.vhd
@@ -731,6 +742,7 @@ set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name QIP_FILE altpll3.qip set_global_assignment -name QIP_FILE altpll3.qip
set_global_assignment -name SOURCE_FILE altpll3.cmp set_global_assignment -name SOURCE_FILE altpll3.cmp
set_global_assignment -name QIP_FILE altpll4.qip set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name AHDL_FILE altpll4.tdf
set_global_assignment -name QIP_FILE altpll_reconfig1.qip set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name SOURCE_FILE lpm_counter0.cmp set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name BDF_FILE firebee1.bdf
@@ -739,8 +751,4 @@ set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

150
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -19,7 +19,7 @@
## PROGRAM "Quartus II" ## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sun Sep 20 21:23:37 2015" ## DATE "Mon Sep 21 20:39:03 2015"
## ##
## DEVICE "EP3C40F484C6" ## DEVICE "EP3C40F484C6"
@@ -40,13 +40,47 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
# Clocks used:
# MAIN_CLK 33MHz
#
# PLL1: i_mfp_acia_clk_pll
# input: MAIN_CLK
# c0: 500 kHz
# c1: 2.4576 MHz
# c2: 24.576 MHz
#
# PLL2: i_ddr_clock_pll
# input: MAIN_CLK
# c0: 132 MHz
# c1: 132 MHz
# c2: 132 MHz
# c3: 132 MHz
# c4: 66 MHz
#
# PLL3: i_atari_clk_pll
# input: MAIN_CLK
# c0: 2 MHz
# c1: 16 MHz
# c2: 25 MHz
# c3: 48 MHz
#
# PLL4_ i_video_clk_pll
# input: USB_CLK (48 MHz, PLL3 c3)
# c0: 96 MHz, programmable in 1MHz steps
#
#************************************************************** #**************************************************************
# Create Generated Clock # Create Generated Clock
#************************************************************** #**************************************************************
derive_pll_clocks derive_pll_clocks
# PIXEL_CLK is either
# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
# where CLK13M is half of CLK25M,
# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
# clock of i_video_clk_pll
#
#************************************************************** #**************************************************************
# Set Clock Latency # Set Clock Latency
@@ -58,21 +92,23 @@ derive_pll_clocks
# Set Clock Uncertainty # Set Clock Uncertainty
#************************************************************** #**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
derive_clock_uncertainty derive_clock_uncertainty
#************************************************************** #**************************************************************
# Set Input Delay # Set Input Delay
#************************************************************** #**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
#************************************************************** #**************************************************************
# Set Output Delay # Set Output Delay
#************************************************************** #**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
#************************************************************** #**************************************************************
@@ -85,52 +121,120 @@ derive_clock_uncertainty
# Set False Path # Set False Path
#************************************************************** #**************************************************************
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] #
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] # i_videl_clk is freely programmable
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] #
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] # MAIN_CLK to 16 MHz clk -> false_path
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
# MAIN_CLK to DDR clk and v.v.
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
# 2 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
# 16 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
# 25 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|nBLANK}] -to [get_keepers {falconio_sdcard_ide_cf:i_falcon_io_sdcard_ide_cf|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]}]
#************************************************************** #**************************************************************
# Set Multicycle Path # Set Multicycle Path
#************************************************************** #**************************************************************
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 # Clocks used:
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 # MAIN_CLK 33MHz
set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8 #
# PLL1: i_mfp_acia_clk_pll
# input: MAIN_CLK
# c0: 500 kHz
# c1: 2.4576 MHz
# c2: 24.576 MHz
#
# PLL2: i_ddr_clock_pll
# input: MAIN_CLK
# c0: 132 MHz
# c1: 132 MHz
# c2: 132 MHz
# c3: 132 MHz
# c4: 66 MHz
#
# PLL3: i_atari_clk_pll
# input: MAIN_CLK
# c0: 2 MHz
# c1: 16 MHz
# c2: 25 MHz
# c3: 48 MHz
#
# PLL4_ i_video_clk_pll
# input: USB_CLK (48 MHz, PLL3 c3)
# c0: 96 MHz, programmable in 1MHz steps
# 66 MHz to 33 MHz
set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
# 33 MHz to 66 MHz
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
# 132 MHz to 33 MHz
set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
# 33 MHz to 132 MHz
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
#************************************************************** #**************************************************************
# Set Maximum Delay # Set Maximum Delay
#************************************************************** #**************************************************************
# from here to the end of the file statements are just an experiment
#set_max_delay 25 -from [get_ports {*}]
#************************************************************** #**************************************************************
# Set Minimum Delay # Set Minimum Delay
#************************************************************** #**************************************************************
#set_min_delay 0.5 -from [get_ports {*}]
#************************************************************** #**************************************************************
# Set Input Transition # Set Input Transition
#************************************************************** #**************************************************************
#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5