Firebee/FPGA_Config
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improved timing, added timing constraints, got rid of CLK_33M

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Design compiles and runs, but still has issues with different screen resolutions and video clocks
This commit is contained in:
Markus Fröschle
2015-09-23 09:49:05 +00:00
parent ad05ca8523
commit 7e2181fbc9
19 changed files with 1631 additions and 1519 deletions
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14
FPGA_Quartus_13.1/altpll1.qip
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@@ -1,7 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]