From 7d2430a62c468f75de29a1f76d24a3c9197be593 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 07:14:33 +0000 Subject: [PATCH] reformat converted VHDL --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 84 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 2065 ++++++++++++++------------- FPGA_Quartus_13.1/Video/video.vhd | 1261 ++++++++-------- FPGA_Quartus_13.1/firebee1.qsf | 364 ++--- FPGA_Quartus_13.1/firebee1.sdc | 24 +- 5 files changed, 1998 insertions(+), 1800 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index f8ae6ec..bc65c0b 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -15,45 +15,47 @@ CONSTANT FIFO_HWM = 500; SUBDESIGN ddr_ctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - CLR_FIFO : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ADR[31..0] : INPUT; - BLITTER_SIG : INPUT; - BLITTER_WR : INPUT; - DDRCLK0 : INPUT; - CLK33M : INPUT; - FIFO_MW[8..0] : INPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - SR_FIFO_WRE : OUTPUT; - SR_DDR_FB : OUTPUT; - SR_DDR_WR : OUTPUT; - SR_DDRWR_D_SEL : OUTPUT; - SR_VDMP[7..0] : OUTPUT; - VIDEO_DDR_TA : OUTPUT; - SR_BLITTER_DACK : OUTPUT; - BA[1..0] : OUTPUT; - DDRWR_D_SEL1 : OUTPUT; - VDM_SEL[3..0] : OUTPUT; - FB_AD[31..0] : BIDIR; + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + + DDRCLK0 : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + BA[1..0] : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) @@ -657,10 +659,10 @@ BEGIN VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - % FB_AD[31..24] = lpm_bustri_BYT( + FB_AD[31..24] = lpm_bustri_BYT( VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), - (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); % + (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); FB_AD[23..16] = lpm_bustri_BYT( VIDEO_BASE_L & VIDEO_BASE_L_D[] diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index be0cf87..966b0be 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -16,126 +16,219 @@ -- FIFO WATER MARK -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -Library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; -entity DDR_CTR is - --- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - Port ( - FB_ADR: in std_logic_vector(31 downto 0); - nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1, nRSTO, MAIN_CLK, - FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO: in std_logic; - VIDEO_RAM_CTR: in std_logic_vector(15 downto 0); - BLITTER_ADR: in std_logic_vector(31 downto 0); - BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M: in std_logic; - FIFO_MW: in std_logic_vector(8 downto 0); - VA: buffer std_logic_vector(12 downto 0); - nVWE, nVRAS, nVCS, VCKE, nVCAS: buffer std_logic; - FB_LE: buffer std_logic_vector(3 downto 0); - FB_VDOE: buffer std_logic_vector(3 downto 0); - SR_FIFO_WRE, SR_DDR_FB, SR_DDR_WR, SR_DDRWR_D_SEL: buffer std_logic; - SR_VDMP: buffer std_logic_vector(7 downto 0); - VIDEO_DDR_TA, SR_BLITTER_DACK: buffer std_logic; - BA: buffer std_logic_vector(1 downto 0); - DDRWR_D_SEL1: buffer std_logic; - VDM_SEL: buffer std_logic_vector(3 downto 0); - FB_AD: inout std_logic_vector(31 downto 0) +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_arith.all; +ENTITY ddr_ctr IS + PORT + ( + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + DDR_SYNC_66M : IN std_logic; + CLR_FIFO : IN std_logic; + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; + DDRCLK0 : IN std_logic; + CLK33M : IN std_logic; + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); + VA : BUFFER std_logic_vector(12 DOWNTO 0); + nVWE : BUFFER std_logic; + nVRAS : BUFFER std_logic; + nVCS : BUFFER std_logic; + VCKE : BUFFER std_logic; + nVCAS : BUFFER std_logic; + FB_LE : BUFFER std_logic_vector(3 DOWNTO 0); + FB_VDOE : BUFFER std_logic_vector(3 DOWNTO 0); + SR_FIFO_WRE : BUFFER std_logic; + SR_DDR_FB : BUFFER std_logic; + SR_DDR_WR : BUFFER std_logic; + SR_DDRWR_D_SEL : BUFFER std_logic; + SR_VDMP : BUFFER std_logic_vector(7 DOWNTO 0); + VIDEO_DDR_TA : BUFFER std_logic; + SR_BLITTER_DACK : BUFFER std_logic; + BA : BUFFER std_logic_vector(1 DOWNTO 0); + DDRWR_D_SEL1 : BUFFER std_logic; + VDM_SEL : BUFFER std_logic_vector(3 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -end DDR_CTR; +END ddr_ctr; -architecture DDR_CTR_behav of DDR_CTR is - --- START (NORMAL 8 CYCLES TOTAL = 60ns) --- CONFIG --- READ CPU UND BLITTER, --- WRITE CPU UND BLITTER --- READ FIFO --- CLOSE FIFO BANK --- REFRESH 10X7.5NS=75NS - signal FB_REGDDR_3: std_logic_vector(2 downto 0); - signal FB_REGDDR_d: std_logic_vector(2 downto 0); - signal FB_REGDDR_q: std_logic_vector(2 downto 0); - signal DDR_SM_6: std_logic_vector(5 downto 0); - signal DDR_SM_d: std_logic_vector(5 downto 0); - signal DDR_SM_q: std_logic_vector(5 downto 0); - signal FB_B: std_logic_vector(3 downto 0); - signal VA_P: std_logic_vector(12 downto 0); - signal VA_P_d: std_logic_vector(12 downto 0); - signal VA_P_q: std_logic_vector(12 downto 0); - signal BA_P: std_logic_vector(1 downto 0); - signal BA_P_d: std_logic_vector(1 downto 0); - signal BA_P_q: std_logic_vector(1 downto 0); - signal VA_S: std_logic_vector(12 downto 0); - signal VA_S_d: std_logic_vector(12 downto 0); - signal VA_S_q: std_logic_vector(12 downto 0); - signal BA_S: std_logic_vector(1 downto 0); - signal BA_S_d: std_logic_vector(1 downto 0); - signal BA_S_q: std_logic_vector(1 downto 0); - signal MCS: std_logic_vector(1 downto 0); - signal MCS_d: std_logic_vector(1 downto 0); - signal MCS_q: std_logic_vector(1 downto 0); - signal SR_VDMP_d: std_logic_vector(7 downto 0); - signal SR_VDMP_q: std_logic_vector(7 downto 0); - signal CPU_ROW_ADR: std_logic_vector(12 downto 0); - signal CPU_BA: std_logic_vector(1 downto 0); - signal CPU_COL_ADR: std_logic_vector(9 downto 0); - signal BLITTER_ROW_ADR: std_logic_vector(12 downto 0); - signal BLITTER_BA: std_logic_vector(1 downto 0); - signal BLITTER_COL_ADR: std_logic_vector(9 downto 0); - signal FIFO_ROW_ADR: std_logic_vector(12 downto 0); - signal FIFO_BA: std_logic_vector(1 downto 0); - signal FIFO_COL_ADR: std_logic_vector(9 downto 0); - signal DDR_REFRESH_CNT: std_logic_vector(10 downto 0); - signal DDR_REFRESH_CNT_d: std_logic_vector(10 downto 0); - signal DDR_REFRESH_CNT_q: std_logic_vector(10 downto 0); - signal DDR_REFRESH_SIG: std_logic_vector(3 downto 0); - signal DDR_REFRESH_SIG_d: std_logic_vector(3 downto 0); - signal DDR_REFRESH_SIG_q: std_logic_vector(3 downto 0); - signal VIDEO_BASE_L_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_L_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_L_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_X_D: std_logic_vector(2 downto 0); - signal VIDEO_BASE_X_D_d: std_logic_vector(2 downto 0); - signal VIDEO_BASE_X_D_q: std_logic_vector(2 downto 0); - signal VIDEO_ADR_CNT: std_logic_vector(22 downto 0); - signal VIDEO_ADR_CNT_d: std_logic_vector(22 downto 0); - signal VIDEO_ADR_CNT_q: std_logic_vector(22 downto 0); - signal VIDEO_BASE_ADR: std_logic_vector(22 downto 0); - signal VIDEO_ACT_ADR: std_logic_vector(26 downto 0); - signal u0_data: std_logic_vector(7 downto 0); - signal u0_tridata: std_logic_vector(7 downto 0); - signal FB_REGDDR_0_clk_ctrl, SR_VDMP0_clk_ctrl, MCS0_clk_ctrl, - VA_S0_clk_ctrl, BA_S0_clk_ctrl, VA_P0_clk_ctrl, BA_P0_clk_ctrl, - DDR_SM_0_clk_ctrl, VIDEO_ADR_CNT0_clk_ctrl, VIDEO_ADR_CNT0_ena_ctrl, - DDR_REFRESH_CNT0_clk_ctrl, DDR_REFRESH_SIG0_clk_ctrl, - DDR_REFRESH_SIG0_ena_ctrl, VIDEO_BASE_L_D0_clk_ctrl, - VIDEO_BASE_L_D0_ena_ctrl, VIDEO_BASE_M_D0_clk_ctrl, - VIDEO_BASE_M_D0_ena_ctrl, VIDEO_BASE_H_D0_clk_ctrl, - VIDEO_BASE_H_D0_ena_ctrl, VIDEO_BASE_X_D0_clk_ctrl, - VIDEO_BASE_X_D0_ena_ctrl, VA12_2, VA12_1, VA11_2, VA11_1, VA10_2, - VA10_1, VA9_2, VA9_1, VA8_2, VA8_1, VA7_2, VA7_1, VA6_2, VA6_1, VA5_2, - VA5_1, VA4_2, VA4_1, VA3_2, VA3_1, VA2_2, VA2_1, VA1_2, VA1_1, VA0_2, - VA0_1, BA1_2, BA1_1, BA0_2, BA0_1, BUS_CYC_d_2, BUS_CYC_d_1, - FIFO_BANK_OK_d_2, FIFO_BANK_OK_d_1, u0_enabledt, gnd, vcc, - VIDEO_CNT_H, VIDEO_CNT_M, VIDEO_CNT_L, VIDEO_BASE_H, VIDEO_BASE_M, - VIDEO_BASE_L, REFRESH_TIME_q, REFRESH_TIME_clk, REFRESH_TIME_d, - REFRESH_TIME, DDR_REFRESH_REQ_q, DDR_REFRESH_REQ_clk, - DDR_REFRESH_REQ_d, DDR_REFRESH_REQ, DDR_REFRESH_ON, FIFO_BANK_NOT_OK, - FIFO_BANK_OK_q, FIFO_BANK_OK_clk, FIFO_BANK_OK_d, FIFO_BANK_OK, - SR_FIFO_WRE_q, SR_FIFO_WRE_clk, SR_FIFO_WRE_d, STOP_q, STOP_clk, - STOP_d, STOP, CLEAR_FIFO_CNT_q, CLEAR_FIFO_CNT_clk, CLEAR_FIFO_CNT_d, - CLEAR_FIFO_CNT, CLR_FIFO_SYNC_q, CLR_FIFO_SYNC_clk, CLR_FIFO_SYNC_d, - CLR_FIFO_SYNC, FIFO_ACTIVE, FIFO_AC_q, FIFO_AC_clk, FIFO_AC_d, - FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, +ARCHITECTURE rtl OF ddr_ctr IS + -- START (NORMAL 8 CYCLES TOTAL = 60ns) + -- CONFIG + -- READ CPU UND BLITTER, + -- WRITE CPU UND BLITTER + -- READ FIFO + -- CLOSE FIFO BANK + -- REFRESH 10X7.5NfS=75NS + SIGNAL FB_REGDDR_3 : std_logic_vector(2 DOWNTO 0); + SIGNAL FB_REGDDR_d : std_logic_vector(2 DOWNTO 0); + SIGNAL FB_REGDDR_q : std_logic_vector(2 DOWNTO 0); + SIGNAL DDR_SM_6 : std_logic_vector(5 DOWNTO 0); + SIGNAL DDR_SM_d : std_logic_vector(5 DOWNTO 0); + SIGNAL DDR_SM_q : std_logic_vector(5 DOWNTO 0); + SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); + SIGNAL VA_P : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_P_d : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_P_q : std_logic_vector(12 DOWNTO 0); + SIGNAL BA_P : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_P_d : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_P_q : std_logic_vector(1 DOWNTO 0); + SIGNAL VA_S : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_S_d : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_S_q : std_logic_vector(12 DOWNTO 0); + SIGNAL BA_S : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_S_d : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_S_q : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS_d : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS_q : std_logic_vector(1 DOWNTO 0); + SIGNAL SR_VDMP_d : std_logic_vector(7 DOWNTO 0); + SIGNAL SR_VDMP_q : std_logic_vector(7 DOWNTO 0); + SIGNAL CPU_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL CPU_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL CPU_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL BLITTER_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL BLITTER_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL BLITTER_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL FIFO_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL FIFO_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL FIFO_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT_d : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT_q : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG : std_logic_vector(3 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG_d : std_logic_vector(3 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG_q : std_logic_vector(3 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D_d : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D_q : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT_d : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT_q : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_BASE_ADR : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ACT_ADR : std_logic_vector(26 DOWNTO 0); + SIGNAL u0_data : std_logic_vector(7 DOWNTO 0); + SIGNAL u0_tridata : std_logic_vector(7 DOWNTO 0); + SIGNAL FB_REGDDR_0_clk_ctrl : std_logic; + SIGNAL SR_VDMP0_clk_ctrl : std_logic; + SIGNAL MCS0_clk_ctrl : std_logic; + SIGNAL VA_S0_clk_ctrl : std_logic; + SIGNAL BA_S0_clk_ctrl : std_logic; + SIGNAL VA_P0_clk_ctrl : std_logic; + SIGNAL BA_P0_clk_ctrl : std_logic; + SIGNAL DDR_SM_0_clk_ctrl : std_logic; + SIGNAL VIDEO_ADR_CNT0_clk_ctrl : std_logic; + SIGNAL VIDEO_ADR_CNT0_ena_ctrl : std_logic; + SIGNAL DDR_REFRESH_CNT0_clk_ctrl : std_logic; + SIGNAL DDR_REFRESH_SIG0_clk_ctrl : std_logic; + SIGNAL DDR_REFRESH_SIG0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_L_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_L_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_M_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_M_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_H_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_H_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_X_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_X_D0_ena_ctrl : std_logic; + SIGNAL VA12_2 : std_logic; + SIGNAL VA12_1 : std_logic; + SIGNAL VA11_2 : std_logic; + SIGNAL VA11_1 : std_logic; + SIGNAL VA10_2 : std_logic; + SIGNAL VA10_1 : std_logic; + SIGNAL VA9_2 : std_logic; + SIGNAL VA9_1 : std_logic; + SIGNAL VA8_2 : std_logic; + SIGNAL VA8_1 : std_logic; + SIGNAL VA7_2 : std_logic; + SIGNAL VA7_1 : std_logic; + SIGNAL VA6_2 : std_logic; + SIGNAL VA6_1 : std_logic; + SIGNAL VA5_2 : std_logic; + SIGNAL VA5_1 : std_logic; + SIGNAL VA4_2 : std_logic; + SIGNAL VA4_1 : std_logic; + SIGNAL VA3_2 : std_logic; + SIGNAL VA3_1 : std_logic; + SIGNAL VA2_2 : std_logic; + SIGNAL VA2_1 : std_logic; + SIGNAL VA1_2 : std_logic; + SIGNAL VA1_1 : std_logic; + SIGNAL VA0_2 : std_logic; + SIGNAL VA0_1 : std_logic; + SIGNAL BA1_2 : std_logic; + SIGNAL BA1_1 : std_logic; + SIGNAL BA0_2 : std_logic; + SIGNAL BA0_1 : std_logic; + SIGNAL BUS_CYC_d_2 : std_logic; + SIGNAL BUS_CYC_d_1 : std_logic; + SIGNAL FIFO_BANK_OK_d_2 : std_logic; + SIGNAL FIFO_BANK_OK_d_1 : std_logic; + SIGNAL u0_enabledt : std_logic; + SiGNAL gnd : std_logic; + SIGNAL vcc : std_logic; + SIGNAL VIDEO_CNT_H : std_logic; + SIGNAL VIDEO_CNT_M : std_logic; + SIGNAL VIDEO_CNT_L : std_logic; + SIGNAL VIDEO_BASE_H : std_logic; + SIGNAL VIDEO_BASE_M : std_logic; + SIGNAL VIDEO_BASE_L : std_logic; + SIGNAL REFRESH_TIME_q : std_logic; + SIGNAL REFRESH_TIME_clk : std_logic; + SIGNAL REFRESH_TIME_d : std_logic; + SIGNAL REFRESH_TIME : std_logic; + SIGNAL DDR_REFRESH_REQ_q : std_logic; + SIGNAL DDR_REFRESH_REQ_clk : std_logic; + SIGNAL DDR_REFRESH_REQ_d : std_logic; + SIGNAL DDR_REFRESH_REQ : std_logic; + SIGNAL DDR_REFRESH_ON : std_logic; + SIGNAL FIFO_BANK_NOT_OK : std_logic; + SIGNAL FIFO_BANK_OK_q : std_logic; + SIGNAL FIFO_BANK_OK_clk : std_logic; + SIGNAL FIFO_BANK_OK_d : std_logic; + SIGNAL FIFO_BANK_OK : std_logic; + SiGNAL SR_FIFO_WRE_q : std_logic; + SIGNAL SR_FIFO_WRE_clk : std_logic; + SIGNAL SR_FIFO_WRE_d : std_logic; + SIGNAL STOP_q : std_logic; + SIGNAL STOP_clk : std_logic; + SIGNAL STOP_d : std_logic; + SIGNAL STOP : std_logic; + SIGNAL CLEAR_FIFO_CNT_q : std_logic; + SIGNAL CLEAR_FIFO_CNT_clk : std_logic; + SIGNAL CLEAR_FIFO_CNT_d : std_logic; + SIGNAL CLEAR_FIFO_CNT : std_logic; + SIGNAL CLR_FIFO_SYNC_q : std_logic; + SIGNAL CLR_FIFO_SYNC_clk : std_logic; + SIGNAL CLR_FIFO_SYNC_d : std_logic; + SIGNAL CLR_FIFO_SYNC : std_logic; + SIGNAL FIFO_ACTIVE : std_logic; + SIGNAL FIFO_AC_q : std_logic; + SIGNAL FIFO_AC_clk : std_logic; + SIGNAL FIFO_AC_d : std_logic; + SIGNAL FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, BLITTER_AC_clk, BLITTER_AC_d, BLITTER_AC, BLITTER_REQ_q, BLITTER_REQ_clk, BLITTER_REQ_d, BLITTER_REQ, BUS_CYC_END, BUS_CYC_q, BUS_CYC_clk, BUS_CYC_d, BUS_CYC, CPU_AC_q, CPU_AC_clk, CPU_AC_d, @@ -151,26 +244,26 @@ architecture DDR_CTR_behav of DDR_CTR is component lpm_bustri_BYT Port ( - data: in std_logic_vector(7 downto 0); + data: in std_logic_vector(7 DOWNTO 0); enabledt: in std_logic; - tridata: buffer std_logic_vector(7 downto 0) + tridata: buffer std_logic_vector(7 DOWNTO 0) ); - end component; + END component; - Function to_std_logic(X: in Boolean) return Std_Logic is - variable ret : std_logic; - begin - if x then ret := '1'; else ret := '0'; end if; + Function to_std_logic(X: in Boolean) return Std_Logic IS + VARIABLE ret : std_logic; + BEGIN + IF x THEN ret := '1'; ELSE ret := '0'; END IF; return ret; - end to_std_logic; + END to_std_logic; -- sizeIt replicates a value to an array of specific length. - Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is - variable rep: std_logic_vector( len-1 downto 0); - begin for i in rep'range loop rep(i) := a; end loop; return rep; - end sizeIt; -begin + Function sizeIt(a: std_Logic; len: integer) return std_logic_vector IS + VARIABLE rep: std_logic_vector( len-1 DOWNTO 0); + BEGIN for i in rep'range loop rep(i) := a; END loop; return rep; + END sizeIt; +BEGIN -- Sub Module Section u0: lpm_bustri_BYT port map (data=>u0_data, enabledt=>u0_enabledt, @@ -179,220 +272,220 @@ begin -- Register Section SR_FIFO_WRE <= SR_FIFO_WRE_q; - process (SR_FIFO_WRE_clk) begin - if SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' then + PROCESS (SR_FIFO_WRE_clk) BEGIN + IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN SR_FIFO_WRE_q <= SR_FIFO_WRE_d; - end if; - end process; + END IF; + END PROCESS; SR_DDR_WR <= SR_DDR_WR_q; - process (SR_DDR_WR_clk) begin - if SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' then + PROCESS (SR_DDR_WR_clk) BEGIN + IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN SR_DDR_WR_q <= SR_DDR_WR_d; - end if; - end process; + END IF; + END PROCESS; SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; - process (SR_DDRWR_D_SEL_clk) begin - if SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' then + PROCESS (SR_DDRWR_D_SEL_clk) BEGIN + IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; - end if; - end process; + END IF; + END PROCESS; SR_VDMP <= SR_VDMP_q; - process (SR_VDMP0_clk_ctrl) begin - if SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' then + PROCESS (SR_VDMP0_clk_ctrl) BEGIN + IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN SR_VDMP_q <= SR_VDMP_d; - end if; - end process; + END IF; + END PROCESS; - process (FB_REGDDR_0_clk_ctrl) begin - if FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' then + PROCESS (FB_REGDDR_0_clk_ctrl) BEGIN + IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN FB_REGDDR_q <= FB_REGDDR_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_SM_0_clk_ctrl) begin - if DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' then + PROCESS (DDR_SM_0_clk_ctrl) BEGIN + IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN DDR_SM_q <= DDR_SM_d; - end if; - end process; + END IF; + END PROCESS; - process (VA_P0_clk_ctrl) begin - if VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' then + PROCESS (VA_P0_clk_ctrl) BEGIN + IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN VA_P_q <= VA_P_d; - end if; - end process; + END IF; + END PROCESS; - process (BA_P0_clk_ctrl) begin - if BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' then + PROCESS (BA_P0_clk_ctrl) BEGIN + IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN BA_P_q <= BA_P_d; - end if; - end process; + END IF; + END PROCESS; - process (VA_S0_clk_ctrl) begin - if VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' then + PROCESS (VA_S0_clk_ctrl) BEGIN + IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN VA_S_q <= VA_S_d; - end if; - end process; + END IF; + END PROCESS; - process (BA_S0_clk_ctrl) begin - if BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' then + PROCESS (BA_S0_clk_ctrl) BEGIN + IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN BA_S_q <= BA_S_d; - end if; - end process; + END IF; + END PROCESS; - process (MCS0_clk_ctrl) begin - if MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' then + PROCESS (MCS0_clk_ctrl) BEGIN + IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN MCS_q <= MCS_d; - end if; - end process; + END IF; + END PROCESS; - process (CPU_DDR_SYNC_clk) begin - if CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' then + PROCESS (CPU_DDR_SYNC_clk) BEGIN + IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_CS_clk) begin - if DDR_CS_clk'event and DDR_CS_clk='1' then - if DDR_CS_ena='1' then + PROCESS (DDR_CS_clk) BEGIN + IF DDR_CS_clk'event and DDR_CS_clk='1' THEN + IF DDR_CS_ena='1' THEN DDR_CS_q <= DDR_CS_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (CPU_REQ_clk) begin - if CPU_REQ_clk'event and CPU_REQ_clk='1' then + PROCESS (CPU_REQ_clk) BEGIN + IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN CPU_REQ_q <= CPU_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (CPU_AC_clk) begin - if CPU_AC_clk'event and CPU_AC_clk='1' then + PROCESS (CPU_AC_clk) BEGIN + IF CPU_AC_clk'event and CPU_AC_clk='1' THEN CPU_AC_q <= CPU_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (BUS_CYC_clk) begin - if BUS_CYC_clk'event and BUS_CYC_clk='1' then + PROCESS (BUS_CYC_clk) BEGIN + IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN BUS_CYC_q <= BUS_CYC_d; - end if; - end process; + END IF; + END PROCESS; - process (BLITTER_REQ_clk) begin - if BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' then + PROCESS (BLITTER_REQ_clk) BEGIN + IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN BLITTER_REQ_q <= BLITTER_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (BLITTER_AC_clk) begin - if BLITTER_AC_clk'event and BLITTER_AC_clk='1' then + PROCESS (BLITTER_AC_clk) BEGIN + IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN BLITTER_AC_q <= BLITTER_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_REQ_clk) begin - if FIFO_REQ_clk'event and FIFO_REQ_clk='1' then + PROCESS (FIFO_REQ_clk) BEGIN + IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN FIFO_REQ_q <= FIFO_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_AC_clk) begin - if FIFO_AC_clk'event and FIFO_AC_clk='1' then + PROCESS (FIFO_AC_clk) BEGIN + IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN FIFO_AC_q <= FIFO_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (CLR_FIFO_SYNC_clk) begin - if CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' then + PROCESS (CLR_FIFO_SYNC_clk) BEGIN + IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; - end if; - end process; + END IF; + END PROCESS; - process (CLEAR_FIFO_CNT_clk) begin - if CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' then + PROCESS (CLEAR_FIFO_CNT_clk) BEGIN + IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; - end if; - end process; + END IF; + END PROCESS; - process (STOP_clk) begin - if STOP_clk'event and STOP_clk='1' then + PROCESS (STOP_clk) BEGIN + IF STOP_clk'event and STOP_clk='1' THEN STOP_q <= STOP_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_BANK_OK_clk) begin - if FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' then + PROCESS (FIFO_BANK_OK_clk) BEGIN + IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN FIFO_BANK_OK_q <= FIFO_BANK_OK_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_CNT0_clk_ctrl) begin - if DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' then + PROCESS (DDR_REFRESH_CNT0_clk_ctrl) BEGIN + IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_REQ_clk) begin - if DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' then + PROCESS (DDR_REFRESH_REQ_clk) BEGIN + IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_SIG0_clk_ctrl) begin - if DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' then - if DDR_REFRESH_SIG0_ena_ctrl='1' then + PROCESS (DDR_REFRESH_SIG0_clk_ctrl) BEGIN + IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN + IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (REFRESH_TIME_clk) begin - if REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' then + PROCESS (REFRESH_TIME_clk) BEGIN + IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN REFRESH_TIME_q <= REFRESH_TIME_d; - end if; - end process; + END IF; + END PROCESS; - process (VIDEO_BASE_L_D0_clk_ctrl) begin - if VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' then - if VIDEO_BASE_L_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_L_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_M_D0_clk_ctrl) begin - if VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' then - if VIDEO_BASE_M_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_M_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_H_D0_clk_ctrl) begin - if VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' then - if VIDEO_BASE_H_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_H_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_X_D0_clk_ctrl) begin - if VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' then - if VIDEO_BASE_X_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_X_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_ADR_CNT0_clk_ctrl) begin - if VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' then - if VIDEO_ADR_CNT0_ena_ctrl='1' then + PROCESS (VIDEO_ADR_CNT0_clk_ctrl) BEGIN + IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN + IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; -- Start of original equations LINE <= FB_SIZE0 and FB_SIZE1; @@ -400,25 +493,25 @@ begin -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and + FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not + FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and + FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not + FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); @@ -426,741 +519,737 @@ begin FB_REGDDR_0_clk_ctrl <= MAIN_CLK; - process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, - DDR_CONFIG, nFB_WR, vcc) - variable stdVec3: std_logic_vector(2 downto 0); - begin - FB_REGDDR_d <= FB_REGDDR_q; - (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); - (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), - VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); - stdVec3 := FB_REGDDR_q; - case stdVec3 is - when "000" => - FB_LE(0) <= not nFB_WR; + PROCESS (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) + VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); + BEGIN + FB_REGDDR_d <= FB_REGDDR_q; + (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); + (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), + VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); + stdVec3 := FB_REGDDR_q; + CASE stdVec3 IS + WHEN "000" => + FB_LE(0) <= not nFB_WR; + -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' THEN + FB_REGDDR_d <= "001"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "001" => + IF (DDR_CS_q)='1' THEN + FB_LE(0) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + IF (LINE)='1' THEN + FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); + FB_REGDDR_d <= "010"; + ELSE + BUS_CYC_END <= vcc; + FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); + FB_REGDDR_d <= "000"; + END IF; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "010" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(1) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "011"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "011" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(2) <= not nFB_WR; --- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' then - FB_REGDDR_d <= "001"; - else - FB_REGDDR_d <= "000"; - end if; - when "001" => - if (DDR_CS_q)='1' then - FB_LE(0) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - if (LINE)='1' then - FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); - FB_REGDDR_d <= "010"; - else - BUS_CYC_END <= vcc; - FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not - DDR_CONFIG); - FB_REGDDR_d <= "000"; - end if; - else - FB_REGDDR_d <= "000"; - end if; - when "010" => - if (DDR_CS_q)='1' then - FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(1) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - FB_REGDDR_d <= "011"; - else - FB_REGDDR_d <= "000"; - end if; - when "011" => - if (DDR_CS_q)='1' then - FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(2) <= not nFB_WR; + -- BEI LINE WRITE EVT. WARTEN + IF ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' THEN + FB_REGDDR_d <= "011"; + ELSE + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "100"; + END IF; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "100" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); + FB_LE(3) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + BUS_CYC_END <= vcc; + FB_REGDDR_d <= "000"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN others => + END CASE; + stdVec3 := (others=>'0'); -- no storage needed + END PROCESS; --- BEI LINE WRITE EVT. WARTEN - if ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' then - FB_REGDDR_d <= "011"; - else - VIDEO_DDR_TA <= vcc; - FB_REGDDR_d <= "100"; - end if; - else - FB_REGDDR_d <= "000"; - end if; - when "100" => - if (DDR_CS_q)='1' then - FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_LE(3) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - BUS_CYC_END <= vcc; - FB_REGDDR_d <= "000"; - else - FB_REGDDR_d <= "000"; - end if; - when others => - end case; - stdVec3 := (others=>'0'); -- no storage needed - end process; + -- DDR STEUERUNG ----------------------------------------------------- + -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE <= VIDEO_RAM_CTR(0); + nVCS <= not VIDEO_RAM_CTR(1); + DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); + DDR_CONFIG <= VIDEO_RAM_CTR(3); + FIFO_ACTIVE <= VIDEO_RAM_CTR(8); --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE <= VIDEO_RAM_CTR(0); - nVCS <= not VIDEO_RAM_CTR(1); - DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); - DDR_CONFIG <= VIDEO_RAM_CTR(3); - FIFO_ACTIVE <= VIDEO_RAM_CTR(8); + -- ------------------------------ + CPU_ROW_ADR <= FB_ADR(26 DOWNTO 14); + CPU_BA <= FB_ADR(13 DOWNTO 12); + CPU_COL_ADR <= FB_ADR(11 DOWNTO 2); + nVRAS <= not VRAS; + nVCAS <= not VCAS; + nVWE <= not VWE; + SR_DDR_WR_clk <= DDRCLK0; + SR_DDRWR_D_SEL_clk <= DDRCLK0; + SR_VDMP0_clk_ctrl <= DDRCLK0; + SR_FIFO_WRE_clk <= DDRCLK0; + CPU_AC_clk <= DDRCLK0; + FIFO_AC_clk <= DDRCLK0; + BLITTER_AC_clk <= DDRCLK0; + DDRWR_D_SEL1 <= BLITTER_AC_q; --- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 downto 14); - CPU_BA <= FB_ADR(13 downto 12); - CPU_COL_ADR <= FB_ADR(11 downto 2); - nVRAS <= not VRAS; - nVCAS <= not VCAS; - nVWE <= not VWE; - SR_DDR_WR_clk <= DDRCLK0; - SR_DDRWR_D_SEL_clk <= DDRCLK0; - SR_VDMP0_clk_ctrl <= DDRCLK0; - SR_FIFO_WRE_clk <= DDRCLK0; - CPU_AC_clk <= DDRCLK0; - FIFO_AC_clk <= DDRCLK0; - BLITTER_AC_clk <= DDRCLK0; - DDRWR_D_SEL1 <= BLITTER_AC_q; + -- SELECT LOGIC + DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 DOWNTO 30) = "01"); + DDR_CS_clk <= MAIN_CLK; + DDR_CS_ena <= FB_ALE; + DDR_CS_d <= DDR_SEL; --- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); - DDR_CS_clk <= MAIN_CLK; - DDR_CS_ena <= FB_ALE; - DDR_CS_d <= DDR_SEL; + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + -- CONFIG SOFORT LOS + -- LINE WRITE SPÄTER + CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or + (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and (not nFB_WR)); + CPU_REQ_clk <= DDR_SYNC_66M; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER --- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG --- CONFIG SOFORT LOS --- LINE WRITE SPÄTER - CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or - (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and - (not nFB_WR)); - CPU_REQ_clk <= DDR_SYNC_66M; - --- HALTEN BUS CYC BEGONNEN ODER FERTIG - CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" + -- HALTEN BUS CYC BEGONNEN ODER FERTIG + CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); - BUS_CYC_clk <= DDRCLK0; - BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); + BUS_CYC_clk <= DDRCLK0; + BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); --- STATE MACHINE SYNCHRONISIEREN ----------------- - MCS0_clk_ctrl <= DDRCLK0; - MCS_d(0) <= MAIN_CLK; - MCS_d(1) <= MCS_q(0); - CPU_DDR_SYNC_clk <= DDRCLK0; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS0_clk_ctrl <= DDRCLK0; + MCS_d(0) <= MAIN_CLK; + MCS_d(1) <= MCS_q(0); + CPU_DDR_SYNC_clk <= DDRCLK0; --- NUR 1 WENN EIN - CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); + -- NUR 1 WENN EIN + CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); --- ------------------------------------------------- - VA_S0_clk_ctrl <= DDRCLK0; - BA_S0_clk_ctrl <= DDRCLK0; - (VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1, VA3_1, + -- ------------------------------------------------- + VA_S0_clk_ctrl <= DDRCLK0; + BA_S0_clk_ctrl <= DDRCLK0; + (VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1, VA3_1, VA2_1, VA1_1, VA0_1) <= VA_S_q; - (BA1_1, BA0_1) <= BA_S_q; - VA_P0_clk_ctrl <= DDRCLK0; - BA_P0_clk_ctrl <= DDRCLK0; + (BA1_1, BA0_1) <= BA_S_q; + VA_P0_clk_ctrl <= DDRCLK0; + BA_P0_clk_ctrl <= DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM_0_clk_ctrl <= DDRCLK0; + -- DDR STATE MACHINE ----------------------------------------------- + DDR_SM_0_clk_ctrl <= DDRCLK0; - process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, + PROCESS (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, DDR_REFRESH_SIG_q, vcc) - variable stdVec6: std_logic_vector(5 downto 0); - begin - DDR_SM_d <= DDR_SM_q; - BA_S_d <= "00"; - VA_S_d <= "0000000000000"; - BA_P_d <= "00"; - (VA_P_d(9), VA_P_d(8), VA_P_d(7), VA_P_d(6), VA_P_d(5), VA_P_d(4), - VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= - std_logic_vector'("00000000000"); - SR_VDMP_d <= "00000000"; - VA_P_d(12 downto 11) <= "00"; - (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, + VARIABLE stdVec6: std_logic_vector(5 DOWNTO 0); + BEGIN + DDR_SM_d <= DDR_SM_q; + BA_S_d <= "00"; + VA_S_d <= "0000000000000"; + BA_P_d <= "00"; + (VA_P_d(9), VA_P_d(8), VA_P_d(7), VA_P_d(6), VA_P_d(5), VA_P_d(4), + VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= + std_logic_vector'("00000000000"); + SR_VDMP_d <= "00000000"; + VA_P_d(12 DOWNTO 11) <= "00"; + (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, FIFO_BANK_NOT_OK, VCAS, VRAS) <= std_logic_vector'("00000000000000000000000000000"); - stdVec6 := DDR_SM_q; - case stdVec6 is - when "000000" => - if (DDR_REFRESH_REQ_q)='1' then - DDR_SM_d <= "011111"; - --- SYNCHRON UND EIN? - elsif (CPU_DDR_SYNC_q)='1' then - --- JA - if (DDR_CONFIG)='1' then - DDR_SM_d <= "001000"; - --- BEI WAIT UND LINE WRITE - elsif (CPU_REQ_q)='1' then - VA_S_d <= CPU_ROW_ADR; - BA_S_d <= CPU_BA; - CPU_AC_d <= vcc; - BUS_CYC_d_2 <= vcc; - DDR_SM_d <= "000010"; - else - --- FIFO IST DEFAULT - if (FIFO_REQ_q or (not BLITTER_REQ_q))='1' then - VA_P_d <= FIFO_ROW_ADR; - BA_P_d <= FIFO_BA; - --- VORBESETZEN - FIFO_AC_d <= vcc; - else - VA_P_d <= BLITTER_ROW_ADR; - BA_P_d <= BLITTER_BA; - --- VORBESETZEN - BLITTER_AC_d <= vcc; - end if; - DDR_SM_d <= "000001"; - end if; - else - --- NEIN ->SYNCHRONISIEREN - DDR_SM_d <= "000000"; - end if; - when "000001" => - --- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - if (DDR_SEL and (nFB_WR or (not LINE)))='1' then - VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); - --- AUTO PRECHARGE DA NICHT FIFO PAGE - VA_S_d(10) <= vcc; - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - else - VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and - BLITTER_REQ_q); - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; - (BA1_2, BA0_2) <= BA_P_q; - VA_S_d(10) <= not (FIFO_AC_q and FIFO_REQ_q); - FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; - FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; - BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; - end if; - DDR_SM_d <= "000011"; - when "000010" => - VRAS <= vcc; - FIFO_BANK_NOT_OK <= vcc; - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - DDR_SM_d <= "000011"; - when "000011" => - CPU_AC_d <= CPU_AC_q; - FIFO_AC_d <= FIFO_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - if (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' - then - DDR_SM_d <= "010000"; - --- CPU? - elsif (CPU_AC_q)='1' then - VA_S_d(9 downto 0) <= CPU_COL_ADR; - BA_S_d <= CPU_BA; - DDR_SM_d <= "001110"; - --- FIFO? - elsif (FIFO_AC_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "010110"; - elsif (BLITTER_AC_q)='1' then - VA_S_d(9 downto 0) <= BLITTER_COL_ADR; - BA_S_d <= BLITTER_BA; - DDR_SM_d <= "001110"; - else - --- READ - DDR_SM_d <= "000111"; - end if; - when "001110" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; - --- READ DATEN FÜR CPU - SR_DDR_FB <= CPU_AC_q; - --- BLITTER DACK AND BLITTER LATCH DATEN - SR_BLITTER_DACK <= BLITTER_AC_q; - DDR_SM_d <= "001111"; - when "001111" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- FIFO READ EINSCHIEBEN WENN BANK OK - if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - --- MANUELL PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- WRITE - DDR_SM_d <= "011101"; - end if; - when "010000" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- BLITTER ACK AND BLITTER LATCH DATEN - SR_BLITTER_DACK <= BLITTER_AC_q; - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - DDR_SM_d <= "010001"; - when "010001" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VA_S_d(9 downto 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or - (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or - (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); - --- BYTE ENABLE WRITE - SR_VDMP_d(7 downto 4) <= FB_B; - --- LINE ENABLE WRITE - SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; - DDR_SM_d <= "010010"; - when "010010" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; - VWE <= vcc; - --- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDR_WR_d <= vcc; - --- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; - --- WENN LINE DANN ACTIV - SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; - DDR_SM_d <= "010011"; - when "010011" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDR_WR_d <= vcc; - --- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; - DDR_SM_d <= "010100"; - when "010100" => - DDR_SM_d <= "010101"; - when "010101" => - if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- FIFO READ - DDR_SM_d <= "011101"; - end if; - when "010110" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - DDR_SM_d <= "010111"; - when "010111" => - if (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - else - VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - end if; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- NOCH OFFEN LASSEN - DDR_SM_d <= "011101"; - end if; - when "011000" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - DDR_SM_d <= "011001"; - when "011001" => - if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then - --- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - elsif (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - else - VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011010"; - end if; - else - --- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - end if; - when "011010" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - --- NOTFALL? - if (unsigned(FIFO_MW) < unsigned'("000000000")) then - --- JA-> - DDR_SM_d <= "010111"; - else - DDR_SM_d <= "011011"; - end if; - when "011011" => - if (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - else - VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_P_d(10) <= gnd; - BA_P_d <= FIFO_BA; - DDR_SM_d <= "011100"; - end if; - else - --- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - end if; - when "011100" => - if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= - FIFO_BA then - VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - --- AUTO PRECHARGE DA NICHT FIFO BANK - VA_S_d(10) <= vcc; - DDR_SM_d <= "000011"; - else - VCAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; - (BA1_2, BA0_2) <= BA_P_q; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - --- CONFIG CYCLUS - DDR_SM_d <= "011001"; - end if; - when "001000" => - DDR_SM_d <= "001001"; - when "001001" => - BUS_CYC_d_2 <= CPU_REQ_q; - DDR_SM_d <= "001010"; - when "001010" => - if (CPU_REQ_q)='1' then - DDR_SM_d <= "001011"; - else - DDR_SM_d <= "000000"; - end if; - when "001011" => - DDR_SM_d <= "001100"; - when "001100" => - VA_S_d <= FB_AD(12 downto 0); - BA_S_d <= FB_AD(14 downto 13); - DDR_SM_d <= "001101"; - when "001101" => - --- NUR BEI LONG WRITE - VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- NUR BEI LONG WRITE - VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- NUR BEI LONG WRITE - VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- CLOSE FIFO BANK - DDR_SM_d <= "000111"; - when "011101" => - --- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; - --- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - DDR_SM_d <= "000110"; - when "011110" => - --- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; - --- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - --- REFRESH 70NS = 10 ZYCLEN - DDR_SM_d <= "000000"; - when "011111" => - --- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - if DDR_REFRESH_SIG_q = "1001" then - --- ALLE BANKS SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - VA10_2 <= vcc; - FIFO_BANK_NOT_OK <= vcc; - DDR_SM_d <= "100001"; - else - VCAS <= vcc; - VRAS <= vcc; - DDR_SM_d <= "100000"; - end if; - when "100000" => - DDR_SM_d <= "100001"; - when "100001" => - DDR_SM_d <= "100010"; - when "100010" => - DDR_SM_d <= "100011"; - when "100011" => - --- LEERSCHLAUFE - DDR_SM_d <= "000100"; - when "000100" => - DDR_SM_d <= "000101"; - when "000101" => - DDR_SM_d <= "000110"; - when "000110" => - DDR_SM_d <= "000111"; - when "000111" => - DDR_SM_d <= "000000"; - when others => - end case; - stdVec6 := (others=>'0'); -- no storage needed - end process; - --- ------------------------------------------------------------- --- BLITTER ---------------------- --- --------------------------------------- - BLITTER_REQ_clk <= DDRCLK0; - BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); - BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); - BLITTER_BA(1) <= BLITTER_ADR(13); - BLITTER_BA(0) <= BLITTER_ADR(12); - BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); - --- ---------------------------------------------------------------------------- --- FIFO --------------------------------- --- ------------------------------------------------------ - FIFO_REQ_clk <= DDRCLK0; - FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or + stdVec6 := DDR_SM_q; + + CASE stdVec6 IS + WHEN "000000" => + IF (DDR_REFRESH_REQ_q)='1' THEN + DDR_SM_d <= "011111"; + -- SYNCHRON UND EIN? + ELSIF (CPU_DDR_SYNC_q)='1' THEN + -- JA + IF (DDR_CONFIG)='1' THEN + DDR_SM_d <= "001000"; + -- BEI WAIT UND LINE WRITE + ELSIF (CPU_REQ_q)='1' THEN + VA_S_d <= CPU_ROW_ADR; + BA_S_d <= CPU_BA; + CPU_AC_d <= vcc; + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000010"; + ELSE + -- FIFO IST DEFAULT + IF (FIFO_REQ_q or (not BLITTER_REQ_q))='1' THEN + VA_P_d <= FIFO_ROW_ADR; + BA_P_d <= FIFO_BA; + -- VORBESETZEN + FIFO_AC_d <= vcc; + ELSE + VA_P_d <= BLITTER_ROW_ADR; + BA_P_d <= BLITTER_BA; + -- VORBESETZEN + BLITTER_AC_d <= vcc; + END IF; + DDR_SM_d <= "000001"; + END IF; + ELSE + -- NEIN ->SYNCHRONISIEREN + DDR_SM_d <= "000000"; + END IF; + + WHEN "000001" => + -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF (DDR_SEL and (nFB_WR or (not LINE)))='1' THEN + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); + (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + -- AUTO PRECHARGE DA NICHT FIFO PAGE + VA_S_d(10) <= vcc; + CPU_AC_d <= vcc; + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + ELSE + VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + VA_S_d(10) <= not (FIFO_AC_q and FIFO_REQ_q); + FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; + FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; + BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; + END IF; + DDR_SM_d <= "000011"; + + WHEN "000010" => + VRAS <= vcc; + FIFO_BANK_NOT_OK <= vcc; + CPU_AC_d <= vcc; + + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000011"; + + WHEN "000011" => + CPU_AC_d <= CPU_AC_q; + FIFO_AC_d <= FIFO_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + IF (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' THEN + DDR_SM_d <= "010000"; + -- CPU? + ELSIF (CPU_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= CPU_COL_ADR; + BA_S_d <= CPU_BA; + DDR_SM_d <= "001110"; + + -- FIFO? + ELSIF (FIFO_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "010110"; + ELSIF (BLITTER_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= BLITTER_COL_ADR; + BA_S_d <= BLITTER_BA; + DDR_SM_d <= "001110"; + ELSE + -- READ + DDR_SM_d <= "000111"; + END IF; + + WHEN "001110" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + + -- READ DATEN FÜR CPU + SR_DDR_FB <= CPU_AC_q; + + -- BLITTER DACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + DDR_SM_d <= "001111"; + + WHEN "001111" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- FIFO READ EINSCHIEBEN WENN BANK OK + IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + + -- MANUELL PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + ELSE + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + -- WRITE + DDR_SM_d <= "011101"; + END IF; + + WHEN "010000" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- BLITTER ACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + DDR_SM_d <= "010001"; + + WHEN "010001" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); + + -- BYTE ENABLE WRITE + SR_VDMP_d(7 DOWNTO 4) <= FB_B; + + -- LINE ENABLE WRITE + SR_VDMP_d(3 DOWNTO 0) <= sizeIt(LINE,4) and "1111"; + DDR_SM_d <= "010010"; + + WHEN "010010" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + VWE <= vcc; + + -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDR_WR_d <= vcc; + + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + + -- WENN LINE DANN ACTIV + SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; + DDR_SM_d <= "010011"; + + WHEN "010011" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDR_WR_d <= vcc; + + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + DDR_SM_d <= "010100"; + + WHEN "010100" => + DDR_SM_d <= "010101"; + + WHEN "010101" => + IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + ELSE + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + -- FIFO READ + DDR_SM_d <= "011101"; + END IF; + + WHEN "010110" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "010111"; + + WHEN "010111" => + IF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + ELSE + VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + END IF; + ELSE + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- NOCH OFFEN LASSEN + DDR_SM_d <= "011101"; + END IF; + + WHEN "011000" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "011001"; + + WHEN "011001" => + IF CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) THEN + + -- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + ELSIF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + ELSE + VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011010"; + END IF; + ELSE + + -- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + END IF; + + WHEN "011010" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + + -- NOTFALL? + IF (unsigned(FIFO_MW) < unsigned'("000000000")) THEN + + -- JA-> + DDR_SM_d <= "010111"; + ELSE + DDR_SM_d <= "011011"; + END IF; + + WHEN "011011" => + IF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + ELSE + VA_P_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_P_d(10) <= gnd; + BA_P_d <= FIFO_BA; + DDR_SM_d <= "011100"; + END IF; + ELSE + + -- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + END IF; + + WHEN "011100" => + IF (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 DOWNTO 12) /= FIFO_BA THEN + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); + (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + CPU_AC_d <= vcc; + + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + + -- AUTO PRECHARGE DA NICHT FIFO BANK + VA_S_d(10) <= vcc; + DDR_SM_d <= "000011"; + ELSE + VCAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + + -- CONFIG CYCLUS + DDR_SM_d <= "011001"; + END IF; + + WHEN "001000" => + DDR_SM_d <= "001001"; + + WHEN "001001" => + BUS_CYC_d_2 <= CPU_REQ_q; + DDR_SM_d <= "001010"; + + WHEN "001010" => + IF (CPU_REQ_q)='1' THEN + DDR_SM_d <= "001011"; + ELSE + DDR_SM_d <= "000000"; + END IF; + + WHEN "001011" => + DDR_SM_d <= "001100"; + + WHEN "001100" => + VA_S_d <= FB_AD(12 DOWNTO 0); + BA_S_d <= FB_AD(14 DOWNTO 13); + DDR_SM_d <= "001101"; + + WHEN "001101" => + + -- NUR BEI LONG WRITE + VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- NUR BEI LONG WRITE + VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- NUR BEI LONG WRITE + VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- CLOSE FIFO BANK + DDR_SM_d <= "000111"; + + WHEN "011101" => + + -- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + + -- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + DDR_SM_d <= "000110"; + + WHEN "011110" => + -- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + + -- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + + -- REFRESH 70NS = 10 ZYCLEN + DDR_SM_d <= "000000"; + + WHEN "011111" => + + -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + IF DDR_REFRESH_SIG_q = "1001" THEN + + -- ALLE BANKS SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + VA10_2 <= vcc; + FIFO_BANK_NOT_OK <= vcc; + DDR_SM_d <= "100001"; + ELSE + VCAS <= vcc; + VRAS <= vcc; + DDR_SM_d <= "100000"; + END IF; + + WHEN "100000" => + DDR_SM_d <= "100001"; + + WHEN "100001" => + DDR_SM_d <= "100010"; + + WHEN "100010" => + DDR_SM_d <= "100011"; + + WHEN "100011" => + -- LEERSCHLAUFE + DDR_SM_d <= "000100"; + + WHEN "000100" => + DDR_SM_d <= "000101"; + + WHEN "000101" => + DDR_SM_d <= "000110"; + + WHEN "000110" => + DDR_SM_d <= "000111"; + + WHEN "000111" => + DDR_SM_d <= "000000"; + + WHEN OTHERS => + END CASE; + stdVec6 := (OTHERS => '0'); -- no storage needed + END PROCESS; + + -- ------------------------------------------------------------- + -- BLITTER ---------------------- + -- --------------------------------------- + BLITTER_REQ_clk <= DDRCLK0; + BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); + BLITTER_ROW_ADR <= BLITTER_ADR(26 DOWNTO 14); + BLITTER_BA(1) <= BLITTER_ADR(13); + BLITTER_BA(0) <= BLITTER_ADR(12); + BLITTER_COL_ADR <= BLITTER_ADR(11 DOWNTO 2); + + -- ---------------------------------------------------------------------------- + -- FIFO --------------------------------- + -- ------------------------------------------------------ + FIFO_REQ_clk <= DDRCLK0; + FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); - FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); - FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); - FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); - FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & + FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 DOWNTO 10); + FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); + FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); + FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & VIDEO_ADR_CNT_q(5) & VIDEO_ADR_CNT_q(4) & VIDEO_ADR_CNT_q(3) & VIDEO_ADR_CNT_q(2) & VIDEO_ADR_CNT_q(1) & VIDEO_ADR_CNT_q(0) & "00"); - FIFO_BANK_OK_clk <= DDRCLK0; - FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); + FIFO_BANK_OK_clk <= DDRCLK0; + FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); --- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- - CLR_FIFO_SYNC_clk <= DDRCLK0; + -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + CLR_FIFO_SYNC_clk <= DDRCLK0; --- SYNCHRONISIEREN - CLR_FIFO_SYNC_d <= CLR_FIFO; - CLEAR_FIFO_CNT_clk <= DDRCLK0; - CLEAR_FIFO_CNT_d <= CLR_FIFO_SYNC_q or (not FIFO_ACTIVE); - STOP_clk <= DDRCLK0; - STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; + -- SYNCHRONISIEREN + CLR_FIFO_SYNC_d <= CLR_FIFO; + CLEAR_FIFO_CNT_clk <= DDRCLK0; + CLEAR_FIFO_CNT_d <= CLR_FIFO_SYNC_q or (not FIFO_ACTIVE); + STOP_clk <= DDRCLK0; + STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; --- ZÄHLEN ----------------------------------------------- - VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; - VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; - VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or + -- ZÄHLEN ----------------------------------------------- + VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; + VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; + VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or (sizeIt(not CLEAR_FIFO_CNT_q,23) and (std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) + unsigned'("00000000000000000000001")))); - VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D_q; - VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D_q; - VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D_q; - VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D_q(7 downto 4); - VDM_SEL <= VIDEO_BASE_L_D_q(3 downto 0); + + VIDEO_BASE_ADR(22 DOWNTO 20) <= VIDEO_BASE_X_D_q; + VIDEO_BASE_ADR(19 DOWNTO 12) <= VIDEO_BASE_H_D_q; + VIDEO_BASE_ADR(11 DOWNTO 4) <= VIDEO_BASE_M_D_q; + VIDEO_BASE_ADR(3 DOWNTO 0) <= VIDEO_BASE_L_D_q(7 DOWNTO 4); + VDM_SEL <= VIDEO_BASE_L_D_q(3 DOWNTO 0); --- AKTUELLE VIDEO ADRESSE - VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - + -- AKTUELLE VIDEO ADRESSE + VIDEO_ACT_ADR(26 DOWNTO 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - unsigned(std_logic_vector'("00000000000000" & FIFO_MW))); - VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL; + VIDEO_ACT_ADR(3 DOWNTO 0) <= VDM_SEL; --- --------------------------------------------------------------------------------------- --- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS --- --------------------------------------------------------------------------------------- - DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; + -- --------------------------------------------------------------------------------------- + -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS + -- --------------------------------------------------------------------------------------- + DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; --- ZÄHLEN 0-2047 - DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + - unsigned'("00000000001")); - REFRESH_TIME_clk <= DDRCLK0; + -- ZÄHLEN 0-2047 + DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001")); + REFRESH_TIME_clk <= DDRCLK0; --- SYNC - REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not - MAIN_CLK); - DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; - DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = - "100011"); + -- SYNC + REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not MAIN_CLK); + DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; + DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011"); --- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) --- MINUS 1 WENN GEMACHT - DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and + -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + -- MINUS 1 WENN GEMACHT + DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)); - DDR_REFRESH_REQ_clk <= DDRCLK0; - DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and - DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); + DDR_REFRESH_REQ_clk <= DDRCLK0; + DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); --- --------------------------------------------------------- --- VIDEO REGISTER ----------------------- --- ------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; + -- --------------------------------------------------------- + -- VIDEO REGISTER ----------------------- + -- ------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; --- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000110"); + -- 820D/2 + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000110"); --- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); - VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; + -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); + VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; --- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000001"); - VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); - VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; + -- 8203/2 + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000001"); + VIDEO_BASE_M_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); + VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; --- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000000"); - VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); - VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; - VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); - VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); + -- 8200-1/2 + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000000"); + VIDEO_BASE_H_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); + VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_X_D_d <= FB_AD(26 DOWNTO 24); + VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); --- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000100"); + -- 8209/2 + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000100"); --- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000011"); + -- 8207/2 + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000011"); --- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000010"); + -- 8204,5/2 + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) @@ -1169,35 +1258,35 @@ begin u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); + (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 DOWNTO 0)) or + (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 DOWNTO 8)) or + (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 DOWNTO 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - FB_AD(23 downto 16) <= u0_tridata; + FB_AD(23 DOWNTO 16) <= u0_tridata; --- Assignments added to explicitly combine the --- effects of multiple drivers in the source - FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; - BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; - BA(0) <= BA0_1 or BA0_2; - BA(1) <= BA1_1 or BA1_2; - VA(0) <= VA0_1 or VA0_2; - VA(1) <= VA1_1 or VA1_2; - VA(2) <= VA2_1 or VA2_2; - VA(3) <= VA3_1 or VA3_2; - VA(4) <= VA4_1 or VA4_2; - VA(5) <= VA5_1 or VA5_2; - VA(6) <= VA6_1 or VA6_2; - VA(7) <= VA7_1 or VA7_2; - VA(8) <= VA8_1 or VA8_2; - VA(9) <= VA9_1 or VA9_2; - VA(10) <= VA10_1 or VA10_2; - VA(11) <= VA11_1 or VA11_2; - VA(12) <= VA12_1 or VA12_2; + -- Assignments added to explicitly combine the + -- effects of multiple drivers in the source + FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; + BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; + BA(0) <= BA0_1 or BA0_2; + BA(1) <= BA1_1 or BA1_2; + VA(0) <= VA0_1 or VA0_2; + VA(1) <= VA1_1 or VA1_2; + VA(2) <= VA2_1 or VA2_2; + VA(3) <= VA3_1 or VA3_2; + VA(4) <= VA4_1 or VA4_2; + VA(5) <= VA5_1 or VA5_2; + VA(6) <= VA6_1 or VA6_2; + VA(7) <= VA7_1 or VA7_2; + VA(8) <= VA8_1 or VA8_2; + VA(9) <= VA9_1 or VA9_2; + VA(10) <= VA10_1 or VA10_2; + VA(11) <= VA11_1 or VA11_2; + VA(12) <= VA12_1 or VA12_2; --- Define power signal(s) - vcc <= '1'; - gnd <= '0'; -end DDR_CTR_behav; +-- Define power SIGNAL(s) + vcc <= '1'; + gnd <= '0'; +END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 49c66f4..b377532 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -183,70 +183,40 @@ ARCHITECTURE rtl OF video IS ); END COMPONENT; - COMPONENT blitter + COMPONENT ddr_ctr PORT ( + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; nRSTO : IN std_logic; MAIN_CLK : IN std_logic; FB_ALE : IN std_logic; nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - BLITTER_ON : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; + DDR_SYNC_66M : IN std_logic; + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; DDRCLK0 : IN std_logic; - SR_BLITTER_DACK : IN std_logic; - BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); - BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + CLK33M : IN std_logic; + CLR_FIFO : IN std_logic; + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); FB_AD : INOUT std_logic_vector(31 DOWNTO 0); FB_ADR : IN std_logic_vector(31 DOWNTO 0); + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_RUN : OUT std_logic; - BLITTER_SIG : OUT std_logic; - BLITTER_WR : OUT std_logic; - BLITTER_TA : OUT std_logic; - BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); - BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT ddr_ctr - PORT - ( - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - CLR_FIFO : IN std_logic; - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - nVWE : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - VCKE : OUT std_logic; - nVCAS : OUT std_logic; - SR_FIFO_WRE : OUT std_logic; - SR_DDR_FB : OUT std_logic; - SR_DDR_WR : OUT std_logic; - SR_DDRWR_D_SEL : OUT std_logic; - VIDEO_DDR_TA : OUT std_logic; + nVWE : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + VCKE : OUT std_logic; + nVCAS : OUT std_logic; + SR_FIFO_WRE : OUT std_logic; + SR_DDR_FB : OUT std_logic; + SR_DDR_WR : OUT std_logic; + SR_DDRWR_D_SEL : OUT std_logic; + VIDEO_DDR_TA : OUT std_logic; SR_BLITTER_DACK : OUT std_logic; DDRWR_D_SEL1 : OUT std_logic; BA : OUT std_logic_vector(1 DOWNTO 0); @@ -259,455 +229,525 @@ ARCHITECTURE rtl OF video IS END COMPONENT ddr_ctr; COMPONENT altdpram1 - PORT(wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(7 DOWNTO 0); - address_b : IN std_logic_vector(7 DOWNTO 0); - data_a : IN std_logic_vector(5 DOWNTO 0); - data_b : IN std_logic_vector(5 DOWNTO 0); - q_a : OUT std_logic_vector(5 DOWNTO 0); - q_b : OUT std_logic_vector(5 DOWNTO 0) + PORT + ( + wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(7 DOWNTO 0); + address_b : IN std_logic_vector(7 DOWNTO 0); + data_a : IN std_logic_vector(5 DOWNTO 0); + data_b : IN std_logic_vector(5 DOWNTO 0); + q_a : OUT std_logic_vector(5 DOWNTO 0); + q_b : OUT std_logic_vector(5 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_fifo_dc0 - PORT(wrreq : IN std_logic; - wrclk : IN std_logic; - rdreq : IN std_logic; - rdclk : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - rdempty : OUT std_logic; - q : OUT std_logic_vector(127 DOWNTO 0); - wrusedw : OUT std_logic_vector(8 DOWNTO 0) + PORT + ( + wrreq : IN std_logic; + wrclk : IN std_logic; + rdreq : IN std_logic; + rdclk : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + rdempty : OUT std_logic; + q : OUT std_logic_vector(127 DOWNTO 0); + wrusedw : OUT std_logic_vector(8 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_bidir0 - PORT(oe : IN std_logic; - inclock : IN std_logic; - outclock : IN std_logic; - datain_h : IN std_logic_vector(31 DOWNTO 0); - datain_l : IN std_logic_vector(31 DOWNTO 0); - padio : INOUT std_logic_vector(31 DOWNTO 0); - combout : OUT std_logic_vector(31 DOWNTO 0); - dataout_h : OUT std_logic_vector(31 DOWNTO 0); - dataout_l : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + oe : IN std_logic; + inclock : IN std_logic; + outclock : IN std_logic; + datain_h : IN std_logic_vector(31 DOWNTO 0); + datain_l : IN std_logic_vector(31 DOWNTO 0); + padio : INOUT std_logic_vector(31 DOWNTO 0); + combout : OUT std_logic_vector(31 DOWNTO 0); + dataout_h : OUT std_logic_vector(31 DOWNTO 0); + dataout_l : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff4 - PORT(clock : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - q : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + q : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_muxvdm - PORT(data0x : IN std_logic_vector(127 DOWNTO 0); - data10x : IN std_logic_vector(127 DOWNTO 0); - data11x : IN std_logic_vector(127 DOWNTO 0); - data12x : IN std_logic_vector(127 DOWNTO 0); - data13x : IN std_logic_vector(127 DOWNTO 0); - data14x : IN std_logic_vector(127 DOWNTO 0); - data15x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - data2x : IN std_logic_vector(127 DOWNTO 0); - data3x : IN std_logic_vector(127 DOWNTO 0); - data4x : IN std_logic_vector(127 DOWNTO 0); - data5x : IN std_logic_vector(127 DOWNTO 0); - data6x : IN std_logic_vector(127 DOWNTO 0); - data7x : IN std_logic_vector(127 DOWNTO 0); - data8x : IN std_logic_vector(127 DOWNTO 0); - data9x : IN std_logic_vector(127 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + data0x : IN std_logic_vector(127 DOWNTO 0); + data10x : IN std_logic_vector(127 DOWNTO 0); + data11x : IN std_logic_vector(127 DOWNTO 0); + data12x : IN std_logic_vector(127 DOWNTO 0); + data13x : IN std_logic_vector(127 DOWNTO 0); + data14x : IN std_logic_vector(127 DOWNTO 0); + data15x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + data2x : IN std_logic_vector(127 DOWNTO 0); + data3x : IN std_logic_vector(127 DOWNTO 0); + data4x : IN std_logic_vector(127 DOWNTO 0); + data5x : IN std_logic_vector(127 DOWNTO 0); + data6x : IN std_logic_vector(127 DOWNTO 0); + data7x : IN std_logic_vector(127 DOWNTO 0); + data8x : IN std_logic_vector(127 DOWNTO 0); + data9x : IN std_logic_vector(127 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux3 - PORT(data1 : IN std_logic; - data0 : IN std_logic; - sel : IN std_logic; - result : OUT std_logic + PORT + ( + data1 : IN std_logic; + data0 : IN std_logic; + sel : IN std_logic; + result : OUT std_logic ); END COMPONENT; COMPONENT lpm_bustri_long - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - tridata : INOUT std_logic_vector(31 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + tridata : INOUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff5 - PORT(clock : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - q : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + q : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff1 - PORT(clock : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff0 - PORT(clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_out0 - PORT(outclock : IN std_logic; - datain_h : IN std_logic_vector(3 DOWNTO 0); - datain_l : IN std_logic_vector(3 DOWNTO 0); - dataout : OUT std_logic_vector(3 DOWNTO 0) + PORT + ( + outclock : IN std_logic; + datain_h : IN std_logic_vector(3 DOWNTO 0); + datain_l : IN std_logic_vector(3 DOWNTO 0); + dataout : OUT std_logic_vector(3 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux0 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(31 DOWNTO 0); - data1x : IN std_logic_vector(31 DOWNTO 0); - data2x : IN std_logic_vector(31 DOWNTO 0); - data3x : IN std_logic_vector(31 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(31 DOWNTO 0); + data1x : IN std_logic_vector(31 DOWNTO 0); + data2x : IN std_logic_vector(31 DOWNTO 0); + data3x : IN std_logic_vector(31 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux5 - PORT(data0x : IN std_logic_vector(63 DOWNTO 0); - data1x : IN std_logic_vector(63 DOWNTO 0); - data2x : IN std_logic_vector(63 DOWNTO 0); - data3x : IN std_logic_vector(63 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(63 DOWNTO 0) + PORT + ( + data0x : IN std_logic_vector(63 DOWNTO 0); + data1x : IN std_logic_vector(63 DOWNTO 0); + data2x : IN std_logic_vector(63 DOWNTO 0); + data3x : IN std_logic_vector(63 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(63 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant2 - PORT( result : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux1 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(15 DOWNTO 0); - data1x : IN std_logic_vector(15 DOWNTO 0); - data2x : IN std_logic_vector(15 DOWNTO 0); - data3x : IN std_logic_vector(15 DOWNTO 0); - data4x : IN std_logic_vector(15 DOWNTO 0); - data5x : IN std_logic_vector(15 DOWNTO 0); - data6x : IN std_logic_vector(15 DOWNTO 0); - data7x : IN std_logic_vector(15 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(15 DOWNTO 0); + data1x : IN std_logic_vector(15 DOWNTO 0); + data2x : IN std_logic_vector(15 DOWNTO 0); + data3x : IN std_logic_vector(15 DOWNTO 0); + data4x : IN std_logic_vector(15 DOWNTO 0); + data5x : IN std_logic_vector(15 DOWNTO 0); + data6x : IN std_logic_vector(15 DOWNTO 0); + data7x : IN std_logic_vector(15 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux2 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(7 DOWNTO 0); - data10x : IN std_logic_vector(7 DOWNTO 0); - data11x : IN std_logic_vector(7 DOWNTO 0); - data12x : IN std_logic_vector(7 DOWNTO 0); - data13x : IN std_logic_vector(7 DOWNTO 0); - data14x : IN std_logic_vector(7 DOWNTO 0); - data15x : IN std_logic_vector(7 DOWNTO 0); - data1x : IN std_logic_vector(7 DOWNTO 0); - data2x : IN std_logic_vector(7 DOWNTO 0); - data3x : IN std_logic_vector(7 DOWNTO 0); - data4x : IN std_logic_vector(7 DOWNTO 0); - data5x : IN std_logic_vector(7 DOWNTO 0); - data6x : IN std_logic_vector(7 DOWNTO 0); - data7x : IN std_logic_vector(7 DOWNTO 0); - data8x : IN std_logic_vector(7 DOWNTO 0); - data9x : IN std_logic_vector(7 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(7 DOWNTO 0); + data10x : IN std_logic_vector(7 DOWNTO 0); + data11x : IN std_logic_vector(7 DOWNTO 0); + data12x : IN std_logic_vector(7 DOWNTO 0); + data13x : IN std_logic_vector(7 DOWNTO 0); + data14x : IN std_logic_vector(7 DOWNTO 0); + data15x : IN std_logic_vector(7 DOWNTO 0); + data1x : IN std_logic_vector(7 DOWNTO 0); + data2x : IN std_logic_vector(7 DOWNTO 0); + data3x : IN std_logic_vector(7 DOWNTO 0); + data4x : IN std_logic_vector(7 DOWNTO 0); + data5x : IN std_logic_vector(7 DOWNTO 0); + data6x : IN std_logic_vector(7 DOWNTO 0); + data7x : IN std_logic_vector(7 DOWNTO 0); + data8x : IN std_logic_vector(7 DOWNTO 0); + data9x : IN std_logic_vector(7 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg4 - PORT(clock : IN std_logic; - shiftin : IN std_logic; - shiftout : OUT std_logic + PORT + ( + clock : IN std_logic; + shiftin : IN std_logic; + shiftout : OUT std_logic ); END COMPONENT; COMPONENT lpm_latch0 - PORT(gate : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + gate : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff6 - PORT(clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff3 - PORT(clock : IN std_logic; - data : IN std_logic_vector(23 DOWNTO 0); - q : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(23 DOWNTO 0); + q : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_out2 - PORT(outclock : IN std_logic; - datain_h : IN std_logic_vector(23 DOWNTO 0); - datain_l : IN std_logic_vector(23 DOWNTO 0); - dataout : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + outclock : IN std_logic; + datain_h : IN std_logic_vector(23 DOWNTO 0); + datain_l : IN std_logic_vector(23 DOWNTO 0); + dataout : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri1 - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(2 DOWNTO 0); - tridata : INOUT std_logic_vector(2 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(2 DOWNTO 0); + tridata : INOUT std_logic_vector(2 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri_byt - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - tridata : INOUT std_logic_vector(7 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + tridata : INOUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant0 - PORT( result : OUT std_logic_vector(4 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(4 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_muxdz - PORT(clock : IN std_logic; - clken : IN std_logic; - sel : IN std_logic; - data0x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + clock : IN std_logic; + clken : IN std_logic; + sel : IN std_logic; + data0x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_fifodz - PORT(wrreq : IN std_logic; - rdreq : IN std_logic; - clock : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + wrreq : IN std_logic; + rdreq : IN std_logic; + clock : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri3 - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(5 DOWNTO 0); - tridata : INOUT std_logic_vector(5 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(5 DOWNTO 0); + tridata : INOUT std_logic_vector(5 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux6 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(23 DOWNTO 0); - data1x : IN std_logic_vector(23 DOWNTO 0); - data2x : IN std_logic_vector(23 DOWNTO 0); - data3x : IN std_logic_vector(23 DOWNTO 0); - data4x : IN std_logic_vector(23 DOWNTO 0); - data5x : IN std_logic_vector(23 DOWNTO 0); - data6x : IN std_logic_vector(23 DOWNTO 0); - data7x : IN std_logic_vector(23 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(23 DOWNTO 0); + data1x : IN std_logic_vector(23 DOWNTO 0); + data2x : IN std_logic_vector(23 DOWNTO 0); + data3x : IN std_logic_vector(23 DOWNTO 0); + data4x : IN std_logic_vector(23 DOWNTO 0); + data5x : IN std_logic_vector(23 DOWNTO 0); + data6x : IN std_logic_vector(23 DOWNTO 0); + data7x : IN std_logic_vector(23 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant1 - PORT( result : OUT std_logic_vector(1 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(1 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux4 - PORT(sel : IN std_logic; - data0x : IN std_logic_vector(6 DOWNTO 0); - data1x : IN std_logic_vector(6 DOWNTO 0); - result : OUT std_logic_vector(6 DOWNTO 0) + PORT + ( + sel : IN std_logic; + data0x : IN std_logic_vector(6 DOWNTO 0); + data1x : IN std_logic_vector(6 DOWNTO 0); + result : OUT std_logic_vector(6 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant3 - PORT( result : OUT std_logic_vector(6 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(6 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg6 - PORT(clock : IN std_logic; - shiftin : IN std_logic; - q : OUT std_logic_vector(4 DOWNTO 0) + PORT + ( + clock : IN std_logic; + shiftin : IN std_logic; + q : OUT std_logic_vector(4 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg0 - PORT(load : IN std_logic; - clock : IN std_logic; - shiftin : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - shiftout : OUT std_logic + PORT + ( + load : IN std_logic; + clock : IN std_logic; + shiftin : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + shiftout : OUT std_logic ); END COMPONENT; COMPONENT altdpram0 - PORT(wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(3 DOWNTO 0); - address_b : IN std_logic_vector(3 DOWNTO 0); - data_a : IN std_logic_vector(2 DOWNTO 0); - data_b : IN std_logic_vector(2 DOWNTO 0); - q_a : OUT std_logic_vector(2 DOWNTO 0); - q_b : OUT std_logic_vector(2 DOWNTO 0) + PORT + ( + wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(3 DOWNTO 0); + address_b : IN std_logic_vector(3 DOWNTO 0); + data_a : IN std_logic_vector(2 DOWNTO 0); + data_b : IN std_logic_vector(2 DOWNTO 0); + q_a : OUT std_logic_vector(2 DOWNTO 0); + q_b : OUT std_logic_vector(2 DOWNTO 0) ); END COMPONENT; COMPONENT video_mod_mux_clutctr - PORT(nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - BLITTER_RUN : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - COLOR8 : OUT std_logic; - ACP_CLUT_RD : OUT std_logic; - COLOR1 : OUT std_logic; - FALCON_CLUT_RDH : OUT std_logic; - FALCON_CLUT_RDL : OUT std_logic; - ST_CLUT_RD : OUT std_logic; - HSYNC : OUT std_logic; - VSYNC : OUT std_logic; - nBLANK : OUT std_logic; - nSYNC : OUT std_logic; - nPD_VGA : OUT std_logic; - FIFO_RDE : OUT std_logic; - COLOR2 : OUT std_logic; - COLOR4 : OUT std_logic; - PIXEL_CLK : OUT std_logic; - BLITTER_ON : OUT std_logic; - VIDEO_MOD_TA : OUT std_logic; - INTER_ZEI : OUT std_logic; - DOP_FIFO_CLR : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - CLR_FIFO : OUT std_logic; - ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); - CCSEL : OUT std_logic_vector(2 DOWNTO 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); - CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); - FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); - VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + BLITTER_RUN : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_BUSY : IN std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VR_D : IN std_logic_vector(8 DOWNTO 0); + COLOR8 : OUT std_logic; + ACP_CLUT_RD : OUT std_logic; + COLOR1 : OUT std_logic; + FALCON_CLUT_RDH : OUT std_logic; + FALCON_CLUT_RDL : OUT std_logic; + ST_CLUT_RD : OUT std_logic; + HSYNC : OUT std_logic; + VSYNC : OUT std_logic; + nBLANK : OUT std_logic; + nSYNC : OUT std_logic; + nPD_VGA : OUT std_logic; + FIFO_RDE : OUT std_logic; + COLOR2 : OUT std_logic; + COLOR4 : OUT std_logic; + PIXEL_CLK : OUT std_logic; + BLITTER_ON : OUT std_logic; + VIDEO_MOD_TA : OUT std_logic; + INTER_ZEI : OUT std_logic; + DOP_FIFO_CLR : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + CLR_FIFO : OUT std_logic; + ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); + CCSEL : OUT std_logic_vector(2 DOWNTO 0); + CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); + CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); + FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); + VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; - SIGNAL ACP_CLUT_RD : std_logic; - SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); - SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_ON : std_logic; - SIGNAL BLITTER_RUN : std_logic; - SIGNAL BLITTER_SIG : std_logic; - SIGNAL BLITTER_TA : std_logic; - SIGNAL BLITTER_WR : std_logic; - SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); - SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); - SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); - SIGNAL CCA : std_logic_vector(23 DOWNTO 0); - SIGNAL CCF : std_logic_vector(23 DOWNTO 0); - SIGNAL CCS : std_logic_vector(23 DOWNTO 0); - SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); - SIGNAL CLR_FIFO : std_logic; - SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); - SIGNAL CLUT_ADR1A : std_logic; - SIGNAL CLUT_ADR2A : std_logic; - SIGNAL CLUT_ADR3A : std_logic; - SIGNAL CLUT_ADR4A : std_logic; - SIGNAL CLUT_ADR5A : std_logic; - SIGNAL CLUT_ADR6A : std_logic; - SIGNAL CLUT_ADR7A : std_logic; - SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); - SIGNAL COLOR1 : std_logic; - SIGNAL COLOR2 : std_logic; - SIGNAL COLOR4 : std_logic; - SIGNAL COLOR8 : std_logic; - SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); - SIGNAL DDR_WR : std_logic; - SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); - SIGNAL DOP_FIFO_CLR : std_logic; + SIGNAL ACP_CLUT_RD : std_logic; + SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); + SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); + SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_ON : std_logic; + SIGNAL BLITTER_RUN : std_logic; + SIGNAL BLITTER_SIG : std_logic; + SIGNAL BLITTER_TA : std_logic; + SIGNAL BLITTER_WR : std_logic; + SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); + SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); + SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); + SIGNAL CCA : std_logic_vector(23 DOWNTO 0); + SIGNAL CCF : std_logic_vector(23 DOWNTO 0); + SIGNAL CCS : std_logic_vector(23 DOWNTO 0); + SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); + SIGNAL CLUT_ADR1A : std_logic; + SIGNAL CLUT_ADR2A : std_logic; + SIGNAL CLUT_ADR3A : std_logic; + SIGNAL CLUT_ADR4A : std_logic; + SIGNAL CLUT_ADR5A : std_logic; + SIGNAL CLUT_ADR6A : std_logic; + SIGNAL CLUT_ADR7A : std_logic; + SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); + SIGNAL COLOR1 : std_logic; + SIGNAL COLOR2 : std_logic; + SIGNAL COLOR4 : std_logic; + SIGNAL COLOR8 : std_logic; + SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); + SIGNAL DDR_WR : std_logic; + SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); + SIGNAL DOP_FIFO_CLR : std_logic; SIGNAL FALCON_CLUT_RDH : std_logic; SIGNAL FALCON_CLUT_RDL : std_logic; - SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); - SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); - SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); - SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); - SIGNAL FIFO_RDE : std_logic; - SIGNAL FIFO_WRE : std_logic; - SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic; + SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); + SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); + SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); + SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); + SIGNAL FIFO_RDE : std_logic; + SIGNAL FIFO_WRE : std_logic; + SIGNAL INTER_ZEI : std_logic; + SIGNAL nFB_BURST : std_logic; SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : std_logic; SIGNAL SR_BLITTER_DACK : std_logic; - SIGNAL SR_DDR_FB : std_logic; - SIGNAL SR_DDR_WR : std_logic; - SIGNAL SR_DDRWR_D_SEL : std_logic; - SIGNAL SR_FIFO_WRE : std_logic; - SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL ST_CLUT_RD : std_logic; - SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); - SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); - SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL VDOUT_OE : std_logic; - SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); - SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); - SIGNAL VDR : std_logic_vector(31 DOWNTO 0); - SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); - SIGNAL VIDEO_DDR_TA : std_logic; - SIGNAL VIDEO_MOD_TA : std_logic; - SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); - SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); - SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); + SIGNAL SR_DDR_FB : std_logic; + SIGNAL SR_DDR_WR : std_logic; + SIGNAL SR_DDRWR_D_SEL : std_logic; + SIGNAL SR_FIFO_WRE : std_logic; + SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL ST_CLUT_RD : std_logic; + SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); + SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); + SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL VDOUT_OE : std_logic; + SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); + SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); + SIGNAL VDR : std_logic_vector(31 DOWNTO 0); + SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); + SIGNAL VIDEO_DDR_TA : std_logic; + SIGNAL VIDEO_MOD_TA : std_logic; + SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); + SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); + SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_0 : std_logic; SIGNAL SYNTHESIZED_WIRE_1 : std_logic; SIGNAL SYNTHESIZED_WIRE_2 : std_logic; @@ -716,7 +756,7 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_5 : std_logic; SIGNAL SYNTHESIZED_WIRE_60 : std_logic; SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); - SIGNAL DFF_inst93 : std_logic; + SIGNAL DFF_inst93 : std_logic; SIGNAL SYNTHESIZED_WIRE_8 : std_logic; SIGNAL SYNTHESIZED_WIRE_9 : std_logic; SIGNAL SYNTHESIZED_WIRE_61 : std_logic; @@ -754,7 +794,7 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_46 : std_logic; SIGNAL SYNTHESIZED_WIRE_47 : std_logic_vector(6 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_48 : std_logic_vector(31 DOWNTO 0); - SIGNAL DFF_inst91 : std_logic; + SIGNAL DFF_inst91 : std_logic; SIGNAL SYNTHESIZED_WIRE_64 : std_logic; SIGNAL SYNTHESIZED_WIRE_49 : std_logic; SIGNAL SYNTHESIZED_WIRE_50 : std_logic; @@ -768,22 +808,22 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); BEGIN VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); @@ -806,38 +846,32 @@ BEGIN SYNTHESIZED_WIRE_56 <= '0'; SYNTHESIZED_WIRE_57 <= '0'; - CC16(18) <= GDFX_TEMP_SIGNAL_16(7); - CC16(17) <= GDFX_TEMP_SIGNAL_16(6); - CC16(16) <= GDFX_TEMP_SIGNAL_16(5); - CC16(9) <= GDFX_TEMP_SIGNAL_16(4); - CC16(8) <= GDFX_TEMP_SIGNAL_16(3); - CC16(2) <= GDFX_TEMP_SIGNAL_16(2); - CC16(1) <= GDFX_TEMP_SIGNAL_16(1); - CC16(0) <= GDFX_TEMP_SIGNAL_16(0); - CC16(23) <= GDFX_TEMP_SIGNAL_0(15); CC16(22) <= GDFX_TEMP_SIGNAL_0(14); CC16(21) <= GDFX_TEMP_SIGNAL_0(13); CC16(20) <= GDFX_TEMP_SIGNAL_0(12); CC16(19) <= GDFX_TEMP_SIGNAL_0(11); + CC16(18) <= GDFX_TEMP_SIGNAL_16(7); + CC16(17) <= GDFX_TEMP_SIGNAL_16(6); + CC16(16) <= GDFX_TEMP_SIGNAL_16(5); CC16(15) <= GDFX_TEMP_SIGNAL_0(10); CC16(14) <= GDFX_TEMP_SIGNAL_0(9); CC16(13) <= GDFX_TEMP_SIGNAL_0(8); CC16(12) <= GDFX_TEMP_SIGNAL_0(7); CC16(11) <= GDFX_TEMP_SIGNAL_0(6); CC16(10) <= GDFX_TEMP_SIGNAL_0(5); + CC16(9) <= GDFX_TEMP_SIGNAL_16(4); + CC16(8) <= GDFX_TEMP_SIGNAL_16(3); CC16(7) <= GDFX_TEMP_SIGNAL_0(4); CC16(6) <= GDFX_TEMP_SIGNAL_0(3); CC16(5) <= GDFX_TEMP_SIGNAL_0(2); CC16(4) <= GDFX_TEMP_SIGNAL_0(1); CC16(3) <= GDFX_TEMP_SIGNAL_0(0); + CC16(2) <= GDFX_TEMP_SIGNAL_16(2); + CC16(1) <= GDFX_TEMP_SIGNAL_16(1); + CC16(0) <= GDFX_TEMP_SIGNAL_16(0); + - GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); - GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); - GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); - GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); - GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); - GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); @@ -847,210 +881,255 @@ BEGIN GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); + GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); + GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); + GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); + GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); + GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); + GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); ACP_CLUT_RAM : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_0, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(7 DOWNTO 0), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_30, - q_b => CCA(7 DOWNTO 0)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_0, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(7 DOWNTO 0), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_30, + q_b => CCA(7 DOWNTO 0) + ); ACP_CLUT_RAM54 : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(2), - wren_b => SYNTHESIZED_WIRE_1, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(15 DOWNTO 8), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_32, - q_b => CCA(15 DOWNTO 8)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(2), + wren_b => SYNTHESIZED_WIRE_1, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(15 DOWNTO 8), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_32, + q_b => CCA(15 DOWNTO 8) + ); ACP_CLUT_RAM55 : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_2, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(23 DOWNTO 16), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_33, - q_b => CCA(23 DOWNTO 16)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_2, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(23 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_33, + q_b => CCA(23 DOWNTO 16) + ); - i_blitter : blitter - PORT MAP(nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - BLITTER_ON => BLITTER_ON, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - DDRCLK0 => DDRCLK(0), - SR_BLITTER_DACK => SR_BLITTER_DACK, - BLITTER_DACK => BLITTER_DACK, - BLITTER_DIN => BLITTER_DIN, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - BLITTER_RUN => BLITTER_RUN, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - BLITTER_TA => BLITTER_TA, - BLITTER_ADR => BLITTER_ADR, - BLITTER_DOUT => BLITTER_DOUT); + i_blitter : work.blitter + PORT MAP + ( + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + BLITTER_ON => BLITTER_ON, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + DDRCLK0 => DDRCLK(0), + SR_BLITTER_DACK => SR_BLITTER_DACK, + BLITTER_DACK => BLITTER_DACK, + BLITTER_DIN => BLITTER_DIN, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + BLITTER_RUN => BLITTER_RUN, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + BLITTER_TA => BLITTER_TA, + BLITTER_ADR => BLITTER_ADR, + BLITTER_DOUT => BLITTER_DOUT + ); i_ddr_ctr : ddr_ctr - PORT MAP(nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - DDR_SYNC_66M => DDR_SYNC_66M, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - DDRCLK0 => DDRCLK(0), - CLK33M => CLK33M, - CLR_FIFO => CLR_FIFO, - BLITTER_ADR => BLITTER_ADR, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - FIFO_MW => FIFO_MW, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - nVWE => nVWE, - nVRAS => nVRAS, - nVCS => nVCS, - VCKE => VCKE, - nVCAS => nVCAS, - SR_FIFO_WRE => SR_FIFO_WRE, - SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, - SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, - VIDEO_DDR_TA => VIDEO_DDR_TA, - SR_BLITTER_DACK => SR_BLITTER_DACK, - DDRWR_D_SEL1 => DDRWR_D_SEL(1), - BA => BA, - FB_LE => FB_LE, - FB_VDOE => FB_VDOE, - SR_VDMP => SR_VDMP, - VA => VA, - VDM_SEL => VDM_SEL); + PORT MAP + ( + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + DDR_SYNC_66M => DDR_SYNC_66M, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + DDRCLK0 => DDRCLK(0), + CLK33M => CLK33M, + CLR_FIFO => CLR_FIFO, + BLITTER_ADR => BLITTER_ADR, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + FIFO_MW => FIFO_MW, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + nVWE => nVWE, + nVRAS => nVRAS, + nVCS => nVCS, + VCKE => VCKE, + nVCAS => nVCAS, + SR_FIFO_WRE => SR_FIFO_WRE, + SR_DDR_FB => SR_DDR_FB, + SR_DDR_WR => SR_DDR_WR, + SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, + VIDEO_DDR_TA => VIDEO_DDR_TA, + SR_BLITTER_DACK => SR_BLITTER_DACK, + DDRWR_D_SEL1 => DDRWR_D_SEL(1), + BA => BA, + FB_LE => FB_LE, + FB_VDOE => FB_VDOE, + SR_VDMP => SR_VDMP, + VA => VA, + VDM_SEL => VDM_SEL + ); FALCON_CLUT_BLUE : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_3, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_45, - q_b => CCF(7 DOWNTO 2)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_3, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_45, + q_b => CCF(7 DOWNTO 2) + ); FALCON_CLUT_GREEN : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_4, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_44, - q_b => CCF(15 DOWNTO 10)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_4, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_44, + q_b => CCF(15 DOWNTO 10) + ); FALCON_CLUT_RED : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_5, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(31 DOWNTO 26), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_41, - q_b => CCF(23 DOWNTO 18)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_5, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(31 DOWNTO 26), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_41, + q_b => CCF(23 DOWNTO 18) + ); inst : lpm_fifo_dc0 - PORT MAP(wrreq => FIFO_WRE, - wrclk => DDRCLK(0), - rdreq => SYNTHESIZED_WIRE_60, - rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, - aclr => CLR_FIFO, - data => VDMC, - q => SYNTHESIZED_WIRE_63, - wrusedw => FIFO_MW); + PORT MAP + ( + wrreq => FIFO_WRE, + wrclk => DDRCLK(0), + rdreq => SYNTHESIZED_WIRE_60, + rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => CLR_FIFO, + data => VDMC, + q => SYNTHESIZED_WIRE_63, + wrusedw => FIFO_MW + ); inst1 : altddio_bidir0 - PORT MAP(oe => VDOUT_OE, - inclock => DDRCLK(1), - outclock => DDRCLK(3), - datain_h => VDP_OUT(63 DOWNTO 32), - datain_l => VDP_OUT(31 DOWNTO 0), - padio => VD, - combout => SYNTHESIZED_WIRE_15, - dataout_h => VDP_IN(31 DOWNTO 0), - dataout_l => VDP_IN(63 DOWNTO 32)); + PORT MAP + ( + oe => VDOUT_OE, + inclock => DDRCLK(1), + outclock => DDRCLK(3), + datain_h => VDP_OUT(63 DOWNTO 32), + datain_l => VDP_OUT(31 DOWNTO 0), + padio => VD, + combout => SYNTHESIZED_WIRE_15, + dataout_h => VDP_IN(31 DOWNTO 0), + dataout_l => VDP_IN(63 DOWNTO 32) + ); inst10 : lpm_ff4 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_7, - q => GDFX_TEMP_SIGNAL_0); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_7, + q => GDFX_TEMP_SIGNAL_0 + ); inst100 : lpm_muxvdm - PORT MAP(data0x => VDMB, - data10x => GDFX_TEMP_SIGNAL_1, - data11x => GDFX_TEMP_SIGNAL_2, - data12x => GDFX_TEMP_SIGNAL_3, - data13x => GDFX_TEMP_SIGNAL_4, - data14x => GDFX_TEMP_SIGNAL_5, - data15x => GDFX_TEMP_SIGNAL_6, - data1x => GDFX_TEMP_SIGNAL_7, - data2x => GDFX_TEMP_SIGNAL_8, - data3x => GDFX_TEMP_SIGNAL_9, - data4x => GDFX_TEMP_SIGNAL_10, - data5x => GDFX_TEMP_SIGNAL_11, - data6x => GDFX_TEMP_SIGNAL_12, - data7x => GDFX_TEMP_SIGNAL_13, - data8x => GDFX_TEMP_SIGNAL_14, - data9x => GDFX_TEMP_SIGNAL_15, - sel => VDM_SEL, - result => VDMC); + PORT MAP + ( + data0x => VDMB, + data10x => GDFX_TEMP_SIGNAL_1, + data11x => GDFX_TEMP_SIGNAL_2, + data12x => GDFX_TEMP_SIGNAL_3, + data13x => GDFX_TEMP_SIGNAL_4, + data14x => GDFX_TEMP_SIGNAL_5, + data15x => GDFX_TEMP_SIGNAL_6, + data1x => GDFX_TEMP_SIGNAL_7, + data2x => GDFX_TEMP_SIGNAL_8, + data3x => GDFX_TEMP_SIGNAL_9, + data4x => GDFX_TEMP_SIGNAL_10, + data5x => GDFX_TEMP_SIGNAL_11, + data6x => GDFX_TEMP_SIGNAL_12, + data7x => GDFX_TEMP_SIGNAL_13, + data8x => GDFX_TEMP_SIGNAL_14, + data9x => GDFX_TEMP_SIGNAL_15, + sel => VDM_SEL, + result => VDMC + ); inst102 : lpm_mux3 - PORT MAP(data1 => DFF_inst93, - data0 => ZR_C8(0), - sel => COLOR1, - result => ZR_C8B(0)); + PORT MAP + ( + data1 => DFF_inst93, + data0 => ZR_C8(0), + sel => COLOR1, + result => ZR_C8B(0) + ); @@ -1063,53 +1142,77 @@ BEGIN inst108 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(0), - data => VDR, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(0), + data => VDR, + tridata => FB_AD + ); inst109 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(1), - data => SYNTHESIZED_WIRE_11, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(1), + data => SYNTHESIZED_WIRE_11, + tridata => FB_AD + ); inst11 : lpm_ff5 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_12, - q => ZR_C8); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_12, + q => ZR_C8 + ); inst110 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(2), - data => SYNTHESIZED_WIRE_13, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(2), + data => SYNTHESIZED_WIRE_13, + tridata => FB_AD + ); inst119 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(3), - data => SYNTHESIZED_WIRE_14, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(3), + data => SYNTHESIZED_WIRE_14, + tridata => FB_AD + ); inst12 : lpm_ff1 - PORT MAP(clock => DDRCLK(0), - data => VDP_IN(31 DOWNTO 0), - q => VDVZ(31 DOWNTO 0)); + PORT MAP + ( + clock => DDRCLK(0), + data => VDP_IN(31 DOWNTO 0), + q => VDVZ(31 DOWNTO 0) + ); inst13 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(0), - data => FB_AD, - q => FB_DDR(127 DOWNTO 96)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(0), + data => FB_AD, + q => FB_DDR(127 DOWNTO 96) + ); inst14 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(1), - data => FB_AD, - q => FB_DDR(95 DOWNTO 64)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(1), + data => FB_AD, + q => FB_DDR(95 DOWNTO 64) + ); inst15 : lpm_ff0 diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 9712f63..8d9b983 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -670,186 +670,186 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 5e526e2..62ec98e 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -133,16 +133,20 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_port set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} # video RAM access -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} #**************************************************************