fix timing

FPGA_Quartus_13.1/firebee1.vhd

@@ -242,6 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS
         );
     END COMPONENT altpll4;
 
+    COMPONENT Video
+	PORT
+	(
+		FB_ADR		:	 IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		MAIN_CLK		:	 IN STD_LOGIC;
+		nFB_CS1		:	 IN STD_LOGIC;
+		nFB_CS2		:	 IN STD_LOGIC;
+		nFB_CS3		:	 IN STD_LOGIC;
+		nFB_WR		:	 IN STD_LOGIC;
+		FB_SIZE0		:	 IN STD_LOGIC;
+		FB_SIZE1		:	 IN STD_LOGIC;
+		nRSTO		:	 IN STD_LOGIC;
+		nFB_OE		:	 IN STD_LOGIC;
+		FB_ALE		:	 IN STD_LOGIC;
+		DDRCLK		:	 IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DDR_SYNC_66M		:	 IN STD_LOGIC;
+		CLK33M		:	 IN STD_LOGIC;
+		CLK25M		:	 IN STD_LOGIC;
+		CLK_VIDEO		:	 IN STD_LOGIC;
+		VR_D		:	 IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		VR_BUSY		:	 IN STD_LOGIC;
+		VG		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VB		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VR		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		nBLANK		:	 OUT STD_LOGIC;
+		VA		:	 OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
+		nVWE		:	 OUT STD_LOGIC;
+		nVCAS		:	 OUT STD_LOGIC;
+		nVRAS		:	 OUT STD_LOGIC;
+		nVCS		:	 OUT STD_LOGIC;
+		VDM		:	 OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		nPD_VGA		:	 OUT STD_LOGIC;
+		VCKE		:	 OUT STD_LOGIC;
+		VSYNC		:	 OUT STD_LOGIC;
+		HSYNC		:	 OUT STD_LOGIC;
+		nSYNC		:	 OUT STD_LOGIC;
+		VIDEO_TA		:	 OUT STD_LOGIC;
+		PIXEL_CLK		:	 OUT STD_LOGIC;
+		BA		:	 OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		VIDEO_RECONFIG		:	 OUT STD_LOGIC;
+		VR_WR		:	 OUT STD_LOGIC;
+		VR_RD		:	 OUT STD_LOGIC;
+		VDQS		:	 INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		FB_AD		:	 INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VD		:	 INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
 BEGIN 
     nDREQ1 <= nDACK1;
     
@@ -472,7 +519,7 @@ BEGIN
         );
     
     
-    i_video : work.video
+    i_video : video
         PORT MAP
         (
             MAIN_CLK => MAIN_CLK,