From 7a046661542e175f516ee99611ad58228c0e4abf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Fri, 29 Jul 2016 13:27:25 +0000
Subject: [PATCH] complete flexbus_register component (nearly)

---
 .../Interrupt_Handler/interrupt_handler.vhd   |  145 +-
 FPGA_Quartus_13.1/firebee1.qsf                | 1496 ++++++++---------
 FPGA_Quartus_13.1/firebee1.vhd                |    4 +-
 FPGA_Quartus_13.1/firebee_groups.sdc          |    7 +-
 FPGA_Quartus_13.1/flexbus_register.vhd        |   49 +-
 FPGA_Quartus_13.1/video/ddr_controller.vhd    |   43 +-
 6 files changed, 892 insertions(+), 852 deletions(-)

diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
index b88570c..e832ccf 100755
--- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
+++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
@@ -182,13 +182,13 @@ end interrupt_handler;
 
 ARCHITECTURE rtl OF interrupt_handler IS
 --  WERTE REGISTER 0-63
-   signal FB_B              : std_logic_vector(3 downto 0);
-   signal INT_CTR           : std_logic_vector(31 downto 0);
-   signal INT_CTR_d         : std_logic_vector(31 downto 0);
-   signal INT_CTR_q         : std_logic_vector(31 downto 0);
+   signal fb_b              : std_logic_vector(3 downto 0);
+   signal int_ctr           : std_logic_vector(31 downto 0);
+   signal int_ctr_d         : std_logic_vector(31 downto 0);
+   signal int_ctr_q         : std_logic_vector(31 downto 0);
    
-   signal INT_LATCH         : std_logic_vector(31 downto 0);
-   signal INT_LATCH_d       : std_logic_vector(31 downto 0);
+   signal int_latch         : std_logic_vector(31 downto 0);
+   signal int_latch_d       : std_logic_vector(31 downto 0);
    signal INT_LATCH_clrn    : std_logic_vector(31 downto 0);
    signal INT_LATCH_q       : std_logic_vector(31 downto 0);
    signal INT_LATCH_clk     : std_logic_vector(31 downto 0);
@@ -475,7 +475,7 @@ begin
     begin
         if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then
             if INT_CTR24_ena_ctrl='1' then
-                INT_CTR_q(31 downto 24) <= INT_CTR_d(31 downto 24);
+                int_ctr_q(31 downto 24) <= int_ctr_d(31 downto 24);
             end if;
         end if;
     end process;
@@ -484,7 +484,7 @@ begin
     begin
         if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then
             if INT_CTR16_ena_ctrl='1' then
-                INT_CTR_q(23 downto 16) <= INT_CTR_d(23 downto 16);
+                int_ctr_q(23 downto 16) <= int_ctr_d(23 downto 16);
             end if;
         end if;
     end process;
@@ -493,7 +493,7 @@ begin
     begin
         if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then
             if INT_CTR8_ena_ctrl='1' then
-                INT_CTR_q(15 downto 8) <= INT_CTR_d(15 downto 8);
+                int_ctr_q(15 downto 8) <= int_ctr_d(15 downto 8);
             end if;
         end if;
     end process;
@@ -502,7 +502,7 @@ begin
     begin
         if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then
             if INT_CTR0_ena_ctrl='1' then
-                INT_CTR_q(7 downto 0) <= INT_CTR_d(7 downto 0);
+                int_ctr_q(7 downto 0) <= int_ctr_d(7 downto 0);
             end if;
         end if;
     end process;
@@ -512,7 +512,7 @@ begin
         if INT_LATCH_clrn(31)='0' then
             INT_LATCH_q(31) <= '0';
         elsif INT_LATCH_clk(31)'event and INT_LATCH_clk(31)='1' then
-            INT_LATCH_q(31) <= INT_LATCH_d(31);
+            INT_LATCH_q(31) <= int_latch_d(31);
         end if;
     end process;
 
@@ -521,7 +521,7 @@ begin
         if INT_LATCH_clrn(30)='0' then
             INT_LATCH_q(30) <= '0';
         elsif INT_LATCH_clk(30)'event and INT_LATCH_clk(30)='1' then
-            INT_LATCH_q(30) <= INT_LATCH_d(30);
+            INT_LATCH_q(30) <= int_latch_d(30);
         end if;
     end process;
 
@@ -530,7 +530,7 @@ begin
       if INT_LATCH_clrn(29)='0' then
 	 INT_LATCH_q(29) <= '0';
       elsif INT_LATCH_clk(29)'event and INT_LATCH_clk(29)='1' then
-	 INT_LATCH_q(29) <= INT_LATCH_d(29);
+	 INT_LATCH_q(29) <= int_latch_d(29);
       end if;
    end process;
 
@@ -538,7 +538,7 @@ begin
       if INT_LATCH_clrn(28)='0' then
 	 INT_LATCH_q(28) <= '0';
       elsif INT_LATCH_clk(28)'event and INT_LATCH_clk(28)='1' then
-	 INT_LATCH_q(28) <= INT_LATCH_d(28);
+	 INT_LATCH_q(28) <= int_latch_d(28);
       end if;
    end process;
 
@@ -546,7 +546,7 @@ begin
       if INT_LATCH_clrn(27)='0' then
 	 INT_LATCH_q(27) <= '0';
       elsif INT_LATCH_clk(27)'event and INT_LATCH_clk(27)='1' then
-	 INT_LATCH_q(27) <= INT_LATCH_d(27);
+	 INT_LATCH_q(27) <= int_latch_d(27);
       end if;
    end process;
 
@@ -554,7 +554,7 @@ begin
       if INT_LATCH_clrn(26)='0' then
 	 INT_LATCH_q(26) <= '0';
       elsif INT_LATCH_clk(26)'event and INT_LATCH_clk(26)='1' then
-	 INT_LATCH_q(26) <= INT_LATCH_d(26);
+	 INT_LATCH_q(26) <= int_latch_d(26);
       end if;
    end process;
 
@@ -562,7 +562,7 @@ begin
       if INT_LATCH_clrn(25)='0' then
 	 INT_LATCH_q(25) <= '0';
       elsif INT_LATCH_clk(25)'event and INT_LATCH_clk(25)='1' then
-	 INT_LATCH_q(25) <= INT_LATCH_d(25);
+	 INT_LATCH_q(25) <= int_latch_d(25);
       end if;
    end process;
 
@@ -570,7 +570,7 @@ begin
       if INT_LATCH_clrn(24)='0' then
 	 INT_LATCH_q(24) <= '0';
       elsif INT_LATCH_clk(24)'event and INT_LATCH_clk(24)='1' then
-	 INT_LATCH_q(24) <= INT_LATCH_d(24);
+	 INT_LATCH_q(24) <= int_latch_d(24);
       end if;
    end process;
 
@@ -578,7 +578,7 @@ begin
       if INT_LATCH_clrn(23)='0' then
 	 INT_LATCH_q(23) <= '0';
       elsif INT_LATCH_clk(23)'event and INT_LATCH_clk(23)='1' then
-	 INT_LATCH_q(23) <= INT_LATCH_d(23);
+	 INT_LATCH_q(23) <= int_latch_d(23);
       end if;
    end process;
 
@@ -586,7 +586,7 @@ begin
       if INT_LATCH_clrn(22)='0' then
 	 INT_LATCH_q(22) <= '0';
       elsif INT_LATCH_clk(22)'event and INT_LATCH_clk(22)='1' then
-	 INT_LATCH_q(22) <= INT_LATCH_d(22);
+	 INT_LATCH_q(22) <= int_latch_d(22);
       end if;
    end process;
 
@@ -594,7 +594,7 @@ begin
       if INT_LATCH_clrn(21)='0' then
 	 INT_LATCH_q(21) <= '0';
       elsif INT_LATCH_clk(21)'event and INT_LATCH_clk(21)='1' then
-	 INT_LATCH_q(21) <= INT_LATCH_d(21);
+	 INT_LATCH_q(21) <= int_latch_d(21);
       end if;
    end process;
 
@@ -602,7 +602,7 @@ begin
       if INT_LATCH_clrn(20)='0' then
 	 INT_LATCH_q(20) <= '0';
       elsif INT_LATCH_clk(20)'event and INT_LATCH_clk(20)='1' then
-	 INT_LATCH_q(20) <= INT_LATCH_d(20);
+	 INT_LATCH_q(20) <= int_latch_d(20);
       end if;
    end process;
 
@@ -610,7 +610,7 @@ begin
       if INT_LATCH_clrn(19)='0' then
 	 INT_LATCH_q(19) <= '0';
       elsif INT_LATCH_clk(19)'event and INT_LATCH_clk(19)='1' then
-	 INT_LATCH_q(19) <= INT_LATCH_d(19);
+	 INT_LATCH_q(19) <= int_latch_d(19);
       end if;
    end process;
 
@@ -618,7 +618,7 @@ begin
       if INT_LATCH_clrn(18)='0' then
 	 INT_LATCH_q(18) <= '0';
       elsif INT_LATCH_clk(18)'event and INT_LATCH_clk(18)='1' then
-	 INT_LATCH_q(18) <= INT_LATCH_d(18);
+	 INT_LATCH_q(18) <= int_latch_d(18);
       end if;
    end process;
 
@@ -626,7 +626,7 @@ begin
       if INT_LATCH_clrn(17)='0' then
 	 INT_LATCH_q(17) <= '0';
       elsif INT_LATCH_clk(17)'event and INT_LATCH_clk(17)='1' then
-	 INT_LATCH_q(17) <= INT_LATCH_d(17);
+	 INT_LATCH_q(17) <= int_latch_d(17);
       end if;
    end process;
 
@@ -634,7 +634,7 @@ begin
       if INT_LATCH_clrn(16)='0' then
 	 INT_LATCH_q(16) <= '0';
       elsif INT_LATCH_clk(16)'event and INT_LATCH_clk(16)='1' then
-	 INT_LATCH_q(16) <= INT_LATCH_d(16);
+	 INT_LATCH_q(16) <= int_latch_d(16);
       end if;
    end process;
 
@@ -642,7 +642,7 @@ begin
       if INT_LATCH_clrn(15)='0' then
 	 INT_LATCH_q(15) <= '0';
       elsif INT_LATCH_clk(15)'event and INT_LATCH_clk(15)='1' then
-	 INT_LATCH_q(15) <= INT_LATCH_d(15);
+	 INT_LATCH_q(15) <= int_latch_d(15);
       end if;
    end process;
 
@@ -650,7 +650,7 @@ begin
       if INT_LATCH_clrn(14)='0' then
 	 INT_LATCH_q(14) <= '0';
       elsif INT_LATCH_clk(14)'event and INT_LATCH_clk(14)='1' then
-	 INT_LATCH_q(14) <= INT_LATCH_d(14);
+	 INT_LATCH_q(14) <= int_latch_d(14);
       end if;
    end process;
 
@@ -658,7 +658,7 @@ begin
       if INT_LATCH_clrn(13)='0' then
 	 INT_LATCH_q(13) <= '0';
       elsif INT_LATCH_clk(13)'event and INT_LATCH_clk(13)='1' then
-	 INT_LATCH_q(13) <= INT_LATCH_d(13);
+	 INT_LATCH_q(13) <= int_latch_d(13);
       end if;
    end process;
 
@@ -666,7 +666,7 @@ begin
       if INT_LATCH_clrn(12)='0' then
 	 INT_LATCH_q(12) <= '0';
       elsif INT_LATCH_clk(12)'event and INT_LATCH_clk(12)='1' then
-	 INT_LATCH_q(12) <= INT_LATCH_d(12);
+	 INT_LATCH_q(12) <= int_latch_d(12);
       end if;
    end process;
 
@@ -674,7 +674,7 @@ begin
       if INT_LATCH_clrn(11)='0' then
 	 INT_LATCH_q(11) <= '0';
       elsif INT_LATCH_clk(11)'event and INT_LATCH_clk(11)='1' then
-	 INT_LATCH_q(11) <= INT_LATCH_d(11);
+	 INT_LATCH_q(11) <= int_latch_d(11);
       end if;
    end process;
 
@@ -682,7 +682,7 @@ begin
       if INT_LATCH_clrn(10)='0' then
 	 INT_LATCH_q(10) <= '0';
       elsif INT_LATCH_clk(10)'event and INT_LATCH_clk(10)='1' then
-	 INT_LATCH_q(10) <= INT_LATCH_d(10);
+	 INT_LATCH_q(10) <= int_latch_d(10);
       end if;
    end process;
 
@@ -690,7 +690,7 @@ begin
       if INT_LATCH_clrn(9)='0' then
 	 INT_LATCH_q(9) <= '0';
       elsif INT_LATCH9_clk_1'event and INT_LATCH9_clk_1='1' then
-	 INT_LATCH_q(9) <= INT_LATCH_d(9);
+	 INT_LATCH_q(9) <= int_latch_d(9);
       end if;
    end process;
 
@@ -698,7 +698,7 @@ begin
       if INT_LATCH_clrn(8)='0' then
 	 INT_LATCH_q(8) <= '0';
       elsif INT_LATCH8_clk_1'event and INT_LATCH8_clk_1='1' then
-	 INT_LATCH_q(8) <= INT_LATCH_d(8);
+	 INT_LATCH_q(8) <= int_latch_d(8);
       end if;
    end process;
 
@@ -706,7 +706,7 @@ begin
       if INT_LATCH_clrn(7)='0' then
 	 INT_LATCH_q(7) <= '0';
       elsif INT_LATCH7_clk_1'event and INT_LATCH7_clk_1='1' then
-	 INT_LATCH_q(7) <= INT_LATCH_d(7);
+	 INT_LATCH_q(7) <= int_latch_d(7);
       end if;
    end process;
 
@@ -714,7 +714,7 @@ begin
       if INT_LATCH_clrn(6)='0' then
 	 INT_LATCH_q(6) <= '0';
       elsif INT_LATCH6_clk_1'event and INT_LATCH6_clk_1='1' then
-	 INT_LATCH_q(6) <= INT_LATCH_d(6);
+	 INT_LATCH_q(6) <= int_latch_d(6);
       end if;
    end process;
 
@@ -722,7 +722,7 @@ begin
       if INT_LATCH_clrn(5)='0' then
 	 INT_LATCH_q(5) <= '0';
       elsif INT_LATCH5_clk_1'event and INT_LATCH5_clk_1='1' then
-	 INT_LATCH_q(5) <= INT_LATCH_d(5);
+	 INT_LATCH_q(5) <= int_latch_d(5);
       end if;
    end process;
 
@@ -730,7 +730,7 @@ begin
       if INT_LATCH_clrn(4)='0' then
 	 INT_LATCH_q(4) <= '0';
       elsif INT_LATCH4_clk_1'event and INT_LATCH4_clk_1='1' then
-	 INT_LATCH_q(4) <= INT_LATCH_d(4);
+	 INT_LATCH_q(4) <= int_latch_d(4);
       end if;
    end process;
 
@@ -738,7 +738,7 @@ begin
       if INT_LATCH_clrn(3)='0' then
 	 INT_LATCH_q(3) <= '0';
       elsif INT_LATCH3_clk_1'event and INT_LATCH3_clk_1='1' then
-	 INT_LATCH_q(3) <= INT_LATCH_d(3);
+	 INT_LATCH_q(3) <= int_latch_d(3);
       end if;
    end process;
 
@@ -746,7 +746,7 @@ begin
       if INT_LATCH_clrn(2)='0' then
 	 INT_LATCH_q(2) <= '0';
       elsif INT_LATCH2_clk_1'event and INT_LATCH2_clk_1='1' then
-	 INT_LATCH_q(2) <= INT_LATCH_d(2);
+	 INT_LATCH_q(2) <= int_latch_d(2);
       end if;
    end process;
 
@@ -754,7 +754,7 @@ begin
       if INT_LATCH_clrn(1)='0' then
 	 INT_LATCH_q(1) <= '0';
       elsif INT_LATCH1_clk_1'event and INT_LATCH1_clk_1='1' then
-	 INT_LATCH_q(1) <= INT_LATCH_d(1);
+	 INT_LATCH_q(1) <= int_latch_d(1);
       end if;
    end process;
 
@@ -763,7 +763,7 @@ begin
         if INT_LATCH_clrn(0)='0' then
             INT_LATCH_q(0) <= '0';
         elsif INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' then
-            INT_LATCH_q(0) <= INT_LATCH_d(0);
+            INT_LATCH_q(0) <= int_latch_d(0);
         end if;
     end process;
 
@@ -5030,7 +5030,7 @@ begin
 --  HWORD
 --  HHBYT
 --  LONG UND LINE
-    FB_B(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or
+    fb_b(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or
                ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and (not FB_ADR(0))) or
                ((not FB_SIZE1) and (not FB_SIZE0)) or
                (FB_SIZE1 and FB_SIZE0);
@@ -5038,7 +5038,7 @@ begin
 --  HWORD
 --  HLBYT
 --  LONG UND LINE
-    FB_B(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or
+    fb_b(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or
                ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and FB_ADR(0)) or
                ((not FB_SIZE1) and (not FB_SIZE0)) or
                (FB_SIZE1 and FB_SIZE0);
@@ -5046,14 +5046,14 @@ begin
 --  LWORD
 --  LHBYT
 --  LONG UND LINE
-    FB_B(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or
+    fb_b(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or
                ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and (not FB_ADR(0))) or
                ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0);
 
 --  LWORD
 --  LLBYT
 --  LONG UND LINE
-    FB_B(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or
+    fb_b(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or
                ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and FB_ADR(0)) or
                ((not FB_SIZE1) and (not FB_SIZE0)) or
                (FB_SIZE1 and FB_SIZE0);
@@ -5063,11 +5063,11 @@ begin
 
 --  $10000/4
     int_ctr_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0';
-    INT_CTR_d <= fb_ad_in;
-    INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR);
-    INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR);
-    INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR);
-    INT_CTR0_ena_ctrl <= INT_CTR_CS and FB_B(3) and (not nFB_WR);
+    int_ctr_d <= fb_ad_in;
+    INT_CTR24_ena_ctrl <= INT_CTR_CS and fb_b(0) and (not nFB_WR);
+    INT_CTR16_ena_ctrl <= INT_CTR_CS and fb_b(1) and (not nFB_WR);
+    INT_CTR8_ena_ctrl <= INT_CTR_CS and fb_b(2) and (not nFB_WR);
+    INT_CTR0_ena_ctrl <= INT_CTR_CS and fb_b(3) and (not nFB_WR);
 
 --  INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
     INT_ENA0_clk_ctrl <= MAIN_CLK;
@@ -5079,10 +5079,10 @@ begin
     -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) =
     -- "00000000000100000000000001");
     INT_ENA_d <= fb_ad_in;
-    INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR);
-    INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR);
-    INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR);
-    INT_ENA0_ena_ctrl <= INT_ENA_CS and FB_B(3) and (not nFB_WR);
+    INT_ENA24_ena_ctrl <= INT_ENA_CS and fb_b(0) and (not nFB_WR);
+    INT_ENA16_ena_ctrl <= INT_ENA_CS and fb_b(1) and (not nFB_WR);
+    INT_ENA8_ena_ctrl <= INT_ENA_CS and fb_b(2) and (not nFB_WR);
+    INT_ENA0_ena_ctrl <= INT_ENA_CS and fb_b(3) and (not nFB_WR);
 
 --  INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
     INT_CLEAR0_clk_ctrl <= MAIN_CLK;
@@ -5091,16 +5091,17 @@ begin
     int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0';
     -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000100000000000010");
 
+    
     int_clear_d(31 downto 24) <= fb_ad_in(31 downto 24) when int_clear_cs and fb_b(0) and not nfb_wr;
     int_clear_d(23 downto 16) <= fb_ad_in(23 downto 16) when int_clear_cs and fb_b(1) and not nfb_wr;
     int_clear_d(15 downto 8) <= fb_ad_in(15 downto 8) when int_clear_cs and fb_b(2) and not nfb_wr;
     int_clear_d(7 downto 0) <= fb_ad_in(7 downto 0) when int_clear_cs and fb_b(3) and not nfb_wr;
 
         
---    INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8);
---    INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8);
---    INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8);
---    INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8);
+--    INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(0),8) and sizeIt(not nFB_WR,8);
+--    INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(1),8) and sizeIt(not nFB_WR,8);
+--    INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(2),8) and sizeIt(not nFB_WR,8);
+--    INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(3),8) and sizeIt(not nFB_WR,8);
 
 --  INTERRUPT LATCH REGISTER READ ONLY
 --  $1000C/4
@@ -5110,7 +5111,7 @@ begin
 
 --  INTERRUPT
     nIRQ(2) <= not (HSYNC and INT_ENA_q(26));
-    nIRQ(3) <= not (INT_CTR_q(0) and INT_ENA_q(27));
+    nIRQ(3) <= not (int_ctr_q(0) and INT_ENA_q(27));
     nIRQ(4) <= not (VSYNC and INT_ENA_q(28));
     nIRQ(5) <= not (to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000") and INT_ENA_q(29));
     nIRQ(6) <= not ((not nMFP_INT) and INT_ENA_q(30));
@@ -5168,7 +5169,7 @@ begin
     INT_LA2_0_clk_ctrl <= MAIN_CLK;
     INT_LA1_0_clk_ctrl <= MAIN_CLK;
     INT_LA0_0_clk_ctrl <= MAIN_CLK;
-    INT_LATCH_d <= "11111111111111111111111111111111";
+    int_latch_d <= "11111111111111111111111111111111";
     INT_LATCH_clrn <= (not INT_CLEAR_q) and sizeIt(nRSTO,32);
     INT_LA0_0_clrn_ctrl <= INT_ENA_q(0) and nRSTO;
     INT_LA0_d <= ((std_logic_vector'(unsigned(INT_LA0_q) + unsigned'("0001"))) and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q)
@@ -5292,7 +5293,7 @@ begin
     INT_IN(9) <= HSYNC;
     INT_IN(25 downto 10) <= "0000000000000000";
     INT_IN(26) <= HSYNC;
-    INT_IN(27) <= INT_CTR_q(0);
+    INT_IN(27) <= int_ctr_q(0);
     INT_IN(28) <= VSYNC;
     INT_IN(29) <= to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000");
     INT_IN(30) <= not nMFP_INT;
@@ -5305,10 +5306,10 @@ begin
     --  $4'0000/4
     ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000010000000000000000");
     ACP_CONF_d <= fb_ad_in;
-    ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR);
-    ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR);
-    ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR);
-    ACP_CONF0_ena_ctrl <= ACP_CONF_CS and FB_B(3) and (not nFB_WR);
+    ACP_CONF24_ena_ctrl <= ACP_CONF_CS and fb_b(0) and (not nFB_WR);
+    ACP_CONF16_ena_ctrl <= ACP_CONF_CS and fb_b(1) and (not nFB_WR);
+    ACP_CONF8_ena_ctrl <= ACP_CONF_CS and fb_b(2) and (not nFB_WR);
+    ACP_CONF0_ena_ctrl <= ACP_CONF_CS and fb_b(3) and (not nFB_WR);
 
     -- ***************************************************************************************
     -- ------------------------------------------------------------
@@ -5318,10 +5319,10 @@ begin
     RTC_ADR_d <= fb_ad_in(21 downto 16);
 
     --  FFFF8961
-    UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110000") and FB_B(1);
+    UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110000") and fb_b(1);
 
     --  FFFF8963
-    UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110001") and FB_B(3);
+    UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110001") and fb_b(3);
     RTC_ADR0_ena_ctrl <= UHR_AS and (not nFB_WR);
     WERTE7_0_clk_ctrl <= MAIN_CLK;
     WERTE6_0_clk_ctrl <= MAIN_CLK;
@@ -5964,7 +5965,7 @@ begin
 	 "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8)));
 
 --  TRISTATE OUTPUT
---   u0_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(31 downto 24)) or
+--   u0_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(31 downto 24)) or
 --	 (sizeIt(INT_ENA_CS,8) and INT_ENA_q(31 downto 24)) or
 --	 (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(31 downto 24)) or
 --	 (sizeIt(INT_CLEAR_CS,8) and INT_IN(31 downto 24)) or
@@ -6191,7 +6192,7 @@ begin
 	 WERTE2_q(63) & WERTE1_q(63) & WERTE0_q(63)) and
 	 sizeIt(to_std_logic(RTC_ADR_q = "111111"),8) and sizeIt(UHR_DS,8)) or
 	 (std_logic_vector'("00" & RTC_ADR_q) and sizeIt(UHR_AS,8)) or
-	 (sizeIt(INT_CTR_CS,8) and INT_CTR_q(23 downto 16)) or
+	 (sizeIt(INT_CTR_CS,8) and int_ctr_q(23 downto 16)) or
 	 (sizeIt(INT_ENA_CS,8) and INT_ENA_q(23 downto 16)) or
 	 (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(23 downto 16)) or
 	 (sizeIt(INT_CLEAR_CS,8) and INT_IN(23 downto 16)) or
@@ -6200,7 +6201,7 @@ begin
     u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE);  
     fb_ad_out(23 downto 16) <= u1_tridata;
    
---   u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 downto 8)) or
+--   u2_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(15 downto 8)) or
 --	 (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 downto 8)) or
 --	 (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 downto 8)) or
 --	 (sizeIt(INT_CLEAR_CS,8) and INT_IN(15 downto 8)) or
@@ -6216,7 +6217,7 @@ begin
                               acp_conf_q(15 downto 8) when acp_conf_cs and not nfb_oe else
                               (others => 'Z');
                               
---   u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 downto 0)) or
+--   u3_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(7 downto 0)) or
 --	 (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 downto 0)) or
 --	 (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 downto 0)) or
 --	 (sizeIt(INT_CLEAR_CS,8) and INT_IN(7 downto 0)) or
diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf
index a9a68e7..85aadb8 100644
--- a/FPGA_Quartus_13.1/firebee1.qsf
+++ b/FPGA_Quartus_13.1/firebee1.qsf
@@ -39,389 +39,389 @@
 
 # Project-Wide Assignments
 # ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 
 # Pin & Location Assignments
 # ==========================
-set_location_assignment PIN_G2 -to MAIN_CLK
-set_location_assignment PIN_Y3 -to FB_AD[0]
-set_location_assignment PIN_Y6 -to FB_AD[1]
-set_location_assignment PIN_AA3 -to FB_AD[2]
-set_location_assignment PIN_AB3 -to FB_AD[3]
-set_location_assignment PIN_W6 -to FB_AD[4]
-set_location_assignment PIN_V7 -to FB_AD[5]
-set_location_assignment PIN_AA4 -to FB_AD[6]
-set_location_assignment PIN_AB4 -to FB_AD[7]
-set_location_assignment PIN_AA5 -to FB_AD[8]
-set_location_assignment PIN_AB5 -to FB_AD[9]
-set_location_assignment PIN_W7 -to FB_AD[10]
-set_location_assignment PIN_Y7 -to FB_AD[11]
-set_location_assignment PIN_U9 -to FB_AD[12]
-set_location_assignment PIN_V8 -to FB_AD[13]
-set_location_assignment PIN_W8 -to FB_AD[14]
-set_location_assignment PIN_AA7 -to FB_AD[15]
-set_location_assignment PIN_AB7 -to FB_AD[16]
-set_location_assignment PIN_Y8 -to FB_AD[17]
-set_location_assignment PIN_V9 -to FB_AD[18]
-set_location_assignment PIN_V10 -to FB_AD[19]
-set_location_assignment PIN_T10 -to FB_AD[20]
-set_location_assignment PIN_U10 -to FB_AD[21]
-set_location_assignment PIN_AA8 -to FB_AD[22]
-set_location_assignment PIN_AB8 -to FB_AD[23]
-set_location_assignment PIN_T11 -to FB_AD[24]
-set_location_assignment PIN_AA9 -to FB_AD[25]
-set_location_assignment PIN_AB9 -to FB_AD[26]
-set_location_assignment PIN_U11 -to FB_AD[27]
-set_location_assignment PIN_V11 -to FB_AD[28]
-set_location_assignment PIN_W10 -to FB_AD[29]
-set_location_assignment PIN_Y10 -to FB_AD[30]
-set_location_assignment PIN_AA10 -to FB_AD[31]
-set_location_assignment PIN_R7 -to FB_ALE
-set_location_assignment PIN_N19 -to LED_FPGA_OK
-set_location_assignment PIN_AB10 -to CLK24M576
-set_location_assignment PIN_J1 -to CLKUSB
-set_location_assignment PIN_T4 -to CLK25M
-set_location_assignment PIN_U8 -to FB_SIZE0
-set_location_assignment PIN_Y4 -to FB_SIZE1
-set_location_assignment PIN_T3 -to nFB_BURST
-set_location_assignment PIN_T8 -to nFB_CS1
-set_location_assignment PIN_T9 -to nFB_CS2
-set_location_assignment PIN_V6 -to nFB_CS3
-set_location_assignment PIN_R6 -to nFB_OE
-set_location_assignment PIN_T5 -to nFB_WR
-set_location_assignment PIN_R5 -to TIN0
-set_location_assignment PIN_T21 -to nMASTER
-set_location_assignment PIN_E11 -to nDREQ1
-set_location_assignment PIN_A12 -to nDACK1
-set_location_assignment PIN_B12 -to nDACK0
-set_location_assignment PIN_T22 -to TOUT0
-set_location_assignment PIN_AB17 -to DDR_CLK
-set_location_assignment PIN_AA17 -to nDDR_CLK
-set_location_assignment PIN_AB18 -to nVCAS
-set_location_assignment PIN_T18 -to nVCS
-set_location_assignment PIN_W17 -to nVRAS
-set_location_assignment PIN_Y17 -to nVWE
-set_location_assignment PIN_W20 -to VA[0]
-set_location_assignment PIN_W22 -to VA[1]
-set_location_assignment PIN_W21 -to VA[2]
-set_location_assignment PIN_Y22 -to VA[3]
-set_location_assignment PIN_AA22 -to VA[4]
-set_location_assignment PIN_Y21 -to VA[5]
-set_location_assignment PIN_AA21 -to VA[6]
-set_location_assignment PIN_AA20 -to VA[7]
-set_location_assignment PIN_AB20 -to VA[8]
-set_location_assignment PIN_AB19 -to VA[9]
-set_location_assignment PIN_V21 -to VA[10]
-set_location_assignment PIN_U19 -to VA[11]
-set_location_assignment PIN_AA18 -to VA[12]
-set_location_assignment PIN_U15 -to VCKE
-set_location_assignment PIN_M22 -to VD[0]
-set_location_assignment PIN_M21 -to VD[1]
-set_location_assignment PIN_P22 -to VD[2]
-set_location_assignment PIN_R20 -to VD[3]
-set_location_assignment PIN_P21 -to VD[4]
-set_location_assignment PIN_R17 -to VD[5]
-set_location_assignment PIN_R19 -to VD[6]
-set_location_assignment PIN_U21 -to VD[7]
-set_location_assignment PIN_V22 -to VD[8]
-set_location_assignment PIN_R18 -to VD[9]
-set_location_assignment PIN_P17 -to VD[10]
-set_location_assignment PIN_R21 -to VD[11]
-set_location_assignment PIN_N17 -to VD[12]
-set_location_assignment PIN_P20 -to VD[13]
-set_location_assignment PIN_R22 -to VD[14]
-set_location_assignment PIN_N20 -to VD[15]
-set_location_assignment PIN_T12 -to VD[16]
-set_location_assignment PIN_Y13 -to VD[17]
-set_location_assignment PIN_AA13 -to VD[18]
-set_location_assignment PIN_V14 -to VD[19]
-set_location_assignment PIN_U13 -to VD[20]
-set_location_assignment PIN_V15 -to VD[21]
-set_location_assignment PIN_W14 -to VD[22]
-set_location_assignment PIN_AB16 -to VD[23]
-set_location_assignment PIN_AB15 -to VD[24]
-set_location_assignment PIN_AA14 -to VD[25]
-set_location_assignment PIN_AB14 -to VD[26]
-set_location_assignment PIN_V13 -to VD[27]
-set_location_assignment PIN_W13 -to VD[28]
-set_location_assignment PIN_AB13 -to VD[29]
-set_location_assignment PIN_V12 -to VD[30]
-set_location_assignment PIN_U12 -to VD[31]
-set_location_assignment PIN_AA16 -to VDM[0]
-set_location_assignment PIN_V16 -to VDM[1]
-set_location_assignment PIN_U20 -to VDM[2]
-set_location_assignment PIN_T17 -to VDM[3]
-set_location_assignment PIN_AA15 -to VDQS[0]
-set_location_assignment PIN_W15 -to VDQS[1]
-set_location_assignment PIN_U22 -to VDQS[2]
-set_location_assignment PIN_T16 -to VDQS[3]
-set_location_assignment PIN_V1 -to nPD_VGA
-set_location_assignment PIN_G18 -to VB[0]
-set_location_assignment PIN_H17 -to VB[1]
-set_location_assignment PIN_C22 -to VB[2]
-set_location_assignment PIN_C21 -to VB[3]
-set_location_assignment PIN_B22 -to VB[4]
-set_location_assignment PIN_B21 -to VB[5]
-set_location_assignment PIN_C20 -to VB[6]
-set_location_assignment PIN_D20 -to VB[7]
-set_location_assignment PIN_H19 -to VG[0]
-set_location_assignment PIN_E22 -to VG[1]
-set_location_assignment PIN_E21 -to VG[2]
-set_location_assignment PIN_H18 -to VG[3]
-set_location_assignment PIN_J17 -to VG[4]
-set_location_assignment PIN_H16 -to VG[5]
-set_location_assignment PIN_D22 -to VG[6]
-set_location_assignment PIN_D21 -to VG[7]
-set_location_assignment PIN_J22 -to VR[0]
-set_location_assignment PIN_J21 -to VR[1]
-set_location_assignment PIN_H22 -to VR[2]
-set_location_assignment PIN_H21 -to VR[3]
-set_location_assignment PIN_K17 -to VR[4]
-set_location_assignment PIN_K18 -to VR[5]
-set_location_assignment PIN_J18 -to VR[6]
-set_location_assignment PIN_F22 -to VR[7]
-set_location_assignment PIN_M6 -to ACSI_A1
-set_location_assignment PIN_B1 -to ACSI_D[0]
-set_location_assignment PIN_G5 -to ACSI_D[1]
-set_location_assignment PIN_E3 -to ACSI_D[2]
-set_location_assignment PIN_C2 -to ACSI_D[3]
-set_location_assignment PIN_C1 -to ACSI_D[4]
-set_location_assignment PIN_D2 -to ACSI_D[5]
-set_location_assignment PIN_H7 -to ACSI_D[6]
-set_location_assignment PIN_H6 -to ACSI_D[7]
-set_location_assignment PIN_L6 -to ACSI_DIR
-set_location_assignment PIN_N1 -to AMKB_TX
-set_location_assignment PIN_F15 -to DSA_D
-set_location_assignment PIN_D15 -to DTR
-set_location_assignment PIN_A11 -to DVI_INT
-set_location_assignment PIN_G21 -to E0_INT
-set_location_assignment PIN_M5 -to IDE_RES
-set_location_assignment PIN_A8 -to IO[0]
-set_location_assignment PIN_A7 -to IO[1]
-set_location_assignment PIN_B7 -to IO[2]
-set_location_assignment PIN_A6 -to IO[3]
-set_location_assignment PIN_B6 -to IO[4]
-set_location_assignment PIN_E9 -to IO[5]
-set_location_assignment PIN_C8 -to IO[6]
-set_location_assignment PIN_C7 -to IO[7]
-set_location_assignment PIN_G10 -to IO[8]
-set_location_assignment PIN_A15 -to IO[9]
-set_location_assignment PIN_B15 -to IO[10]
-set_location_assignment PIN_C13 -to IO[11]
-set_location_assignment PIN_D13 -to IO[12]
-set_location_assignment PIN_E13 -to IO[13]
-set_location_assignment PIN_A14 -to IO[14]
-set_location_assignment PIN_B14 -to IO[15]
-set_location_assignment PIN_A13 -to IO[16]
-set_location_assignment PIN_B13 -to IO[17]
-set_location_assignment PIN_F7 -to LP_D[0]
-set_location_assignment PIN_C4 -to LP_D[1]
-set_location_assignment PIN_C3 -to LP_D[2]
-set_location_assignment PIN_E7 -to LP_D[3]
-set_location_assignment PIN_D6 -to LP_D[4]
-set_location_assignment PIN_B3 -to LP_D[5]
-set_location_assignment PIN_A3 -to LP_D[6]
-set_location_assignment PIN_G8 -to LP_D[7]
-set_location_assignment PIN_E6 -to LP_STR
-set_location_assignment PIN_H5 -to MIDI_OLR
-set_location_assignment PIN_B2 -to MIDI_TLR
-set_location_assignment PIN_M4 -to nACSI_ACK
-set_location_assignment PIN_M2 -to nACSI_CS
-set_location_assignment PIN_M1 -to nACSI_RESET
-set_location_assignment PIN_W2 -to nCF_CS0
-set_location_assignment PIN_W1 -to nCF_CS1
-set_location_assignment PIN_T7 -to nFB_TA
-set_location_assignment PIN_R2 -to nIDE_CS0
-set_location_assignment PIN_R1 -to nIDE_CS1
-set_location_assignment PIN_P1 -to nIDE_RD
-set_location_assignment PIN_P2 -to nIDE_WR
-set_location_assignment PIN_F21 -to nIRQ[2]
-set_location_assignment PIN_H20 -to nIRQ[3]
-set_location_assignment PIN_F20 -to nIRQ[4]
-set_location_assignment PIN_P5 -to nIRQ[5]
-set_location_assignment PIN_P7 -to nIRQ[6]
-set_location_assignment PIN_N7 -to nIRQ[7]
-set_location_assignment PIN_AA1 -to nPCI_INTA
-set_location_assignment PIN_V4 -to nPCI_INTB
-set_location_assignment PIN_V3 -to nPCI_INTC
-set_location_assignment PIN_P6 -to nPCI_INTD
-set_location_assignment PIN_P3 -to nROM3
-set_location_assignment PIN_U2 -to nROM4
-set_location_assignment PIN_N5 -to nRP_LDS
-set_location_assignment PIN_P4 -to nRP_UDS
-set_location_assignment PIN_N2 -to nSCSI_ACK
-set_location_assignment PIN_M3 -to nSCSI_ATN
-set_location_assignment PIN_N8 -to nSCSI_BUSY
-set_location_assignment PIN_N6 -to nSCSI_RST
-set_location_assignment PIN_M8 -to nSCSI_SEL
-set_location_assignment PIN_B20 -to nSDSEL
-set_location_assignment PIN_B4 -to nSRBHE
-set_location_assignment PIN_A4 -to nSRBLE
-set_location_assignment PIN_B8 -to nSRCS
-set_location_assignment PIN_F11 -to nSROE
-set_location_assignment PIN_F8 -to nSRWE
-set_location_assignment PIN_G14 -to nWR
-set_location_assignment PIN_D17 -to nWR_GATE
-set_location_assignment PIN_AA2 -to PIC_INT
-set_location_assignment PIN_B18 -to RTS
-set_location_assignment PIN_J6 -to SCSI_D[0]
-set_location_assignment PIN_E1 -to SCSI_D[1]
-set_location_assignment PIN_F2 -to SCSI_D[2]
-set_location_assignment PIN_F1 -to SCSI_D[3]
-set_location_assignment PIN_G4 -to SCSI_D[4]
-set_location_assignment PIN_G3 -to SCSI_D[5]
-set_location_assignment PIN_L8 -to SCSI_D[6]
-set_location_assignment PIN_K8 -to SCSI_D[7]
-set_location_assignment PIN_J7 -to SCSI_DIR
-set_location_assignment PIN_M7 -to SCSI_PAR
-set_location_assignment PIN_F13 -to SD_CD_DATA3
-set_location_assignment PIN_C15 -to SD_CLK
-set_location_assignment PIN_E14 -to SD_CMD_D1
-set_location_assignment PIN_B5 -to SRD[0]
-set_location_assignment PIN_A5 -to SRD[1]
-set_location_assignment PIN_C6 -to SRD[2]
-set_location_assignment PIN_G11 -to SRD[3]
-set_location_assignment PIN_C10 -to SRD[4]
-set_location_assignment PIN_F9 -to SRD[5]
-set_location_assignment PIN_E10 -to SRD[6]
-set_location_assignment PIN_H11 -to SRD[7]
-set_location_assignment PIN_B9 -to SRD[8]
-set_location_assignment PIN_A10 -to SRD[9]
-set_location_assignment PIN_A9 -to SRD[10]
-set_location_assignment PIN_B10 -to SRD[11]
-set_location_assignment PIN_D10 -to SRD[12]
-set_location_assignment PIN_F10 -to SRD[13]
-set_location_assignment PIN_G9 -to SRD[14]
-set_location_assignment PIN_H10 -to SRD[15]
-set_location_assignment PIN_A18 -to TxD
-set_location_assignment PIN_A17 -to YM_QA
-set_location_assignment PIN_G13 -to YM_QB
-set_location_assignment PIN_E15 -to YM_QC
-set_location_assignment PIN_T1 -to WP_CF_CARD
-set_location_assignment PIN_C19 -to TRACK00
-set_location_assignment PIN_M19 -to SD_WP
-set_location_assignment PIN_B17 -to SD_DATA2
-set_location_assignment PIN_A16 -to SD_DATA1
-set_location_assignment PIN_B16 -to SD_DATA0
-set_location_assignment PIN_M20 -to SD_CARD_DEDECT
-set_location_assignment PIN_H15 -to RxD
-set_location_assignment PIN_B19 -to RI
-set_location_assignment PIN_L7 -to PIC_AMKB_RX
-set_location_assignment PIN_D19 -to nWP
-set_location_assignment PIN_H2 -to nSCSI_MSG
-set_location_assignment PIN_J3 -to nSCSI_I_O
-set_location_assignment PIN_U1 -to nSCSI_DRQ
-set_location_assignment PIN_H1 -to nSCSI_C_D
-set_location_assignment PIN_A20 -to nRD_DATA
-set_location_assignment PIN_C17 -to nDCHG
-set_location_assignment PIN_J4 -to nACSI_INT
-set_location_assignment PIN_K7 -to nACSI_DRQ
-set_location_assignment PIN_G7 -to LP_BUSY
-set_location_assignment PIN_Y1 -to IDE_RDY
-set_location_assignment PIN_G22 -to IDE_INT
-set_location_assignment PIN_F16 -to HD_DD
-set_location_assignment PIN_A19 -to DCD
-set_location_assignment PIN_H14 -to CTS
-set_location_assignment PIN_Y2 -to AMKB_RX
-set_location_assignment PIN_E16 -to nINDEX
-set_location_assignment PIN_W19 -to BA[0]
-set_location_assignment PIN_AA19 -to BA[1]
-set_location_assignment PIN_K21 -to HSYNC_PAD
-set_location_assignment PIN_K19 -to VSYNC_PAD
-set_location_assignment PIN_G17 -to nBLANK_PAD
-set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
-set_location_assignment PIN_F17 -to nSYNC
-set_location_assignment PIN_G15 -to nSTEP_DIR
-set_location_assignment PIN_F14 -to nSTEP
-set_location_assignment PIN_G16 -to nMOT_ON
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
 
 # Classic Timing Assignments
 # ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name TPD_REQUIREMENT "1 ns"
-set_global_assignment -name TSU_REQUIREMENT "1 ns"
-set_global_assignment -name TCO_REQUIREMENT "1 ns"
-set_global_assignment -name TH_REQUIREMENT "1 ns"
-set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "30 ns"
 
 # Analysis & Synthesis Assignments
 # ================================
-set_global_assignment -name FAMILY CycloneIII
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SAFE_STATE_MACHINE OFF
-set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+set_global_assignment -name FAMILY CycloneIII
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
 
 # Fitter Assignments
 # ==================
-set_global_assignment -name DEVICE EP3C40F484C6
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
 
 # Assembler Assignments
 # =====================
-set_global_assignment -name GENERATE_TTF_FILE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name GENERATE_HEX_FILE OFF
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
 
 # Simulator Assignments
 # =====================
-set_global_assignment -name END_TIME "2 us"
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
-set_global_assignment -name SETUP_HOLD_DETECTION OFF
-set_global_assignment -name GLITCH_DETECTION OFF
-set_global_assignment -name CHECK_OUTPUTS OFF
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
 
 # start EDA_TOOL_SETTINGS(eda_blast_fpga)
 # ---------------------------------------
 
 	# Analysis & Synthesis Assignments
 	# ================================
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
 
 # end EDA_TOOL_SETTINGS(eda_blast_fpga)
 # -------------------------------------
@@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e
 
 	# Classic Timing Assignments
 	# ==========================
-set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 # end CLOCK(fast)
 # ---------------
@@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 	# Assignment Group Assignments
 	# ============================
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
 
 # end ASSIGNMENT_GROUP(fast)
 # --------------------------
@@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_
 
 	# Classic Timing Assignments
 	# ==========================
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
-set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
-set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
 
 	# Fitter Assignments
 	# ==================
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
 
 	# Simulator Assignments
 	# =====================
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 	# start LOGICLOCK_REGION(Root Region)
 	# -----------------------------------
@@ -556,314 +556,314 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 # end ENTITY(firebee1)
 # --------------------
-set_location_assignment PIN_E5 -to LPDIR
-set_location_assignment PIN_B11 -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
-set_location_assignment PIN_AB12 -to CLK33MDIR
-set_location_assignment PIN_E12 -to MIDI_IN_PIN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
-set_instance_assignment -name PCI_IO ON -to nPCI_INTA
-set_instance_assignment -name PCI_IO ON -to nPCI_INTB
-set_instance_assignment -name PCI_IO ON -to nPCI_INTC
-set_instance_assignment -name PCI_IO ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name SMART_RECOMPILE ON
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name TOP_LEVEL_ENTITY firebee1
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
-set_global_assignment -name VHDL_FILE video/video.vhd
-set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd
-set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
-set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
-set_global_assignment -name AHDL_FILE altpll4.tdf
-set_global_assignment -name SDC_FILE firebee_groups.sdc
-set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd
-set_global_assignment -name VHDL_FILE video/ddr_controller.vhd
-set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
-set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
-set_global_assignment -name SOURCE_FILE altpll4.cmp
-set_global_assignment -name VHDL_FILE firebee1.vhd
-set_global_assignment -name VHDL_FILE video/mux41.vhd
-set_global_assignment -name VHDL_FILE video/mux41_5.vhd
-set_global_assignment -name VHDL_FILE video/mux41_4.vhd
-set_global_assignment -name VHDL_FILE video/mux41_3.vhd
-set_global_assignment -name VHDL_FILE video/mux41_2.vhd
-set_global_assignment -name VHDL_FILE video/mux41_1.vhd
-set_global_assignment -name VHDL_FILE video/mux41_0.vhd
-set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp
-set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp
-set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp
-set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp
-set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp
-set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp
-set_global_assignment -name SOURCE_FILE video/altdpram2.cmp
-set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp
-set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp
-set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp
-set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp
-set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp
-set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd
-set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp
-set_global_assignment -name SOURCE_FILE video/altdpram0.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp
-set_global_assignment -name VHDL_FILE video/altdpram0.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp
-set_global_assignment -name SOURCE_FILE video/altdpram1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp
-set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp
-set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp
-set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE video/altdpram0.qip
-set_global_assignment -name QIP_FILE video/lpm_bustri1.qip
-set_global_assignment -name QIP_FILE video/altdpram1.qip
-set_global_assignment -name QIP_FILE video/lpm_bustri2.qip
-set_global_assignment -name QIP_FILE video/lpm_bustri4.qip
-set_global_assignment -name QIP_FILE video/lpm_constant0.qip
-set_global_assignment -name QIP_FILE video/lpm_constant1.qip
-set_global_assignment -name QIP_FILE video/lpm_mux0.qip
-set_global_assignment -name QIP_FILE video/lpm_mux1.qip
-set_global_assignment -name QIP_FILE video/lpm_mux2.qip
-set_global_assignment -name QIP_FILE video/lpm_constant2.qip
-set_global_assignment -name QIP_FILE video/altdpram2.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip
-set_global_assignment -name QIP_FILE video/altddio_bidir0.qip
-set_global_assignment -name QIP_FILE video/altddio_out0.qip
-set_global_assignment -name QIP_FILE video/lpm_mux5.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip
-set_global_assignment -name QIP_FILE video/altddio_out1.qip
-set_global_assignment -name QIP_FILE video/altddio_out2.qip
-set_global_assignment -name QIP_FILE video/lpm_bustri6.qip
-set_global_assignment -name QIP_FILE video/lpm_mux6.qip
-set_global_assignment -name QIP_FILE video/lpm_mux3.qip
-set_global_assignment -name QIP_FILE video/lpm_mux4.qip
-set_global_assignment -name QIP_FILE video/lpm_constant3.qip
-set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip
-set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip
-set_global_assignment -name QIP_FILE video/lpm_latch1.qip
-set_global_assignment -name QIP_FILE video/lpm_constant4.qip
-set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip
-set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip
-set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT
-set_global_assignment -name QIP_FILE video/lpm_compare1.qip
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp
-set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp
-set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd
-set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp
-set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd
-set_global_assignment -name QIP_FILE video/lpm_ff4.qip
-set_global_assignment -name QIP_FILE video/lpm_ff5.qip
-set_global_assignment -name QIP_FILE video/lpm_ff6.qip
-set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp
-set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip
-set_global_assignment -name VHDL_FILE DSP/DSP.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
-set_global_assignment -name VHDL_FILE lpm_latch0.vhd
-set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
-set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name QIP_FILE altpll2.qip
-set_global_assignment -name QIP_FILE altpll3.qip
-set_global_assignment -name SOURCE_FILE altpll0.cmp
-set_global_assignment -name SOURCE_FILE altpll2.cmp
-set_global_assignment -name VHDL_FILE altpll2.vhd
-set_global_assignment -name SOURCE_FILE altpll3.cmp
-set_global_assignment -name VHDL_FILE altpll3.vhd
-set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
-set_global_assignment -name VHDL_FILE altpll1.vhd
-set_global_assignment -name SOURCE_FILE altpll1.cmp
-set_global_assignment -name QIP_FILE altpll0.qip
-set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
-set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
-set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
-set_global_assignment -name QIP_FILE altddio_out3.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
-set_global_assignment -name QIP_FILE altpll4.qip
-set_global_assignment -name QIP_FILE lpm_mux0.qip
-set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE lpm_counter1.qip
-set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
-set_global_assignment -name VHDL_FILE flexbus_register.vhd
-
-
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
+set_global_assignment -name VHDL_FILE video/video.vhd
+set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd
+set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
+set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
+set_global_assignment -name AHDL_FILE altpll4.tdf
+set_global_assignment -name SDC_FILE firebee_groups.sdc
+set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd
+set_global_assignment -name VHDL_FILE video/ddr_controller.vhd
+set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
+set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
+set_global_assignment -name SOURCE_FILE altpll4.cmp
+set_global_assignment -name VHDL_FILE firebee1.vhd
+set_global_assignment -name VHDL_FILE video/mux41.vhd
+set_global_assignment -name VHDL_FILE video/mux41_5.vhd
+set_global_assignment -name VHDL_FILE video/mux41_4.vhd
+set_global_assignment -name VHDL_FILE video/mux41_3.vhd
+set_global_assignment -name VHDL_FILE video/mux41_2.vhd
+set_global_assignment -name VHDL_FILE video/mux41_1.vhd
+set_global_assignment -name VHDL_FILE video/mux41_0.vhd
+set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp
+set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp
+set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp
+set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp
+set_global_assignment -name SOURCE_FILE video/altdpram2.cmp
+set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp
+set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd
+set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp
+set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE video/altdpram0.qip
+set_global_assignment -name QIP_FILE video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE video/altdpram1.qip
+set_global_assignment -name QIP_FILE video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE video/altdpram2.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE video/altddio_out0.qip
+set_global_assignment -name QIP_FILE video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE video/altddio_out1.qip
+set_global_assignment -name QIP_FILE video/altddio_out2.qip
+set_global_assignment -name QIP_FILE video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE video/lpm_mux6.qip
+set_global_assignment -name QIP_FILE video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip
+set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT
+set_global_assignment -name QIP_FILE video/lpm_compare1.qip
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp
+set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd
+set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp
+set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd
+set_global_assignment -name QIP_FILE video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE video/lpm_ff6.qip
+set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp
+set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
+set_global_assignment -name QIP_FILE altpll4.qip
+set_global_assignment -name QIP_FILE lpm_mux0.qip
+set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE lpm_counter1.qip
+set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
+set_global_assignment -name VHDL_FILE flexbus_register.vhd
+
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd
index fbce6a1..4c78b37 100644
--- a/FPGA_Quartus_13.1/firebee1.vhd
+++ b/FPGA_Quartus_13.1/firebee1.vhd
@@ -35,7 +35,7 @@ entity firebee1 is
 		SD_DATA0        : in std_logic;
 		SD_DATA1        : in std_logic;
 		SD_DATA2        : in std_logic;
-		SD_CARD_DEDECT  : in std_logic;
+		sd_card_detect  : in std_logic;
 		nSCSI_DRQ       : in std_logic;
 		SD_WP           : in std_logic;
 		nRD_DATA        : in std_logic;
@@ -331,7 +331,7 @@ begin
             SD_DATA0 => SD_DATA0,
             SD_DATA1 => SD_DATA1,
             SD_DATA2 => SD_DATA2,
-            SD_CARD_DEDECT => SD_CARD_DEDECT,
+            sd_card_dedect => sd_card_detect,
             SD_WP => SD_WP,
             nDACK0 => nDACK0,
             nFB_WR => nFB_WR,
diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc
index 16b6afb..02b3cb1 100644
--- a/FPGA_Quartus_13.1/firebee_groups.sdc
+++ b/FPGA_Quartus_13.1/firebee_groups.sdc
@@ -195,8 +195,11 @@ set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \
 #**************************************************************
 
 if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } {
-    post_message -type info "Over constraining hold"
+    post_message -type info "Over constraining hold for MAIN_CLK"
     set_clock_uncertainty -add -enable_same_physical_edge -from { MAIN_CLK } -to { MAIN_CLK } -hold 0.2
 }
 
- 
+if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } {
+    post_message -type info "Over constraining setup for i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]"
+    set_clock_uncertainty -add -enable_same_physical_edge -from { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -to { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -setup 0.2
+} 
diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd
index d7aea7e..df202a5 100644
--- a/FPGA_Quartus_13.1/flexbus_register.vhd
+++ b/FPGA_Quartus_13.1/flexbus_register.vhd
@@ -25,7 +25,7 @@ entity flexbus_register is
         fb_wr_n         : in std_logic;
         fb_oe_n         : in std_logic;
         fb_size         : in std_logic_vector(1 downto 0);
-        
+
         register_ta     : out std_logic
     );
 end entity flexbus_register;
@@ -71,10 +71,45 @@ begin
 
     fbcs_match <= '1' when not(fb_cs_n(match_fbcs)) = '1' else '0';
     address_match <= f_addr_cmp_mask(fb_addr, match_address, num_ignore);
-    
-    p_register_access : process(all)
-    begin
-        if rising_edge(clk) then
-        end if;
-    end process p_register_access;
+    cs <= '1' when fbcs_match and address_match else '0';
+    
+    p_copy_data_in : process (all)
+    begin
+        reg_value <= reg_value;
+        if cs and not fb_wr_n then
+            if reg_width > 24 and fb_b(0) = '1' then      -- HH byte
+                reg_value(reg_width - 1 downto 24) <= fb_ad_in(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24);
+            end if;
+            if reg_width > 16 and fb_b(1) = '1' then      -- HL byte
+                reg_value(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16) <= fb_ad_in(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16);
+            end if;
+            if reg_width > 8 and fb_b(2) = '1' then       -- LH byte
+                reg_value(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8) <= fb_ad_in(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8);
+            end if;
+            if reg_width > 0 and fb_b(3) = '1' then       -- LL byte
+                reg_value(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0) <= fb_ad_in(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0);
+            end if;
+        end if;
+    end process p_copy_data_in;
+    
+    p_copy_data_out : process (all)
+    begin
+        fb_ad_out <= (others => 'Z');
+        if cs and not fb_oe_n then
+            if reg_width > 24 and fb_b(0) = '1' then      -- HH byte
+                fb_ad_out(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24) <= reg_value(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24);
+            end if;
+            if reg_width > 16 and fb_b(1) = '1' then      -- HL byte
+                fb_ad_out(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16) <= reg_value(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16);
+            end if;
+            if reg_width > 8 and fb_b(2) = '1' then       -- LH byte
+                fb_ad_out(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8) <= reg_value(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8);
+            end if;
+            if reg_width > 0 and fb_b(3) = '1' then       -- LL byte
+                fb_ad_out(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0) <= reg_value(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0);
+            end if;
+        end if;            
+    end process p_copy_data_out;
+    
+    register_ta <= cs;
 end architecture rtl;
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/video/ddr_controller.vhd b/FPGA_Quartus_13.1/video/ddr_controller.vhd
index b7d5087..c288688 100755
--- a/FPGA_Quartus_13.1/video/ddr_controller.vhd
+++ b/FPGA_Quartus_13.1/video/ddr_controller.vhd
@@ -277,7 +277,7 @@ architecture rtl of ddr_ctr is
     signal LINE                         : std_logic;
 
     signal v_basx                       : std_logic_vector(1 downto 0);
-    signal v_basx_cs                    : std_logic;
+    signal v_basx_ta                    : std_logic;
 
     signal v_bash                       : std_logic_vector(7 downto 0);
     signal v_bash_cs                    : std_logic;
@@ -562,26 +562,27 @@ begin
         end if;
     end process;
 
---    i_vbasx : work.flexbus_register
---        generic map
---        (
---            reg_width => 2,
---            match_address => x"ffff8603",
---            match_mask => x"0000ffff",      -- byte register
---            match_fbcs => 1
---        )
---        port map
---        (
---            clk => clk33m,
---            fb_addr => fb_adr,
---            fb_data => fb_ad,
---            fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
---            fb_ta_n => reg_ta,
---            fb_wr_n => nfb_wr,
---            reg_value => v_basx,
---            cs => v_basx_cs
---        );
---
+    i_vbasx : work.flexbus_register
+        generic map
+        (
+            reg_width => 8,
+            match_address => x"ffff8603",
+            num_ignore => 4,
+            match_fbcs => 1
+        )
+        port map
+        (
+            clk => clk33m,
+            fb_addr => fb_adr,
+            fb_ad_in => fb_ad_in,
+            fb_ad_out => fb_ad_out,
+            fb_cs_n => ('1', '1', nfb_cs3, nfb_cs2, nfb_cs1),
+            fb_wr_n => nfb_wr,
+            fb_oe_n => nfb_oe,
+            fb_size => (fb_size1, fb_size0),
+            register_ta => v_basx_ta
+        );
+
 --    i_vbash : work.flexbus_register
 --        generic map
 --        (