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reformat internal signals

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This commit is contained in:
Markus Fröschle
2016-01-13 07:27:57 +00:00
parent 621e2267a7
commit 79a14e2a70
1 changed files with 48 additions and 10 deletions
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58
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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@@ -228,16 +228,54 @@ ARCHITECTURE rtl OF ddr_ctr IS
SIGNAL FIFO_AC_q : std_logic; SIGNAL FIFO_AC_q : std_logic;
SIGNAL FIFO_AC_clk : std_logic; SIGNAL FIFO_AC_clk : std_logic;
SIGNAL FIFO_AC_d : std_logic; SIGNAL FIFO_AC_d : std_logic;
SIGNAL FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, SIGNAL FIFO_AC : std_logic;
BLITTER_AC_clk, BLITTER_AC_d, BLITTER_AC, BLITTER_REQ_q, SIGNAL FIFO_REQ_q : std_logic;
BLITTER_REQ_clk, BLITTER_REQ_d, BLITTER_REQ, BUS_CYC_END, BUS_CYC_q, SIGNAL FIFO_REQ_clk : std_logic;
BUS_CYC_clk, BUS_CYC_d, BUS_CYC, CPU_AC_q, CPU_AC_clk, CPU_AC_d, SIGNAL FIFO_REQ_d : std_logic;
CPU_AC, CPU_REQ_q, CPU_REQ_clk, CPU_REQ_d, CPU_REQ, CPU_SIG, SIGNAL FIFO_REQ : std_logic;
SR_DDRWR_D_SEL_q, SR_DDRWR_D_SEL_clk, SR_DDRWR_D_SEL_d, SR_DDR_WR_q, SIGNAL BLITTER_AC_q : std_logic;
SR_DDR_WR_clk, SR_DDR_WR_d, DDR_CONFIG, DDR_CS_q, DDR_CS_ena, SIGNAL BLITTER_AC_clk : std_logic;
DDR_CS_clk, DDR_CS_d, DDR_CS, DDR_SEL, CPU_DDR_SYNC_q, SIGNAL BLITTER_AC_d : std_logic;
CPU_DDR_SYNC_clk, CPU_DDR_SYNC_d, CPU_DDR_SYNC, VWE, VRAS, VCAS, LINE: SIGNAL BLITTER_AC : std_logic;
std_logic; SIGNAL BLITTER_REQ_q : std_logic;
SIGNAL BLITTER_REQ_clk : std_logic;
SIGNAL BLITTER_REQ_d : std_logic;
SIGNAL BLITTER_REQ : std_logic;
SIGNAL BUS_CYC_END : std_logic;
SIGNAL BUS_CYC_q : std_logic;
SIGNAL BUS_CYC_clk : std_logic;
SIGNAL BUS_CYC_d : std_logic;
SIGNAL BUS_CYC : std_logic;
SIGNAL CPU_AC_q : std_logic;
SIGNAL CPU_AC_clk : std_logic;
SIGNAL CPU_AC_d : std_logic;
SIGNAL CPU_AC : std_logic;
SIGNAL CPU_REQ_q : std_logic;
SIGNAL CPU_REQ_clk : std_logic;
SIGNAL CPU_REQ_d : std_logic;
SIGNAL CPU_REQ : std_logic;
SIGNAL CPU_SIG : std_logic;
SIGNAL SR_DDRWR_D_SEL_q : std_logic;
SIGNAL SR_DDRWR_D_SEL_clk : std_logic;
SIGNAL SR_DDRWR_D_SEL_d : std_logic;
SIGNAL SR_DDR_WR_q : std_logic;
SIGNAL SR_DDR_WR_clk : std_logic;
SIGNAL SR_DDR_WR_d : std_logic;
SIGNAL DDR_CONFIG : std_logic;
SIGNAL DDR_CS_q : std_logic;
SIGNAL DDR_CS_ena : std_logic;
SIGNAL DDR_CS_clk : std_logic;
SIGNAL DDR_CS_d : std_logic;
SIGNAL DDR_CS : std_logic;
SIGNAL DDR_SEL : std_logic;
SIGNAL CPU_DDR_SYNC_q : std_logic;
SIGNAL CPU_DDR_SYNC_clk : std_logic;
SIGNAL CPU_DDR_SYNC_d : std_logic;
SIGNAL CPU_DDR_SYNC : std_logic;
SIGNAL VWE : std_logic;
SIGNAL VRAS : std_logic;
SIGNAL VCAS : std_logic;
SIGNAL LINE : std_logic;
-- Sub Module Interface Section -- Sub Module Interface Section