diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
index 74699d5..52c8703 100755
--- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
+++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
@@ -394,9 +394,12 @@ ARCHITECTURE rtl OF interrupt_handler IS
 	 UPDATE_ON_2, UPDATE_ON_1, u3_enabledt, u2_enabledt, u1_enabledt,
 	 u0_enabledt, vcc, gnd, UPDATE_ON, INC_JAHR, INC_MONAT, SOMMERZEIT,
 	 WINTERZEIT, INC_TAG, INC_STD, INC_MIN, INC_SEC, UHR_DS, UHR_AS,
-	 PSEUDO_BUS_ERROR, ACP_CONF_CS, INT_ENA_CS, INT_CLEAR_CS, INT_LATCH_CS,
+	 PSEUDO_BUS_ERROR, ACP_CONF_CS,
 	 INT_CTR_CS: std_logic;
-
+    signal INT_ENA_CS   : std_logic := '0';
+    signal INT_CLEAR_CS : std_logic := '0';
+    signal INT_LATCH_CS : std_logic := '0';
+    
     FUNCTION to_std_logic(X: IN boolean) RETURN std_logic IS
         VARIABLE ret : std_logic;
     BEGIN
@@ -5096,7 +5099,7 @@ BEGIN
    INT_CTR0_clk_ctrl <= MAIN_CLK;
 
 --  $10000/4
-   INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4000" else '0';
+   INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0';
    INT_CTR_d <= FB_AD;
    INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR);
    INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR);
@@ -5108,7 +5111,7 @@ BEGIN
    INT_ENA0_clrn_ctrl <= nRSTO;
 
 --  $10004/4
-    int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4001";
+    int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4001";
     
     -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
     -- "00000000000100000000000001");
@@ -5122,7 +5125,7 @@ BEGIN
    INT_CLEAR0_clk_ctrl <= MAIN_CLK;
 
 --  $10008/4
-    int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4002" else '0';
+    int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0';
     -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010");
    INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8)
 	 and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8);
@@ -5136,7 +5139,7 @@ BEGIN
 --  INTERRUPT LATCH REGISTER READ ONLY
 --  $1000C/4
 
-    int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4003";
+    int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4003";
     -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
 	--  "00000000000100000000000011");
 
diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd
index f99242b..958dbde 100644
--- a/FPGA_Quartus_13.1/Video/video.vhd
+++ b/FPGA_Quartus_13.1/Video/video.vhd
@@ -794,7 +794,7 @@ BEGIN
         );
     
     VDOUT_OE <= DDR_WR OR SR_DDR_WR;
-    video_ta <= blitter_ta or video_mod_ta or video_ddr_ta;
+    video_ta <= blitter_ta /* or video_mod_ta */ or video_ddr_ta;
     
     inst4 : entity work.lpm_ff1
         PORT MAP
diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
index 1a1993d..ade9e44 100755
--- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
+++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
@@ -1512,9 +1512,9 @@ begin
     VSYNC_I0_ena_ctrl <= LAST_q;
 
     --  3 zeilen vsync length
-    --  runterzählen bis 0
+    --  runterzählen bis 0
     VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else
-                 std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else
+                 std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else
                  (others => '0');
                  
     -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or