Firebee/FPGA_Config
1
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fix number of bits to compare

Browse Source
This commit is contained in:
Markus Fröschle
2016-04-26 19:58:21 +00:00
parent 1a972f2c64
commit 6cf7000199
1 changed files with 6 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -570,20 +570,8 @@ begin
END PROCESS; END PROCESS;
VIDEO_RECONFIG <= VIDEO_RECONFIG_q; VIDEO_RECONFIG <= VIDEO_RECONFIG_q;
PROCESS (main_clk)
BEGIN
IF rising_edge(main_clk) THEN
VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
END IF;
END PROCESS;
VR_WR <= VR_WR_q; VR_WR <= VR_WR_q;
PROCESS (main_clk)
BEGIN
IF rising_edge(main_clk) THEN
VR_WR_q <= VR_WR_d;
END IF;
END PROCESS;
CLR_FIFO <= CLR_FIFO_q; CLR_FIFO <= CLR_FIFO_q;
PROCESS (pixel_clk_i) PROCESS (pixel_clk_i)
@@ -607,6 +595,10 @@ begin
PROCESS (main_clk) PROCESS (main_clk)
BEGIN BEGIN
IF rising_edge(main_clk) THEN IF rising_edge(main_clk) THEN
VR_WR_q <= VR_WR_d;
VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
CLK17M_q <= CLK17M_d; CLK17M_q <= CLK17M_d;
IF VR_DOUT0_ena_ctrl = '1' THEN IF VR_DOUT0_ena_ctrl = '1' THEN
@@ -1508,8 +1500,8 @@ begin
-- 3 zeilen vsync length -- 3 zeilen vsync length
-- runterzählen bis 0 -- runterzählen bis 0
VSYNC_I_d <= x"3" when VSYNC_START_q = '1' else VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else
std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= '0' else std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else
(others => '0'); (others => '0');
-- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or