Firebee/FPGA_Config
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hold time fix test

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This commit is contained in:
Markus Fröschle
2016-01-18 18:15:02 +00:00
parent e623e668c2
commit 652dd1c124
3 changed files with 765 additions and 748 deletions
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9
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
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@@ -449,9 +449,18 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
-- try if an aditional FF will help hold timing
PROCESS
BEGIN
WAIT UNTIL rising_edge(main_clk);
BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
END PROCESS;
-- BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
-- BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
-- BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN
IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN

12
FPGA_Quartus_13.1/firebee_groups.sdc
View File

@@ -91,6 +91,7 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
derive_pll_clocks derive_pll_clocks
# two (video) clocks created by logic
create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q
create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] i_video|i_video_mod_mux_clutctr|CLK13M_q create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] i_video|i_video_mod_mux_clutctr|CLK13M_q
@@ -101,6 +102,13 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut
# clock of i_video_clk_pll # clock of i_video_clk_pll
# #
# virtual clocks for i/o constraints
create_clock -name virt_main_clk -period 30.303 -waveform { 0.000 15.151 }
create_clock -name virt_ddr_clk0 -period 7.575 -waveform { 0.666 4.456 }
create_clock -name virt_ddr_clk1 -period 7.575 -waveform { 0.0 3.788 }
create_clock -name virt_ddr_clk2 -period 7.575 -waveform { 0.5 4.288 }
create_clock -name virt_ddr_clk3 -period 7.575 -waveform { 0.291 4.080 }
#************************************************************** #**************************************************************
# Set Clock Latency # Set Clock Latency
@@ -112,8 +120,8 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut
# Set Clock Uncertainty # Set Clock Uncertainty
#************************************************************** #**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5 # set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5 # set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5
derive_clock_uncertainty derive_clock_uncertainty