diff --git a/FPGA_by_Fredi/Coldari1.qsf b/FPGA_by_Fredi/Coldari1.qsf deleted file mode 100644 index da581cf..0000000 --- a/FPGA_by_Fredi/Coldari1.qsf +++ /dev/null @@ -1,44 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.1 Build 222 10/21/2009 SJ Web Edition -# Date created = 12:11:46 March 06, 2010 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Coldari1_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Stratix II" -set_global_assignment -name DEVICE AUTO -set_global_assignment -name TOP_LEVEL_ENTITY Coldari1 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46 MARCH 06, 2010" -set_global_assignment -name LAST_QUARTUS_VERSION 9.1 \ No newline at end of file diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak deleted file mode 100644 index 0ade395..0000000 --- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak +++ /dev/null @@ -1,617 +0,0 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_WORD.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN VIDEO_MOD_MUX_CLUTCTR -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - DPZF_CLKENA: OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - CLK17M :DFF; - CLK13M :DFF; - ACP_CLUT_CS :NODE; - ACP_CLUT :NODE; - VIDEO_PLL_CONFIG_CS :NODE; - VR_WR :DFF; - VR_DOUT[8..0] :DFFE; - VR_FRQ[7..0] :DFFE; - VIDEO_PLL_RECONFIG_CS :NODE; - VIDEO_RECONFIG :DFF; - FALCON_CLUT_CS :NODE; - FALCON_CLUT :NODE; - ST_CLUT_CS :NODE; - ST_CLUT :NODE; - FB_B[3..0] :NODE; - FB_16B[1..0] :NODE; - ST_SHIFT_MODE[2..0] :DFFE; - ST_SHIFT_MODE_CS :NODE; - FALCON_SHIFT_MODE[10..0] :DFFE; - FALCON_SHIFT_MODE_CS :NODE; - CLUT_MUX_ADR[3..0] :DFF; - CLUT_MUX_AV[1..0][3..0] :DFF; - ACP_VCTR_CS :NODE; - ACP_VCTR[31..0] :DFFE; - CCR_CS :NODE; - CCR[23..0] :DFFE; - ACP_VIDEO_ON :NODE; - SYS_CTR[6..0] :DFFE; - SYS_CTR_CS :NODE; - VDL_LOF[15..0] :DFFE; - VDL_LOF_CS :NODE; - VDL_LWD[15..0] :DFFE; - VDL_LWD_CS :NODE; --- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT - HSYNC :DFF; - HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK - HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT - VSYNC :DFF; - VSYNC_I[2..0] :DFF; - nBLANK :DFF; - DISP_ON :DFF; - DPO_ZL :DFF; - DPO_ON :DFF; - DPO_OFF :DFF; - VDTRON :DFF; - VDO_ZL :DFF; - VDO_ON :DFF; - VDO_OFF :DFF; - VHCNT[12..0] :DFF; - SUB_PIXEL_CNT[6..0] :DFFE; - VVCNT[12..0] :DFFE; - VERZ[2..0][9..0] :DFF; - RAND[6..0] :DFF; - RAND_ON :NODE; - FIFO_RDE :DFF; - CLR_FIFO :DFFE; - START_ZEILE :DFFE; - SYNC_PIX :DFF; - SYNC_PIX1 :DFF; - SYNC_PIX2 :DFF; - CCSEL[2..0] :DFF; - COLOR16 :NODE; - COLOR24 :NODE; -- IST ABER 32BIT BREIT - TE :NODE; --- HORIZONTAL - RAND_LINKS[12..0] :NODE; - HDIS_START[12..0] :NODE; - STARTP[12..0] :NODE; - HDIS_END[12..0] :NODE; - RAND_RECHTS[12..0] :NODE; - MULF[12..0] :NODE; - HS_START[12..0] :NODE; - H_TOTAL[12..0] :NODE; - HDIS_LEN[12..0] :NODE; - WPL[15..0] :NODE; - VDL_HHT[12..0] :DFFE; - VDL_HHT_CS :NODE; - VDL_HBE[12..0] :DFFE; - VDL_HBE_CS :NODE; - VDL_HDB[12..0] :DFFE; - VDL_HDB_CS :NODE; - VDL_HDE[12..0] :DFFE; - VDL_HDE_CS :NODE; - VDL_HBB[12..0] :DFFE; - VDL_HBB_CS :NODE; - VDL_HSS[12..0] :DFFE; - VDL_HSS_CS :NODE; --- VERTIKAL - RAND_OBEN[12..0] :NODE; - VDIS_START[12..0] :NODE; - VDIS_END[12..0] :NODE; - RAND_UNTEN[12..0] :NODE; - VS_START[12..0] :NODE; - V_TOTAL[12..0] :NODE; - FALCON_VIDEO :NODE; - ST_VIDEO :NODE; - INTER_ZEI :DFF; - DOP_FIFO_CLR :DFF; - - VIDEL_CS :NODE; - VDL_VBE[12..0] :DFFE; - VDL_VBE_CS :NODE; - VDL_VDB[12..0] :DFFE; - VDL_VDB_CS :NODE; - VDL_VDE[12..0] :DFFE; - VDL_VDE_CS :NODE; - VDL_VBB[12..0] :DFFE; - VDL_VBB_CS :NODE; - VDL_VSS[12..0] :DFFE; - VDL_VSS_CS :NODE; - VDL_VFT[12..0] :DFFE; - VDL_VFT_CS :NODE; - VDL_VCT[12..0] :DFFE; - VDL_VCT_CS :NODE; - VDL_VMD[3..0] :DFFE; - VDL_VMD_CS :NODE; - VDL_BPP_CS :NODE; - VDL_PH_CS :NODE; - VDL_PV_CS :NODE; - -BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- VIDEL CS - VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82"; -- FFF'F8200-FFF'F82FF --- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 - ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; - ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; - CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 - FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD - FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD - FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 - ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; - ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE - ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 - ST_SHIFT_MODE[] = FB_AD[26..24]; - ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE - FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 - FALCON_SHIFT_MODE[] = FB_AD[26..16]; - FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; - FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR4 = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR8 = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN - ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $F000'0400 - ACP_VCTR[31..8] = FB_AD[31..8]; - ACP_VCTR[5..0] = FB_AD[5..0]; - ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; - ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; - ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; - ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; - ACP_VIDEO_ON = ACP_VCTR0; - nPD_VGA = ACP_VCTR1; --- VIDEO PLL CONFIG - VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY - VR_WR.CLK = MAIN_CLK; - VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; - VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; - VR_DOUT[].CLK = MAIN_CLK; - VR_DOUT[].ENA = !VR_BUSY; - VR_DOUT[] = VR_D[]; - VR_FRQ[].CLK = MAIN_CLK; - VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; - VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG - VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $F000'0800 - VIDEO_RECONFIG.CLK = MAIN_CLK; - VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN - COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; - ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR; - FALCON_VIDEO = ACP_VCTR7; - ST_VIDEO = ACP_VCTR6 & !ACP_VCTR7; - FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; - ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !COLOR1; - CCSEL[].CLK = PIXEL_CLK; - CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION - # B"001" & FALCON_CLUT - # B"100" & ACP_CLUT - # B"101" & COLOR16 - # B"110" & COLOR24 - # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE - CCR[].CLK = MAIN_CLK; - CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $F004'0404/4 - CCR[] = FB_AD[23..0]; - CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; - CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; - CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR - SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $FFFF'8006 - SYS_CTR[].CLK = MAIN_CLK; - SYS_CTR[6..0] = FB_AD[22..16]; - SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; - BLITTER_ON = SYS_CTR3; ---VDL_LOF - VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $F820E/2 - VDL_LOF[].CLK = MAIN_CLK; - VDL_LOF[] = FB_AD[31..16]; - VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; - VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD - VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $F8210/2 - VDL_LWD[].CLK = MAIN_CLK; - VDL_LWD[] = FB_AD[31..16]; - VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; - VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- DATEN AUFLÖSUNG - VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109"; -- $F8212: BITS PER PIXEL - VDL_PH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10A"; -- $F8214: BREITE IN PIXE - VDL_PV_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C10B"; -- $F8216: BREITE IN PIXE --- HORIZONTAL --- VDL_HHT - VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 - VDL_HHT[].CLK = MAIN_CLK; - VDL_HHT[] = FB_AD[28..16]; - VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; - VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE - VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 - VDL_HBE[].CLK = MAIN_CLK; - VDL_HBE[] = FB_AD[28..16]; - VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; - VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB - VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 - VDL_HDB[].CLK = MAIN_CLK; - VDL_HDB[] = FB_AD[28..16]; - VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; - VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE - VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 - VDL_HDE[].CLK = MAIN_CLK; - VDL_HDE[] = FB_AD[28..16]; - VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; - VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB - VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 - VDL_HBB[].CLK = MAIN_CLK; - VDL_HBB[] = FB_AD[28..16]; - VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; - VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS - VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 - VDL_HSS[].CLK = MAIN_CLK; - VDL_HSS[] = FB_AD[28..16]; - VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; - VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE - VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 - VDL_VBE[].CLK = MAIN_CLK; - VDL_VBE[] = FB_AD[28..16]; - VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; - VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB - VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 - VDL_VDB[].CLK = MAIN_CLK; - VDL_VDB[] = FB_AD[28..16]; - VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; - VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE - VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 - VDL_VDE[].CLK = MAIN_CLK; - VDL_VDE[] = FB_AD[28..16]; - VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; - VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB - VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 - VDL_VBB[].CLK = MAIN_CLK; - VDL_VBB[] = FB_AD[28..16]; - VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; - VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS - VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 - VDL_VSS[].CLK = MAIN_CLK; - VDL_VSS[] = FB_AD[28..16]; - VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; - VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT - VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 - VDL_VFT[].CLK = MAIN_CLK; - VDL_VFT[] = FB_AD[28..16]; - VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; - VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT - VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 - VDL_VCT[].CLK = MAIN_CLK; - VDL_VCT[] = FB_AD[28..16]; - VDL_VCT[12..8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; - VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD - VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 - VDL_VMD[].CLK = MAIN_CLK; - VDL_VMD[] = FB_AD[19..16]; - VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT - FB_AD[31..16] = lpm_bustri_WORD( - ST_SHIFT_MODE_CS & (B"00000",ST_SHIFT_MODE[],H"FF") - # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) - # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0]) - # VDL_LOF_CS & VDL_LOF[] - # VDL_LWD_CS & WPL[] - # VDL_BPP_CS & (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1)) - # VDL_PH_CS & (0,HDIS_LEN[]) - # VDL_PV_CS & (0,(VDIS_END[] - VDIS_START[] + 1)) - # VDL_HBE_CS & (0,VDL_HBE[]) - # VDL_HDB_CS & (0,VDL_HDB[]) - # VDL_HDE_CS & (0,VDL_HDE[]) - # VDL_HBB_CS & (0,VDL_HBB[]) - # VDL_HSS_CS & (0,VDL_HSS[]) - # VDL_HHT_CS & (0,VDL_HHT[]) - # VDL_VBE_CS & (0,VDL_VBE[]) - # VDL_VDB_CS & (0,VDL_VDB[]) - # VDL_VDE_CS & (0,VDL_VDE[]) - # VDL_VBB_CS & (0,VDL_VBB[]) - # VDL_VSS_CS & (0,VDL_VSS[]) - # VDL_VFT_CS & (0,VDL_VFT[]) - # VDL_VCT_CS & (0,VDL_VCT[]) - # VDL_VMD_CS & (0,VDL_VMD[]) - # ACP_VCTR_CS & ACP_VCTR[31..16] - # CCR_CS & (0,CCR[23..16]) - # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) - # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") - ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE); - FB_AD[15..0] = lpm_bustri_WORD( - ACP_VCTR_CS & ACP_VCTR[15..0] - # CCR_CS & CCR[15..0] - ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE); - VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS; --- VIDEO AUSGABE SETZEN -------------------------------------------------------------- - CLK17M.CLK = CLK33M; - CLK17M = !CLK17M; - CLK13M.CLK = CLK25M; - CLK13M = !CLK13M; - TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0; -- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480) - PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE - # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE - # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE - # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE - # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ----------------------------------------------------- - HSY_LEN[].CLK = MAIN_CLK; - HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & TE - # 25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & TE - # 38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & VDL_VCT2 & !TE - # 50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE - # 38 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # 50 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # VR_FRQ[] & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = ca. 1us --- MULTIPLIKATIONS FAKTOR ---------------------------------------- - MULF[] = 1 & !ST_VIDEO & ( TE # VDL_VCT0) - # 2 & !ST_VIDEO & !TE & !VDL_VCT0 - # 4 & ST_VIDEO & TE & VDL_VCT0 - # 8 & ST_VIDEO & ( TE & !VDL_VCT0 # !TE & VDL_VCT0) -- WENN ST_VIDEO VORTEILER *8 - # 16 & ST_VIDEO & !TE & !VDL_VCT0; - -- BREITE IN PIXELN ------------------------------------------------ - HDIS_LEN[] = 320 & TE & !ACP_VIDEO_ON - # 640 & !TE & !ACP_VIDEO_ON - # (HDIS_END[] - HDIS_START[] + 1) & ACP_VIDEO_ON; - WPL[] = VDL_LWD[] & !ACP_VIDEO_ON - # (0,HDIS_LEN[12..4]) & COLOR1 & ACP_VIDEO_ON - # (0,HDIS_LEN[12..1]) & COLOR8 & ACP_VIDEO_ON - # (0,HDIS_LEN[]) & COLOR16 & ACP_VIDEO_ON - # (0,HDIS_LEN[],B"0") & COLOR24 & ACP_VIDEO_ON; --- DOPPELZEILENMODUS --------------------------------------------- - INTER_ZEI.CLK = PIXEL_CLK; - INTER_ZEI = VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA; -- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT - DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & (VHCNT[]==HS_START[]); -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER UNGERADEN ZEILEN - DPZF_CLKENA = VVCNT[] > 4; -- FIFO DATASHIFTOUT UNTERBINDEN FÜR DOP.ZEI.FIFO --- TIMING HORIZONTAL - STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[]; -- 2x MITTE SCREEN - RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON - # ((VDL_HBE[] + 1) * MULF[]) & !ACP_VIDEO_ON; -- - HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON - # ((RAND_LINKS[] + 1) & !VDL_VCT0) & !ACP_VIDEO_ON -- MONITOR GANZ RECHTS - # (((0,STARTP[12..1]) + 1) & VDL_VCT0) & !ACP_VIDEO_ON; -- RGB/TV EINMITTEN ZWISCHEN BLANKS - HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON - # (HDIS_START[] + HDIS_LEN[] - 1) & !ACP_VIDEO_ON; -- - RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON - # ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; -- - HS_START[] = VDL_HSS[] & ACP_VIDEO_ON - # ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; -- - H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON - # ((VDL_HHT[] + 2) * 2 * MULF[]) & !ACP_VIDEO_ON; -- --- TIMING VERTICAL - RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON - # ((0,VDL_VBE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON - # (VDL_VBE[] & VDL_VCT0) & !ACP_VIDEO_ON; - VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON - # (((0,VDL_VDB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON - # (( VDL_VDB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON; - VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON - # ((0,VDL_VDE[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON - # ( VDL_VDE[] & VDL_VCT0) & !ACP_VIDEO_ON; - RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON - # (((0,VDL_VBB[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON - # (( VDL_VBB[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON; - VS_START[] = VDL_VSS[] & ACP_VIDEO_ON - # ((0,VDL_VSS[12..1]) & !VDL_VCT0) & !ACP_VIDEO_ON - # ( VDL_VSS[] & VDL_VCT0) & !ACP_VIDEO_ON; - V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON - # (((0,VDL_VFT[12..1]) + 1) & !VDL_VCT0) & !ACP_VIDEO_ON - # ((VDL_VFT[] + 1) & VDL_VCT0) & !ACP_VIDEO_ON; --- ZÄHLER --------------------------------------------------------------------------- - LAST.CLK = PIXEL_CLK; - LAST = VHCNT[]==(H_TOTAL[] - 1); - VHCNT[].CLK = PIXEL_CLK; - VHCNT[] = (VHCNT[] + 1) & !LAST; - VVCNT[].CLK = PIXEL_CLK; - VVCNT[].ENA = LAST; - VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]); --- DISPLAY ON OFF - DPO_ZL.CLK = PIXEL_CLK; - DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]); -- ON OFF - VDTRON.CLK = PIXEL_CLK; - VDTRON = VDTRON & !VDO_OFF - # VDO_ON & VDO_ZL; --- VERZÖGERUNG UND SYNC - HSYNC_START.CLK = PIXEL_CLK; - HSYNC_START = VHCNT[]==HS_START[] - 2; - HSYNC_I[].CLK = PIXEL_CLK; - HSYNC_I[] = HSY_LEN[] & HSYNC_START - # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0; - VSYNC_I[].CLK = PIXEL_CLK; - VSYNC_I[] = VVCNT[12..1]==VS_START[12..1]; -- VSYNC BEI VS_START 2 ZEILEN LANG - VSYNC_I[].CLK = PIXEL_CLK; - VERZ[][].CLK = PIXEL_CLK; - VERZ[][1] = VERZ[][0]; - VERZ[][2] = VERZ[][1]; - VERZ[][3] = VERZ[][2]; - VERZ[][4] = VERZ[][3]; - VERZ[][5] = VERZ[][4]; - VERZ[][6] = VERZ[][5]; - VERZ[][7] = VERZ[][6]; - VERZ[][8] = VERZ[][7]; - VERZ[][9] = VERZ[][8]; - VERZ[0][0] = DISP_ON; - VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0 - # VDL_VCT6 & HSYNC_I[]==0; - VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0 - # VDL_VCT5 & VSYNC_I[]==0; - nBLANK.CLK = PIXEL_CLK; - nBLANK = VERZ[0][8]; - HSYNC.CLK = PIXEL_CLK; - HSYNC = VERZ[1][9]; - VSYNC.CLK = PIXEL_CLK; - VSYNC = VERZ[2][9]; - nSYNC = GND; --- RANDFARBE MACHEN ------------------------------------ - RAND[].CLK = PIXEL_CLK; - RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25; - RAND[1] = RAND[0]; - RAND[2] = RAND[1]; - RAND[3] = RAND[2]; - RAND[4] = RAND[3]; - RAND[5] = RAND[4]; - RAND[6] = RAND[5]; - RAND_ON = RAND[6]; ----------------------------------------------------------- - CLR_FIFO.CLK = PIXEL_CLK; - CLR_FIFO.ENA = LAST; - CLR_FIFO = VVCNT[]==(VDIS_END[] + 2); -- FIFO NACH ENDE ANZEIGE LÖSCHEN (GENUG FRÜH DAMIT ES GEFÜLLT WERDEN KANN BIS ZUR NEUEN ÜBERTRAGUNG) - START_ZEILE.CLK = PIXEL_CLK; - START_ZEILE.ENA = LAST; - START_ZEILE = VVCNT[]==1; -- ZEILE 1 - SYNC_PIX.CLK = PIXEL_CLK; - SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1.CLK = PIXEL_CLK; - SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2.CLK = PIXEL_CLK; - SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SUB_PIXEL_CNT[].CLK = PIXEL_CLK; - SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX; - SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix - FIFO_RDE.CLK = PIXEL_CLK; - FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1 - # SUB_PIXEL_CNT[5..0]==1 & COLOR2 - # SUB_PIXEL_CNT[4..0]==1 & COLOR4 - # SUB_PIXEL_CNT[3..0]==1 & COLOR8 - # SUB_PIXEL_CNT[2..0]==1 & COLOR16 - # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON - # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - - CLUT_MUX_ADR[].CLK = PIXEL_CLK; - CLUT_MUX_AV[][].CLK = PIXEL_CLK; - CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0]; - CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][]; - CLUT_MUX_ADR[] = CLUT_MUX_AV[1][]; -END; diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak deleted file mode 100644 index 3da6541..0000000 --- a/FPGA_by_Fredi/blitter.tdf.bak +++ /dev/null @@ -1,700 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2010 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010) --- Created on Sat Jan 15 11:06:17 2011 -INCLUDE "lpm_bustri_WORD.inc"; -INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC"; -INCLUDE "VIDEO/BLITTER/altsyncram0.INC"; -INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc"; -INCLUDE "VIDEO/BLITTER/lpm_ror128.inc"; - - ---CONSTANT BL_SKEW_LF = 255; - --- Title Statement (optional) -TITLE "Blitter"; - - --- Parameters Statement (optional) - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - - --- Subdesign Section - -SUBDESIGN BLITTER -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ON : INPUT; - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - DDRCLK0 : INPUT; - VDP_IN[63..0] : INPUT; - BLITTER_DACK[4..0] : INPUT; - SR_BLITTER_DACK : INPUT; - BLITTER_RUN : OUTPUT; - BLITTER_INT : OUTPUT; - BLITTER_DOUT[127..0] : OUTPUT; - BLITTER_ADR[31..0] : OUTPUT; - BLITTER_SIG : OUTPUT; - BLITTER_WR : OUTPUT; - BLITTER_TA : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - BYT :NODE; - FB_16B[1..0] :NODE; - BLITTER_CS :NODE; - BL_HRAM_CS :NODE; - DP_RAM_CS :NODE; - BL_HRAM_BE[1..0] :NODE; - BL_HRAM_OUT[15..0] :NODE; - BL_DPRAM_OUT[15..0] :NODE; - BL_SRC_X_INC_CS :NODE; - BL_SRC_X_INC[15..0] :DFFE; - SRC_ADR_INC[31..0] :NODE; - SRC_XINC32[31..0] :NODE; - BL_SRC_Y_INC_CS :NODE; - BL_SRC_Y_INC[15..0] :DFFE; - SRC_YINC32[31..0] :NODE; - BL_ENDMASK1_CS :NODE; - BL_ENDMASK1[15..0] :DFFE; - BL_ENDMASK2_CS :NODE; - BL_ENDMASK2[15..0] :DFFE; - BL_ENDMASK3_CS :NODE; - BL_ENDMASK3[15..0] :DFFE; - BL_ENDMASK0[15..0] :NODE; - BL_ENDMASKF[15..0] :NODE; - BL_ENDMASKL[15..0] :NODE; - BL_ENDMASKR[15..0] :NODE; - BL_SRC_ADRH_CS :NODE; - BL_SRC_ADRL_CS :NODE; - BL_SRC_ADR[31..0] :DFFE; - SRC_OLD[27..0] :DFFE; - SRC_IADRH_CS :NODE; - SRC_IADRL_CS :NODE; - SRC_IADR[31..0] :DFF; - SRC_IADR_CLR :DFF; - SRC_ADR32[31..0] :NODE; - BL_DST_X_INC_CS :NODE; - BL_DST_X_INC[15..0] :DFFE; - DST_ADR_INC[31..0] :NODE; - DST_XINC32[31..0] :NODE; - BL_DST_Y_INC_CS :NODE; - BL_DST_Y_INC[15..0] :DFFE; - DST_YINC32[31..0] :NODE; - BL_DST_ADRH_CS :NODE; - BL_DST_ADRL_CS :NODE; - BL_DST_ADR[31..0] :DFFE; - DST_IADRH_CS :NODE; - DST_IADRL_CS :NODE; - DST_IADR[31..0] :DFF; - DST_IADR_CLR :DFF; - DST_ADR32[31..0] :NODE; - BL_X_CNT_CS :NODE; - BL_X_CNT[15..0] :DFFE; - X_CNT16[15..0] :NODE; - BL_Y_CNT_CS :NODE; - BL_Y_CNT[15..0] :DFFE; - BL_HOP_CS :NODE; - BL_HOP[7..0] :DFFE; - BL_OP[7..0] :DFFE; - BL_LN_CS :NODE; - BL_LN_WR :NODE; - LN7_CLR :NODE; - BL_LN[7..0] :DFFE; - BL_SKEW[7..0] :DFFE; --- barell shifter - DIST_RIGHT[8..0] :NODE; - BS_SKEW[7..0] :NODE; - BL_BSIN[383..0] :NODE; - BL_BSOUT[383..0] :NODE; - SHIFT_DIR :NODE; - BL_SRC_BUF1[127..0] :DFFE; - BL_SRC_BUF2[127..0] :DFFE; - BL_SRC_BUF3[127..0] :DFFE; - BL_DST_BUFRD[127..0] :DFFE; - BL_READ_DST :NODE; -- LATCH SIGNAL DST BUF RD - BL_READ_SRC :NODE; -- LATCH SIGNAL SRC BUF - SRC_READ :NODE; -- FREIGABE LATCH SIGNAL - NOT_DST_READ :NODE; - WREN_B :NODE; -- WR ENA HALFTONE RAM - X_INDEX_CS :NODE; - X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT - X_INDEX_CLR :DFF; -- X INDEX LÖSCHEN CPU WRITE - X_INDEX_CLR_DIR :NODE; -- X INDEX LÖSCHEN STATE MACHINE - DST_X_INC[15..0] :NODE; -- ANZAHL WORTE PRO DURCHLAUF - X_CNT_T[15..0] :NODE; - Y_INDEX_CS :NODE; - Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT - Y_INDEX_CLR :DFF; - LINE_NR[3..0] :NODE; - SDXINC :DFF; -- INC INDEX SPALTE - YIINC :NODE; -- INC INDEX ZEILE - ZAINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH - HOP_OUT[127..0] :NODE; - OP_OUT[127..0] :NODE; - ENDMASK1_SHIFT[7..0] :NODE; - ENDMASK2_SHIFT[7..0] :NODE; - ENDMASK12_IN[143..0] :NODE; - ENDMASK12_OUT[143..0] :NODE; - ENDMASK23_IN[143..0] :NODE; - ENDMASK23_OUT[143..0] :NODE; - ENDMASKM_IN[127..0] :NODE; - ENDMASKM_OUT[127..0] :NODE; - ROR_CNT[8..0] :NODE; - ENDMASK123[127..0] :DFF; - ENDMASKEND[31..0] :NODE; - BLITTER_SIG :DFF; - BLITTER_REQ :NODE; - BL_START :DFF; - BL_NOTRUN :NODE; - --- MAIN STATE MACHINE - BL_SM :MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); - -BEGIN --- BYT UND WORD SELECT 16 BIT - BYT = !FB_SIZE1 & FB_SIZE0; - FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0 - FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT --- BLITTER CS - BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F - BLITTER_TA = BLITTER_CS; --- REGISTER - -- HALFTON RAM - BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00-1F.w - BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0; - BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1; - WREN_B = B"0"; - LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15)); - (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); - DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528"; -- $F8A50.w - -- SRC X INC - BL_SRC_X_INC[].CLK = MAIN_CLK; - BL_SRC_X_INC[15..1] = FB_AD[31..17]; - BL_SRC_X_INC0 = GND; - BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510"); -- $F8A20.w - BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0; - BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1; - SRC_XINC32[15..0] = BL_SRC_X_INC[]; -- ERWEITERN AUF 32 BIT - SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15; -- ERWEITERN AUF 32 BIT - -- SRC Y INC - BL_SRC_Y_INC[].CLK = MAIN_CLK; - BL_SRC_Y_INC[15..1] = FB_AD[31..17]; - BL_SRC_Y_INC0 = GND; - BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511"); -- $F8A22.w - BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0; - BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1; - SRC_YINC32[15..0] = BL_SRC_Y_INC[]; -- ERWEITERN AUF 32 BIT - SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15; -- ERWEITERN AUF 32 BIT - -- SRC ADR HIGH - BL_SRC_ADR[].CLK = MAIN_CLK; - BL_SRC_ADR[31..16] = FB_AD[31..16]; - BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512"); -- $F8A24.w - BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0; - BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1; - -- SRC ADR LOW - BL_SRC_ADR[].CLK = MAIN_CLK; - BL_SRC_ADR[15..1] = FB_AD[31..17]; - BL_SRC_ADR0 = GND; - BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513"); -- $F8A26.w - BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0; - BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1; - SRC_IADR[].CLK = DDRCLK0; - SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520"); -- $F8A40.w - SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521"); -- $F8A42.w - SRC_IADR_CLR.CLK = MAIN_CLK; - SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE - SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR; - SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH - -- ENDMASK 1 - BL_ENDMASK1[].CLK = MAIN_CLK; - BL_ENDMASK1[] = FB_AD[31..16]; - BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514"); -- $F8A28.w - BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0; - BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1; - -- ENDMASK 2 - BL_ENDMASK2[].CLK = MAIN_CLK; - BL_ENDMASK2[] = FB_AD[31..16]; - BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515"); -- $F8A2A.w - BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0; - BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1; - -- ENDMASK 3 - BL_ENDMASK3[].CLK = MAIN_CLK; - BL_ENDMASK3[] = FB_AD[31..16]; - BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516"); -- $F8A2C.w - BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0; - BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1; - -- DST X INC - BL_DST_X_INC[].CLK = MAIN_CLK; - BL_DST_X_INC[15..1] = FB_AD[31..17]; - BL_DST_X_INC0 = GND; - BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517"); -- $F8A2E.w - BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0; - BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1; - DST_XINC32[15..0] = BL_DST_X_INC[]; -- ERWEITERN AUF 32 BIT - DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15; -- ERWEITERN AUF 32 BIT - -- DST Y INC - BL_DST_Y_INC[].CLK = MAIN_CLK; - BL_DST_Y_INC[15..1] = FB_AD[31..17]; - BL_DST_Y_INC0 = GND; - BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518"); -- $F8A30.w - BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0; - BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1; - DST_YINC32[15..0] = BL_DST_Y_INC[]; -- ERWEITERN AUF 32 BIT - DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15; -- ERWEITERN AUF 32 BIT - -- DST ADR HIGH - BL_DST_ADR[].CLK = MAIN_CLK; - BL_DST_ADR[31..16] = FB_AD[31..16]; - BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519"); -- $F8A32.w - BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0; - BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1; - -- DST ADR LOW - BL_DST_ADR[].CLK = MAIN_CLK; - BL_DST_ADR[15..1] = FB_AD[31..17]; - BL_DST_ADR0 = GND; - BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A"); -- $F8A34.w - BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0; - BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1; - DST_IADR[].CLK = DDRCLK0; - DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522"); -- $F8A44.w - DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523"); -- $F8A46.w - DST_IADR_CLR.CLK = MAIN_CLK; - DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE - DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR; - DST_ADR32[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH - -- X COUNT - BL_X_CNT[].CLK = MAIN_CLK; - BL_X_CNT[] = FB_AD[31..16]; - BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B"); -- $F8A36.w - BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0; - BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1; - X_INDEX[].CLK = DDRCLK0; - X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524"); -- $F8A48.w - X_INDEX_CLR.CLK = MAIN_CLK; - X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE - X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR; - X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0)); -- EFFEKTIV geschrieben --- SCHRITTWEITEN BEI PALLETTENMOD - IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 8) THEN - DST_X_INC[] = 1; - X_CNT_T[] = 0; - SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC - DST_ADR_INC[] = DST_XINC32[]; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"0002" THEN - DST_X_INC[] = 8; - X_CNT_T[] = (0,DST_ADR32[3..1]); - SRC_ADR_INC[] = 16; -- SRC X INC - DST_ADR_INC[] = 16; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"FFFE" THEN - DST_X_INC[] = 8; - X_CNT_T[] = 7 - (0,DST_ADR32[3..1]); - SRC_ADR_INC[] = -16; -- SRC X INC - DST_ADR_INC[] = -16; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"0004" THEN - DST_X_INC[] = 4; - X_CNT_T[] = (0,DST_ADR32[3..2]); - SRC_ADR_INC[] = 16; -- SRC X INC - DST_ADR_INC[] = 16; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"FFFC" THEN - DST_X_INC[] = 4; - X_CNT_T[] = 3 - (0,DST_ADR32[3..2]); - SRC_ADR_INC[] = -16; -- SRC X INC - DST_ADR_INC[] = -16; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"0008" THEN - DST_X_INC[] = 2; - X_CNT_T[] = (0,DST_ADR32[3]); - SRC_ADR_INC[] = 16; -- SRC X INC - DST_ADR_INC[] = 16; -- DST X INC - ELSE - IF BL_SRC_X_INC[] == H"FFF8" THEN - DST_X_INC[] = 2; - X_CNT_T[] = 1 - (0,DST_ADR32[3]); - SRC_ADR_INC[] = -16; -- SRC X INC - DST_ADR_INC[] = -16; -- DST X INC - ELSE - DST_X_INC[] = 1; - X_CNT_T[] = 0; - SRC_ADR_INC[] = SRC_XINC32[]; -- SRC X INC - DST_ADR_INC[] = DST_XINC32[]; -- DST X INC - END IF; - END IF; - END IF; - END IF; - END IF; - END IF; - END IF; - -- Y COUNT - BL_Y_CNT[].CLK = MAIN_CLK; - BL_Y_CNT[] = FB_AD[31..16]; - BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w - BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0; - BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1; - Y_INDEX[].CLK = DDRCLK0; - Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w - Y_INDEX_CLR.CLK = MAIN_CLK; - Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE - Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR; - -- HOP LOGIC - BL_HOP[].CLK = MAIN_CLK; - BL_HOP[] = FB_AD[31..24]; - BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w - BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A - -- OP LOGIC - BL_OP[].CLK = MAIN_CLK; - BL_OP[] = FB_AD[23..16]; - BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B - -- LINE NUMBER BYT - BL_LN[].CLK = MAIN_CLK; - BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E"); -- $F8A3C.w - BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C WRITE SIGNAL - BL_LN[6..0] = FB_AD[30..24]; -- HOG UND SMUDGE - BL_LN[6..0].ENA = BL_LN_WR; -- $F8A3C - BL_LN7.ENA = BL_LN_WR # LN7_CLR; -- $F8A3C - BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY - BL_START.CLK = MAIN_CLK; - BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; - -- SKEW BYT - BL_SKEW[].CLK = MAIN_CLK; - BL_SKEW[] = FB_AD[23..16]; - BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D ---- REGISTER OUT - FB_AD[31..16] = lpm_bustri_WORD( - BL_HRAM_CS & BL_DPRAM_OUT[] - # BL_SRC_X_INC_CS & BL_SRC_X_INC[] - # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[] - # BL_SRC_ADRH_CS & SRC_ADR32[31..16] - # BL_SRC_ADRL_CS & SRC_ADR32[15..0] - # BL_ENDMASK1_CS & BL_ENDMASK1[] - # BL_ENDMASK2_CS & BL_ENDMASK2[] - # BL_ENDMASK3_CS & BL_ENDMASK3[] - # BL_DST_X_INC_CS & BL_DST_X_INC[] - # BL_DST_Y_INC_CS & BL_DST_Y_INC[] - # BL_DST_ADRH_CS & DST_ADR32[31..16] - # BL_DST_ADRL_CS & DST_ADR32[15..0] - # BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[]) - # BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[]) - # BL_HOP_CS & (BL_HOP[],BL_OP[]) - # BL_LN_CS & (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[]) - # SRC_IADRH_CS & SRC_IADR[31..16] - # SRC_IADRL_CS & SRC_IADR[15..0] - # DST_IADRH_CS & DST_IADR[31..16] - # DST_IADRL_CS & DST_IADR[15..0] - # X_INDEX_CS & X_INDEX[] - # Y_INDEX_CS & Y_INDEX[] - # DP_RAM_CS & BL_HRAM_OUT[] - ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F --------------------------------------------------------------------------------------- --- SRC BUFFER LADEN - BL_SRC_BUF1[].CLK = DDRCLK0; - BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; - BL_SRC_BUF1[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; - BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]); - BL_SRC_BUF2[].CLK = DDRCLK0; - BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; - BL_SRC_BUF2[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; - BL_SRC_BUF2[] = BL_SRC_BUF1[]; - BL_SRC_BUF3[].CLK = DDRCLK0; - BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; - BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; - BL_SRC_BUF3[] = BL_SRC_BUF2[]; - -- ZUORDNUNG --------------------------------------------------- - IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN - BL_BSIN[127..0] = BL_SRC_BUF3[]; - BL_BSIN[255..128] = BL_SRC_BUF2[]; - BL_BSIN[383..256] = BL_SRC_BUF1[]; - ELSE -- SONST NORMAL BEI VORWÄRTS - BL_BSIN[127..0] = BL_SRC_BUF1[]; - BL_BSIN[255..128] = BL_SRC_BUF2[]; - BL_BSIN[383..256] = BL_SRC_BUF3[]; - END IF; --- DST BUFFER READ - BL_DST_BUFRD[].CLK = DDRCLK0; - BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST; - BL_DST_BUFRD[63..0].ENA = BLITTER_DACK0 & BL_READ_DST; - BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]); --- barell shift ***************************************************************************** --- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT - DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0])); - IF DIST_RIGHT8 THEN - BS_SKEW[] = 0 - DIST_RIGHT[7..0]; -- LPM SHIFT LEFT - SHIFT_DIR = GND; -- DIR = LEFT - else - BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT - SHIFT_DIR = VCC; -- DIR = RIGHT - end if; --- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert! - BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]); -- wir brauchen 128bit --- HOP *************************************************************************************** - CASE BL_HOP[1..0] IS - WHEN H"0" => - -- 12345678901234567890123456789012 - HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - WHEN H"1" => - HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]); - WHEN H"2" => - HOP_OUT[] = BL_BSOUT[255..128]; - WHEN OTHERS => - HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[])); - END CASE; --- OP ***************************************************************************************** - CASE BL_OP[3..0] IS - WHEN H"0" => - OP_OUT[] = H"0"; - SRC_READ = B"0"; - WHEN H"1" => - OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"2" => - OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"3" => - OP_OUT[] = HOP_OUT[]; - SRC_READ = BL_HOP1; - WHEN H"4" => - OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"5" => - OP_OUT[] = BL_DST_BUFRD[]; - SRC_READ = B"0"; - WHEN H"6" => - OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"7" => - OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"8" => - OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"9" => - OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"A" => - OP_OUT[] = !BL_DST_BUFRD[]; - SRC_READ = B"0"; - WHEN H"B" => - OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"C" => - OP_OUT[] = !HOP_OUT[]; - SRC_READ = BL_HOP1; - WHEN H"D" => - OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN H"E" => - OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[]; - SRC_READ = BL_HOP1; - WHEN OTHERS => - -- 12345678901234567890123456789012 - OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - SRC_READ = B"0"; - END CASE; ------------- ENDMASKEN SETZEN ****************************************************************************** - ENDMASK1_SHIFT[3..0] = 0; - ENDMASK2_SHIFT[3..0] = 0; - ENDMASKEND[] = DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[]; - IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV - IF X_INDEX[] == 0 THEN -- ENDE? - ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1])); -- JA ENDMASK 3 SETZEN - ELSE - ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN - END IF; - IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? - ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA -> ENDMASK 1 SETZEN - ELSE - ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN - END IF; - ELSE ------------------------------------------- VORWÄRTS X_INC POSITIV (immer bei memcopy) - IF X_INDEX[] == 0 THEN -- ANFANG? - ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); -- JA -> ENDMASK 1 SETZEN - ELSE - ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN - END IF; - IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? - ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN - ELSE - ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN - END IF; - END IF; --- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts - BL_ENDMASK0[] = 0; - BL_ENDMASKF[] = -1; - BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15; - BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15; - CASE DST_X_INC[] IS - WHEN 8 => -- INC 2 - ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]); - ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]); - ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]); - WHEN 4 => -- INC 4 - ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]); - ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]); - ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]); - WHEN 2 => -- INC 8 - ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]); - ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]); - ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]); - WHEN OTHERS => - ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]); - ENDMASKM_IN[] = (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]); - ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]); - END CASE; - ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN - ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN - ROR_CNT[] = 16 * (0,DST_ADR32[3..1]); - ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]); - ENDMASK123[].CLK = DDRCLK0; - ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[]; - BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[])); - NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"); --- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 - BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA! - BLITTER_ADR[3..0] = H"0"; -- IMMER LINE - BLITTER_SIG.CLK = DDRCLK0; - BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1; --- BLITTER MAIN STATE MACHINE ----------------------------------------------- - BL_SM.CLK = DDRCLK0; - SRC_OLD[].CLK = DDRCLK0; - SRC_OLD[] = SRC_ADR32[31..4]; - SDXINC.CLK = DDRCLK0; - CASE BL_SM IS - WHEN START => ------------------------- START - BL_NOTRUN = VCC; -- BLITTER NOT RUN - IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN -- STARTEN? - BL_SM = NEW_LINE; -- JA START - ELSE - BL_SM = START; -- NICHT STARTEN - END IF; - WHEN NEW_LINE => ----------------------- NEU LINIE - X_INDEX_CLR_DIR = VCC; -- JA -> X INDEX LÖSCHEN FÜR START LINE - IF SRC_READ THEN -- SOURCE READ NÖTIG? - BL_SM = RDSRC3; -- JA - ELSE - BL_SM = RDDST; -- NEIN -> DIREKT ZU READ DEST - END IF; - WHEN RDSRC3 => ------------------------ READ SRC3 - BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15); - BLITTER_REQ = VCC; - BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 - IF BLITTER_DACK0 THEN - BL_SM = RDSRC2; - ELSE - BL_SM = RDSRC3; - END IF; - WHEN RDSRC2 => ------------------------- READ SRC2 - BLITTER_ADR[31..4] = SRC_ADR32[31..4]; - BLITTER_REQ = VCC; - BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 - IF BLITTER_DACK0 THEN - BL_SM = RDSRC1; - ELSE - BL_SM = RDSRC2; - END IF; - WHEN RDSRC1 => ------------------------ READ SRC1 - BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15); - BLITTER_REQ = VCC; - BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 - SRC_OLD[].ENA = VCC; - IF BLITTER_DACK0 THEN - BL_SM = RDDST; - ELSE - BL_SM = RDSRC1; - END IF; - WHEN RDDST => ------------------------ READ DEST - BLITTER_ADR[31..4] = DST_ADR32[31..4]; - IF NOT_DST_READ THEN - BL_SM = WRDSTW; - ELSE - BLITTER_REQ = VCC; - BL_READ_DST = VCC; - IF BLITTER_DACK0 THEN - BL_SM = WRDSTW; - ELSE - BL_SM = RDDST; - END IF; - END IF; - WHEN WRDSTW => ------------------------ KURZ WARTEN AUF ERGEBNIS - BLITTER_ADR[31..4] = DST_ADR32[31..4]; - BL_SM = WRDST; - WHEN WRDST => ------------------------- WRITE DEST - BLITTER_ADR[31..4] = DST_ADR32[31..4]; - BLITTER_WR = VCC; - BLITTER_REQ = VCC; - SDXINC = BLITTER_DACK2; -- INCCREMENT SRC, DST, X_INDEX - IF BLITTER_DACK0 THEN - BL_SM = TESTZEILENENDE; - ELSE - BL_SM = WRDST; - END IF; - WHEN TESTZEILENENDE => ----------------- ZEILENDE? - IF X_CNT16[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? - YIINC = VCC; -- JA -> INC Y-INDEX - BL_SM = TESTFERTIG; -- => TEST OB FERTIG - ELSE - IF !SRC_READ THEN -- KEIN SOURCE READ? - BL_SM = RDDST; -- JA => LESEN UNNÖTIG -> - ELSE - IF SRC_ADR32[31..4] == SRC_OLD[] THEN -- ADRESSE IMMER NOCH IN DER LINE? - BL_SM = RDDST; -- DATEN SIND GÜLTIG -> READ DEST - ELSE - BL_SM = RDSRC1; -- SONST NEXT SRC - END IF; - END IF; - END IF; - WHEN TESTFERTIG => --------------------- TEST AUF FERTIG - ZAINC = VCC; -- ZEILENENDE: INC SRC UND DST ADRESSEN - IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE? - BL_SM = FERTIG; -- JA => FERTIG - ELSE - BL_SM = NEW_LINE; -- NEIN => NEXT LINE - END IF; - WHEN FERTIG => -------------------------- FERTIG - BL_NOTRUN = VCC; -- BLITTER NOT RUN - BLITTER_INT = VCC; -- BLITTER INTERRUPT - LN7_CLR = VCC; -- BUSY BIT LÖSCHEN - IF (BL_LN7 == 0) & (BL_START == 0) THEN -- WARTEN BIS GELÖSCHT (SYNC MIT 33MHz) - BL_SM = START; - ELSE - BL_SM = FERTIG; - END IF; - WHEN OTHERS => - BL_SM = FERTIG; - END CASE; -END; - diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary deleted file mode 100644 index f142f9b..0000000 --- a/FPGA_by_Fredi/firebee1.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Thu Jun 22 14:20:25 2017 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Device : EP3C40F484C6 -Timing Models : Final -Total logic elements : 20,227 / 39,600 ( 51 % ) - Total combinational functions : 18,217 / 39,600 ( 46 % ) - Dedicated logic registers : 5,767 / 39,600 ( 15 % ) -Total registers : 5906 -Total pins : 296 / 332 ( 89 % ) -Total virtual pins : 0 -Total memory bits : 355,360 / 1,161,216 ( 31 % ) -Embedded Multiplier 9-bit elements : 20 / 252 ( 8 % ) -Total PLLs : 4 / 4 ( 100 % ) diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary deleted file mode 100644 index 286e23f..0000000 --- a/FPGA_by_Fredi/firebee1.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Jun 22 14:14:13 2017 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Total logic elements : 21,573 - Total combinational functions : 18,134 - Dedicated logic registers : 5,773 -Total registers : 5901 -Total pins : 296 -Total virtual pins : 0 -Total memory bits : 355,360 -Embedded Multiplier 9-bit elements : 20 -Total PLLs : 4 diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary deleted file mode 100644 index 75fecaf..0000000 --- a/FPGA_by_Fredi/firebee1.tan.summary +++ /dev/null @@ -1,276 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tsu -Slack : -10.868 ns -Required Time : 1.000 ns -Actual Time : 11.868 ns -From : FB_SIZE0 -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 9538 - -Type : Worst-case tco -Slack : -96.119 ns -Required Time : 1.000 ns -Actual Time : 97.119 ns -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] -To : FB_AD[16] -From Clock : MAIN_CLK -To Clock : -- -Failed Paths : 8562 - -Type : Worst-case tpd -Slack : -13.155 ns -Required Time : 1.000 ns -Actual Time : 14.155 ns -From : nFB_CS2 -To : FB_AD[27] -From Clock : -- -To Clock : -- -Failed Paths : 550 - -Type : Worst-case th -Slack : -0.274 ns -Required Time : 1.000 ns -Actual Time : 1.274 ns -From : VD[18] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 11 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' -Slack : -92.241 ns -Required Time : 25.00 MHz ( period = 39.999 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF -From Clock : MAIN_CLK -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -Failed Paths : 6009 - -Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : -90.899 ns -Required Time : 96.01 MHz ( period = 10.416 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF -From Clock : MAIN_CLK -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 5954 - -Type : Clock Setup: 'MAIN_CLK' -Slack : -63.646 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : 10.64 MHz ( period = 93.949 ns ) -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF -From Clock : MAIN_CLK -To Clock : MAIN_CLK -Failed Paths : 41189 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : -17.307 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_SRC_ADR[1] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO -From Clock : MAIN_CLK -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 26373 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : -12.626 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_X_CNT[0] -To : Video:Fredi_Aschwanden|BLITTER:BLITTER|SRC_IADR[30] -From Clock : MAIN_CLK -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 22076 - -Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' -Slack : -5.032 ns -Required Time : 16.00 MHz ( period = 62.499 ns ) -Actual Time : N/A -From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -Failed Paths : 2839 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : -3.374 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : FB_ALE -To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 33 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 2.966 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 3.965 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]' -Slack : 13.509 ns -Required Time : 2.00 MHz ( period = 499.999 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_DIR_NS1 -From Clock : MAIN_CLK -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]' -Slack : 26.728 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX -From Clock : MAIN_CLK -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'MAIN_CLK' -Slack : -6.235 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2] -From Clock : MAIN_CLK -To Clock : MAIN_CLK -Failed Paths : 5610 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' -Slack : -0.919 ns -Required Time : 25.00 MHz ( period = 39.999 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -To : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -Failed Paths : 405 - -Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' -Slack : 0.456 ns -Required Time : 16.00 MHz ( period = 62.499 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 -From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]' -Slack : 0.502 ns -Required Time : 2.00 MHz ( period = 499.999 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]' -Slack : 0.502 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : 0.502 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG -To : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : 0.502 ns -Required Time : 96.01 MHz ( period = 10.416 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -To : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 1.815 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : 2.291 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|inst90~_Duplicate_4 -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : 2.612 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ -To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 4.336 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 129149 - --------------------------------------------------------------------------------------- -