Firebee/FPGA_Config
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reformat

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This commit is contained in:
Markus Fröschle
2016-01-16 22:04:05 +00:00
parent 7bf4d912a0
commit 58a69ffc5f
1 changed files with 116 additions and 128 deletions
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40
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
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@@ -795,7 +795,8 @@ BEGIN
END IF;
END PROCESS;
PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn) BEGIN
PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn)
BEGIN
IF INT_LATCH_clrn(0)='0' THEN
INT_LATCH_q(0) <= '0';
ELSIF INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' THEN
@@ -803,64 +804,51 @@ BEGIN
END IF;
END PROCESS;
PROCESS (INT_CLEAR0_clk_ctrl) BEGIN
PROCESS (INT_CLEAR0_clk_ctrl)
BEGIN
IF INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' THEN
INT_CLEAR_q <= INT_CLEAR_d;
END IF;
END PROCESS;
PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN
PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl)
BEGIN
IF INT_ENA0_clrn_ctrl='0' THEN
(INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28),
INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <=
std_logic_vector'("00000000");
INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= std_logic_vector'("00000000");
ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN
IF INT_ENA24_ena_ctrl='1' THEN
(INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28),
INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24))
<= INT_ENA_d(31 DOWNTO 24);
(INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= INT_ENA_d(31 DOWNTO 24);
END IF;
END IF;
END PROCESS;
PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN
IF INT_ENA0_clrn_ctrl='0' THEN
(INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20),
INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <=
std_logic_vector'("00000000");
(INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= std_logic_vector'("00000000");
ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN
IF INT_ENA16_ena_ctrl='1' THEN
(INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20),
INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16))
<= INT_ENA_d(23 DOWNTO 16);
(INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= INT_ENA_d(23 DOWNTO 16);
END IF;
END IF;
END PROCESS;
PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN
IF INT_ENA0_clrn_ctrl='0' THEN
(INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12),
INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <=
std_logic_vector'("00000000");
(INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= std_logic_vector'("00000000");
ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN
IF INT_ENA8_ena_ctrl='1' THEN
(INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12),
INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <=
INT_ENA_d(15 DOWNTO 8);
(INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= INT_ENA_d(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN
IF INT_ENA0_clrn_ctrl='0' THEN
(INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3),
INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <=
std_logic_vector'("00000000");
(INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= std_logic_vector'("00000000");
ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN
IF INT_ENA0_ena_ctrl='1' THEN
(INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4),
INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <=
INT_ENA_d(7 DOWNTO 0);
(INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= INT_ENA_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;