Firebee/FPGA_Config
1
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

renamed many instances to more meaningful names

Browse Source
This commit is contained in:
Markus Fröschle
2015-09-20 08:06:12 +00:00
parent 8ec08da1fd
commit 4f57571130
5 changed files with 16512 additions and 16509 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -1,4 +1,4 @@
TITLE "VIDEO MODUSE UND CLUT CONTROL"; TITLE "VIDEO MODI AND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN -- CREATED BY FREDI ASCHWANDEN
@@ -101,7 +101,7 @@ VARIABLE
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF; HSYNC :DFF;
HSYNC_I[7..0] :DFF; HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF; HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF; VSYNC :DFF;
@@ -191,6 +191,7 @@ VARIABLE
VDL_VCT_CS :NODE; VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE; VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE; VDL_VMD_CS :NODE;
ACP_VCTR6_DUP : NODE;
BEGIN BEGIN
-- BYT SELECT 32 BIT -- BYT SELECT 32 BIT
@@ -254,7 +255,7 @@ BEGIN
ACP_VIDEO_ON = ACP_VCTR0; ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1; nPD_VGA = ACP_VCTR1;
-- ATARI MODUS -- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480 -- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK; ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
@@ -312,7 +313,10 @@ BEGIN
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-- duplicate ACP_VCTR6 according to TimeQuest reccomendations
ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ACP_VCTR6_DUP;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7; FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
@@ -497,7 +501,7 @@ BEGIN
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
-------------------------------------------------------------- --------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK -- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
---------------------------------------------------------------- ----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
@@ -524,7 +528,7 @@ BEGIN
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK; DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
@@ -566,7 +570,7 @@ BEGIN
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER -- Z<>HLER
LAST.CLK = PIXEL_CLK; LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2); LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK; VHCNT[].CLK = PIXEL_CLK;
@@ -577,7 +581,7 @@ BEGIN
-- DISPLAY ON OFF -- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK; DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK; DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK; DPO_OFF.CLK = PIXEL_CLK;
@@ -591,12 +595,12 @@ BEGIN
VDO_OFF.CLK = PIXEL_CLK; VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[]; VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK; VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK; VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL; # VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC -- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK; HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3; HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK; HSYNC_I[].CLK = PIXEL_CLK;
@@ -608,7 +612,7 @@ BEGIN
VSYNC_I[].CLK = PIXEL_CLK; VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0 # (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK; VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0]; VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1]; VERZ[][2] = VERZ[][1];
@@ -622,9 +626,9 @@ BEGIN
VERZ[0][0] = DISP_ON; VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0; VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0 VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE # ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0 VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE # ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK; nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8]; nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK; HSYNC.CLK = PIXEL_CLK;
@@ -645,16 +649,16 @@ BEGIN
---------------------------------------------------------- ----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK; CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST; CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK; START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST; START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1 START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK; SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK; SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK; SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK; SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX; SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
@@ -665,7 +669,7 @@ BEGIN
# SUB_PIXEL_CNT[3..0]==1 & COLOR8 # SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16 # SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK; CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK; CLUT_MUX_AV[][].CLK = PIXEL_CLK;

9042
FPGA_Quartus_13.1/Video/Video.bdf
View File

File diff suppressed because it is too large Load Diff

4552
FPGA_Quartus_13.1/firebee1.bdf
View File

File diff suppressed because it is too large Load Diff

5
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -374,9 +374,9 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
@@ -740,7 +740,6 @@ set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
FPGA_Quartus_13.1/firebee1.qws
View File

Binary file not shown.