diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd
index dd18799..0189d67 100755
--- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd
+++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd
@@ -278,6 +278,7 @@ ARCHITECTURE rtl OF ddr_ctr IS
     SIGNAL LINE                         : std_logic;
     SIGNAL v_bash                       : std_logic_vector(7 DOWNTO 0);
     SIGNAL v_bash_cs                    : std_logic;
+    SIGNAL reg_ta                       : std_logic;
 -- Sub Module Interface Section
 
 
@@ -588,8 +589,9 @@ BEGIN
             fb_addr => fb_adr,
             fb_data => fb_ad,
             fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
+            fb_ta_n => reg_ta,
             fb_wr_n => nfb_wr,
-            data => v_bash,
+            reg_value => v_bash,
             cs => v_bash_cs
         );
         
diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd
index 72d3dc0..0fdf3c8 100644
--- a/FPGA_Quartus_13.1/flexbus_register.vhd
+++ b/FPGA_Quartus_13.1/flexbus_register.vhd
@@ -14,10 +14,11 @@ ENTITY flexbus_register IS
     (
         clk             : IN std_logic;
         fb_addr         : IN std_logic_vector(31 DOWNTO 0);
-        fb_data         : IN std_logic_vector(31 DOWNTO 0);
+        fb_data         : INOUT std_logic_vector(31 DOWNTO 0);
         fb_cs           : IN std_logic_vector(5 DOWNTO 1);
         fb_wr_n         : IN std_logic;
-        data            : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
+        fb_ta_n         : OUT std_logic;
+        reg_value       : INOUT std_logic_vector(reg_width - 1 DOWNTO 0);
         cs              : OUT std_logic := '0'
     );
 END ENTITY flexbus_register;
@@ -25,7 +26,6 @@ END ENTITY flexbus_register;
 ARCHITECTURE rtl OF flexbus_register IS
     SIGNAL fbcs_match       : std_logic;
     SIGNAL address_match    : std_logic;
-    SIGNAL reg_value        : std_logic_vector(reg_width - 1 DOWNTO 0) := (OTHERS => '0');
 BEGIN
     fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0';
     address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0';
@@ -38,9 +38,12 @@ BEGIN
                 IF fb_wr_n = '0' THEN   -- write access
                     reg_value <= fb_data(reg_width - 1 DOWNTO 0);
                 ELSE                    -- read access
-                    data <= reg_value;
+                    fb_data(reg_width - 1 DOWNTO 0) <= reg_value;
+                    fb_ta_n <= '0';
                 END IF;
             ELSE
+                fb_data <= (OTHERS => 'Z');
+                fb_ta_n <= 'Z';
                 cs <= '0';
             END IF;
         END IF;