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translate interrupt_controller to vhd

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This commit is contained in:
Markus Fröschle
2016-01-11 16:11:04 +00:00
parent 98a362dc90
commit 476825a3ba
6 changed files with 7740 additions and 1612 deletions
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6381
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd Executable file
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File diff suppressed because it is too large Load Diff

1
FPGA_Quartus_13.1/Video/video.vhd
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@@ -82,6 +82,7 @@ COMPONENT mux41_0
D1 : IN STD_LOGIC; D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC); Q : OUT STD_LOGIC);
END COMPONENT; END COMPONENT;
ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;

13
FPGA_Quartus_13.1/firebee1.qsf
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@@ -670,6 +670,12 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
set_global_assignment -name SOURCE_FILE altpll4.cmp
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name VHDL_FILE firebee1.vhd
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/mux41.vhd set_global_assignment -name VHDL_FILE Video/mux41.vhd
set_global_assignment -name VHDL_FILE Video/mux41_5.vhd set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
set_global_assignment -name VHDL_FILE Video/mux41_4.vhd set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
@@ -677,11 +683,6 @@ set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
set_global_assignment -name VHDL_FILE Video/mux41_2.vhd set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
set_global_assignment -name VHDL_FILE Video/mux41_1.vhd set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
set_global_assignment -name VHDL_FILE Video/mux41_0.vhd set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
set_global_assignment -name VHDL_FILE firebee1.vhd
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
set_global_assignment -name AHDL_FILE altpll4.tdf
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
@@ -786,7 +787,6 @@ set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE DSP/DSP.vhd
set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
@@ -847,7 +847,6 @@ set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip

12
FPGA_Quartus_13.1/firebee1.sdc
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@@ -118,17 +118,21 @@ derive_clock_uncertainty
# Set Input Delay # Set Input Delay
#************************************************************** #**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#************************************************************** #**************************************************************
# Set Output Delay # Set Output Delay
#************************************************************** #**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}]
#************************************************************** #**************************************************************
# Set Clock Groups # Set Clock Groups

711
FPGA_Quartus_13.1/firebee1.vhd
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@@ -1,6 +1,9 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.altera_primitives_components.all;
LIBRARY work; LIBRARY work;
ENTITY firebee1 IS ENTITY firebee1 IS
@@ -145,407 +148,131 @@ ENTITY firebee1 IS
END firebee1; END firebee1;
ARCHITECTURE rtl OF firebee1 IS ARCHITECTURE rtl OF firebee1 IS
SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0);
SIGNAL clk25m_i : std_logic;
SIGNAL CLK2M : std_logic;
SIGNAL CLK2M4576 : std_logic;
SIGNAL CLK33M : std_logic;
SIGNAL CLK48M : std_logic;
SIGNAL CLK500k : std_logic;
SIGNAL CLK_VIDEO : std_logic;
SIGNAL DDR_SYNC_66M : std_logic;
SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0);
SIGNAL DMA_DRQ : std_logic;
SIGNAL DSP_INT : std_logic;
SIGNAL DSP_TA : std_logic;
SIGNAL FALCON_IO_TA : std_logic;
SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0);
SIGNAL FDC_CLK : std_logic;
SIGNAL HSYNC : std_logic;
SIGNAL INT_HANDLER_TA : std_logic;
SIGNAL LP_DIR : std_logic;
SIGNAL MIDI_IN : std_logic;
SIGNAL MOT_ON : std_logic;
SIGNAL nBLANK : std_logic;
SIGNAL nDREQ0 : std_logic;
SIGNAL nMFP_INT : std_logic;
SIGNAL nRSTO : std_logic;
SIGNAL PIXEL_CLK : std_logic;
SIGNAL SD_CDM_D1 : std_logic;
SIGNAL STEP : std_logic;
SIGNAL STEP_DIR : std_logic;
SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0);
SIGNAL VIDEO_RECONFIG : std_logic;
SIGNAL Video_TA : std_logic;
SIGNAL VR_BUSY : std_logic;
SIGNAL VR_D : std_logic_vector(8 DOWNTO 0);
SIGNAL VR_RD : std_logic;
SIGNAL VR_WR : std_logic;
SIGNAL VSYNC : std_logic;
SIGNAL WR_DATA : std_logic;
SIGNAL WR_GATE : std_logic;
SIGNAL scandataout : std_logic;
SIGNAL scandone : std_logic;
SIGNAL reset : std_logic;
SIGNAL pll_reset : std_logic;
SIGNAL scanclk : std_logic;
SIGNAL scandata : std_logic;
SIGNAL scan_clkena : std_logic;
SIGNAL config_update : std_logic;
SIGNAL pll3_locked : std_logic;
SIGNAL pll1_locked : std_logic;
SIGNAL nSRCS_i : std_logic;
SIGNAL nFB_WR_i : std_logic;
SIGNAL nIDE_RD_i : std_logic;
SIGNAL nIDE_WR_i : std_logic;
COMPONENT altpll3 COMPONENT altpll_reconfig1
PORT PORT
( (
inclk0 : IN std_logic; clock : IN STD_LOGIC ;
c0 : OUT std_logic; counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
c1 : OUT std_logic; counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c2 : OUT std_logic; data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
c3 : OUT std_logic; pll_areset_in : IN STD_LOGIC := '0';
locked : OUT std_logic pll_scandataout : IN STD_LOGIC ;
pll_scandone : IN STD_LOGIC ;
read_param : IN STD_LOGIC ;
reconfig : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
write_param : IN STD_LOGIC ;
busy : OUT STD_LOGIC ;
data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset : OUT STD_LOGIC ;
pll_configupdate : OUT STD_LOGIC ;
pll_scanclk : OUT STD_LOGIC ;
pll_scanclkena : OUT STD_LOGIC ;
pll_scandata : OUT STD_LOGIC
); );
END COMPONENT; END COMPONENT altpll_reconfig1;
COMPONENT altpll2 COMPONENT altpll4
PORT PORT
( (
inclk0 : IN std_logic; areset : IN STD_LOGIC := '0';
c0 : OUT std_logic; configupdate : IN STD_LOGIC := '0';
c1 : OUT std_logic; inclk0 : IN STD_LOGIC := '0';
c2 : OUT std_logic; scanclk : IN STD_LOGIC := '1';
c3 : OUT std_logic; scanclkena : IN STD_LOGIC := '0';
c4 : OUT std_logic scandata : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ;
scandataout : OUT STD_LOGIC ;
scandone : OUT STD_LOGIC
); );
END COMPONENT; END COMPONENT altpll4;
COMPONENT dsp
PORT
(
CLK33M : IN std_logic;
MAIN_CLK : IN std_logic;
nFB_OE : IN std_logic;
nFB_WR : IN std_logic;
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
nFB_BURST : IN std_logic;
nRSTO : IN std_logic;
nFB_CS3 : IN std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
IO : INOUT std_logic_vector(17 DOWNTO 0);
SRD : INOUT std_logic_vector(15 DOWNTO 0);
nSRCS : OUT std_logic;
nSRBLE : OUT std_logic;
nSRBHE : OUT std_logic;
nSRWE : OUT std_logic;
nSROE : OUT std_logic;
DSP_INT : OUT std_logic;
DSP_TA : OUT std_logic
);
END COMPONENT;
COMPONENT falconio_sdcard_ide_cf
PORT
(
CLK33M : IN std_logic;
MAIN_CLK : IN std_logic;
CLK2M : IN std_logic;
CLK500k : IN std_logic;
nFB_CS1 : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
nFB_BURST : IN std_logic;
LP_BUSY : IN std_logic;
nACSI_DRQ : IN std_logic;
nACSI_INT : IN std_logic;
nSCSI_DRQ : IN std_logic;
nSCSI_MSG : IN std_logic;
MIDI_IN : IN std_logic;
RxD : IN std_logic;
CTS : IN std_logic;
RI : IN std_logic;
DCD : IN std_logic;
AMKB_RX : IN std_logic;
PIC_AMKB_RX : IN std_logic;
IDE_RDY : IN std_logic;
IDE_INT : IN std_logic;
WP_CS_CARD : IN std_logic;
nINDEX : IN std_logic;
TRACK00 : IN std_logic;
nRD_DATA : IN std_logic;
nDCHG : IN std_logic;
SD_DATA0 : IN std_logic;
SD_DATA1 : IN std_logic;
SD_DATA2 : IN std_logic;
SD_CARD_DEDECT : IN std_logic;
SD_WP : IN std_logic;
nDACK0 : IN std_logic;
nFB_WR : IN std_logic;
WP_CF_CARD : IN std_logic;
nWP : IN std_logic;
nFB_CS2 : IN std_logic;
nRSTO : IN std_logic;
nSCSI_C_D : IN std_logic;
nSCSI_I_O : IN std_logic;
CLK2M4576 : IN std_logic;
nFB_OE : IN std_logic;
VSYNC : IN std_logic;
HSYNC : IN std_logic;
DSP_INT : IN std_logic;
nBLANK : IN std_logic;
FDC_CLK : IN std_logic;
FB_ALE : IN std_logic;
HD_DD : IN std_logic;
SCSI_PAR : INOUT std_logic;
nSCSI_SEL : INOUT std_logic;
nSCSI_BUSY : INOUT std_logic;
nSCSI_RST : INOUT std_logic;
SD_CD_DATA3 : INOUT std_logic;
SD_CDM_D1 : INOUT std_logic;
ACP_CONF : IN std_logic_vector(31 DOWNTO 24);
ACSI_D : INOUT std_logic_vector(7 DOWNTO 0);
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
LP_D : INOUT std_logic_vector(7 DOWNTO 0);
SCSI_D : INOUT std_logic_vector(7 DOWNTO 0);
nIDE_CS1 : OUT std_logic;
nIDE_CS0 : OUT std_logic;
LP_STR : OUT std_logic;
LP_DIR : OUT std_logic;
nACSI_ACK : OUT std_logic;
nACSI_RESET : OUT std_logic;
nACSI_CS : OUT std_logic;
ACSI_DIR : OUT std_logic;
ACSI_A1 : OUT std_logic;
nSCSI_ACK : OUT std_logic;
nSCSI_ATN : OUT std_logic;
SCSI_DIR : OUT std_logic;
SD_CLK : OUT std_logic;
YM_QA : OUT std_logic;
YM_QC : OUT std_logic;
YM_QB : OUT std_logic;
nSDSEL : OUT std_logic;
STEP : OUT std_logic;
MOT_ON : OUT std_logic;
nRP_LDS : OUT std_logic;
nRP_UDS : OUT std_logic;
nROM4 : OUT std_logic;
nROM3 : OUT std_logic;
nCF_CS1 : OUT std_logic;
nCF_CS0 : OUT std_logic;
nIDE_RD : OUT std_logic;
nIDE_WR : OUT std_logic;
AMKB_TX : OUT std_logic;
IDE_RES : OUT std_logic;
DTR : OUT std_logic;
RTS : OUT std_logic;
TxD : OUT std_logic;
MIDI_OLR : OUT std_logic;
nDREQ0 : OUT std_logic;
DSA_D : OUT std_logic;
nMFP_INT : OUT std_logic;
FALCON_IO_TA : OUT std_logic;
STEP_DIR : OUT std_logic;
WR_DATA : OUT std_logic;
WR_GATE : OUT std_logic;
DMA_DRQ : OUT std_logic;
MIDI_TLR : OUT std_logic
);
END COMPONENT;
COMPONENT interrupt_handler
PORT
(
MAIN_CLK : IN std_logic;
nFB_WR : IN std_logic;
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
PIC_INT : IN std_logic;
E0_INT : IN std_logic;
DVI_INT : IN std_logic;
nPCI_INTA : IN std_logic;
nPCI_INTB : IN std_logic;
nPCI_INTC : IN std_logic;
nPCI_INTD : IN std_logic;
nMFP_INT : IN std_logic;
nFB_OE : IN std_logic;
DSP_INT : IN std_logic;
VSYNC : IN std_logic;
HSYNC : IN std_logic;
DMA_DRQ : IN std_logic;
nRSTO : IN std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
INT_HANDLER_TA : OUT std_logic;
TIN0 : OUT std_logic;
ACP_CONF : OUT std_logic_vector(31 DOWNTO 0);
nIRQ : OUT std_logic_vector(7 DOWNTO 2)
);
END COMPONENT;
COMPONENT altpll1
PORT
(
inclk0 : IN std_logic;
c0 : OUT std_logic;
c1 : OUT std_logic;
c2 : OUT std_logic;
locked : OUT std_logic
);
END COMPONENT;
COMPONENT altpll_reconfig1
PORT
(
reconfig : IN std_logic;
read_param : IN std_logic;
write_param : IN std_logic;
pll_scandataout : IN std_logic;
pll_scandone : IN std_logic;
clock : IN std_logic;
reset : IN std_logic;
pll_areset_in : IN std_logic;
counter_param : IN std_logic_vector(2 DOWNTO 0);
counter_type : IN std_logic_vector(3 DOWNTO 0);
data_in : IN std_logic_vector(8 DOWNTO 0);
busy : OUT std_logic;
pll_scandata : OUT std_logic;
pll_scanclk : OUT std_logic;
pll_scanclkena : OUT std_logic;
pll_configupdate : OUT std_logic;
pll_areset : OUT std_logic;
data_out : OUT std_logic_vector(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT video
PORT
(
MAIN_CLK : IN std_logic;
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
nFB_WR : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
nRSTO : IN std_logic;
nFB_OE : IN std_logic;
FB_ALE : IN std_logic;
DDR_SYNC_66M : IN std_logic;
CLK33M : IN std_logic;
CLK25M : IN std_logic;
CLK_VIDEO : IN std_logic;
VR_BUSY : IN std_logic;
DDRCLK : IN std_logic_vector(3 DOWNTO 0);
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
VD : INOUT std_logic_vector(31 DOWNTO 0);
VDQS : INOUT std_logic_vector(3 DOWNTO 0);
VR_D : IN std_logic_vector(8 DOWNTO 0);
VR_RD : OUT std_logic;
nBLANK : OUT std_logic;
nVWE : OUT std_logic;
nVCAS : OUT std_logic;
nVRAS : OUT std_logic;
nVCS : OUT std_logic;
nPD_VGA : OUT std_logic;
VCKE : OUT std_logic;
VSYNC : OUT std_logic;
HSYNC : OUT std_logic;
nSYNC : OUT std_logic;
VIDEO_TA : OUT std_logic;
PIXEL_CLK : OUT std_logic;
VIDEO_RECONFIG : OUT std_logic;
VR_WR : OUT std_logic;
BA : OUT std_logic_vector(1 DOWNTO 0);
VA : OUT std_logic_vector(12 DOWNTO 0);
VB : OUT std_logic_vector(7 DOWNTO 0);
VDM : OUT std_logic_vector(3 DOWNTO 0);
VG : OUT std_logic_vector(7 DOWNTO 0);
VR : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT altpll4
PORT(inclk0 : IN std_logic;
areset : IN std_logic;
scanclk : IN std_logic;
scandata : IN std_logic;
scanclkena : IN std_logic;
configupdate : IN std_logic;
c0 : OUT std_logic;
scandataout : OUT std_logic;
scandone : OUT std_logic;
locked : OUT std_logic
);
END COMPONENT;
COMPONENT lpm_ff0
PORT(clock : IN std_logic;
enable : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0);
q : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_counter0
PORT(clock : IN std_logic;
q : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT alt_iobuf
PORT(i : IN std_logic;
oe : IN std_logic;
io : INOUT std_logic;
o : OUT std_logic
);
END COMPONENT;
COMPONENT altddio_out3
PORT(datain_h : IN std_logic;
datain_l : IN std_logic;
outclock : IN std_logic;
dataout : OUT std_logic
);
END COMPONENT;
SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0);
SIGNAL CLK25M_ALTERA_SYNTHESIZED : std_logic;
SIGNAL CLK2M : std_logic;
SIGNAL CLK2M4576 : std_logic;
SIGNAL CLK33M : std_logic;
SIGNAL CLK48M : std_logic;
SIGNAL CLK500k : std_logic;
SIGNAL CLK_VIDEO : std_logic;
SIGNAL DDR_SYNC_66M : std_logic;
SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0);
SIGNAL DMA_DRQ : std_logic;
SIGNAL DSP_INT : std_logic;
SIGNAL DSP_TA : std_logic;
SIGNAL FALCON_IO_TA : std_logic;
SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0);
SIGNAL FDC_CLK : std_logic;
SIGNAL HSYNC : std_logic;
SIGNAL INT_HANDLER_TA : std_logic;
SIGNAL LP_DIR : std_logic;
SIGNAL MIDI_IN : std_logic;
SIGNAL MOT_ON : std_logic;
SIGNAL nBLANK : std_logic;
SIGNAL nDREQ0 : std_logic;
SIGNAL nMFP_INT : std_logic;
SIGNAL nRSTO : std_logic;
SIGNAL PIXEL_CLK : std_logic;
SIGNAL SD_CDM_D1 : std_logic;
SIGNAL STEP : std_logic;
SIGNAL STEP_DIR : std_logic;
SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0);
SIGNAL VIDEO_RECONFIG : std_logic;
SIGNAL Video_TA : std_logic;
SIGNAL VR_BUSY : std_logic;
SIGNAL VR_D : std_logic_vector(8 DOWNTO 0);
SIGNAL VR_RD : std_logic;
SIGNAL VR_WR : std_logic;
SIGNAL VSYNC : std_logic;
SIGNAL WR_DATA : std_logic;
SIGNAL WR_GATE : std_logic;
SIGNAL SYNTHESIZED_WIRE_0 : std_logic;
SIGNAL SYNTHESIZED_WIRE_1 : std_logic;
SIGNAL SYNTHESIZED_WIRE_2 : std_logic;
SIGNAL SYNTHESIZED_WIRE_3 : std_logic;
SIGNAL SYNTHESIZED_WIRE_4 : std_logic;
SIGNAL SYNTHESIZED_WIRE_5 : std_logic;
SIGNAL SYNTHESIZED_WIRE_6 : std_logic;
SIGNAL SYNTHESIZED_WIRE_7 : std_logic;
SIGNAL SYNTHESIZED_WIRE_8 : std_logic;
SIGNAL SYNTHESIZED_WIRE_9 : std_logic;
SIGNAL SYNTHESIZED_WIRE_10 : std_logic;
SIGNAL SYNTHESIZED_WIRE_11 : std_logic;
BEGIN BEGIN
nDREQ1 <= nDACK1; nDREQ1 <= nDACK1;
SYNTHESIZED_WIRE_10 <= '0';
SYNTHESIZED_WIRE_11 <= '1';
i_atari_clk_pll : work.altpll3
PORT MAP
i_atari_clk_pll : altpll3 (
PORT MAP(inclk0 => MAIN_CLK, inclk0 => MAIN_CLK,
c0 => CLK25M_ALTERA_SYNTHESIZED, c0 => clk25m_i,
c1 => CLK2M, c1 => CLK2M,
c2 => CLK500k, c2 => CLK500k,
c3 => CLK2M4576, c3 => CLK2M4576,
locked => SYNTHESIZED_WIRE_8); locked => pll3_locked
);
i_ddr_clk_pll : altpll2 i_ddr_clk_pll : work.altpll2
PORT MAP(inclk0 => MAIN_CLK, PORT MAP
(
inclk0 => MAIN_CLK,
c0 => DDRCLK(0), c0 => DDRCLK(0),
c1 => DDRCLK(1), c1 => DDRCLK(1),
c2 => DDRCLK(2), c2 => DDRCLK(2),
c3 => DDRCLK(3), c3 => DDRCLK(3),
c4 => DDR_SYNC_66M); c4 => DDR_SYNC_66M
);
i_dsp : dsp i_dsp : work.dsp
PORT MAP(CLK33M => CLK33M, PORT MAP
(
CLK33M => CLK33M,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
nFB_OE => nFB_OE, nFB_OE => nFB_OE,
nFB_WR => nFB_WR, nFB_WR => nFB_WR,
@@ -560,17 +287,20 @@ PORT MAP(CLK33M => CLK33M,
FB_ADR => FB_ADR, FB_ADR => FB_ADR,
IO => IO, IO => IO,
SRD => SRD, SRD => SRD,
nSRCS => nSRCS, nSRCS => nSRCS_i,
nSRBLE => nSRBLE, nSRBLE => nSRBLE,
nSRBHE => nSRBHE, nSRBHE => nSRBHE,
nSRWE => nSRWE, nSRWE => nSRWE,
nSROE => nSROE, nSROE => nSROE,
DSP_INT => DSP_INT, DSP_INT => DSP_INT,
DSP_TA => DSP_TA); DSP_TA => DSP_TA
);
i_falcioio_sdcard_ide_cf : falconio_sdcard_ide_cf i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf
PORT MAP(CLK33M => CLK33M, PORT MAP
(
CLK33M => CLK33M,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
CLK2M => CLK2M, CLK2M => CLK2M,
CLK500k => CLK500k, CLK500k => CLK500k,
@@ -603,7 +333,7 @@ PORT MAP(CLK33M => CLK33M,
SD_CARD_DEDECT => SD_CARD_DEDECT, SD_CARD_DEDECT => SD_CARD_DEDECT,
SD_WP => SD_WP, SD_WP => SD_WP,
nDACK0 => nDACK0, nDACK0 => nDACK0,
nFB_WR => nFB_WR, nFB_WR => nFB_WR_i,
WP_CF_CARD => WP_CF_CARD, WP_CF_CARD => WP_CF_CARD,
nWP => nWP, nWP => nWP,
nFB_CS2 => nFB_CS2, nFB_CS2 => nFB_CS2,
@@ -656,8 +386,8 @@ PORT MAP(CLK33M => CLK33M,
nROM3 => nROM3, nROM3 => nROM3,
nCF_CS1 => nCF_CS1, nCF_CS1 => nCF_CS1,
nCF_CS0 => nCF_CS0, nCF_CS0 => nCF_CS0,
nIDE_RD => nIDE_RD, nIDE_RD => nIDE_RD_i,
nIDE_WR => nIDE_WR, nIDE_WR => nIDE_WR_i,
AMKB_TX => AMKB_TX, AMKB_TX => AMKB_TX,
IDE_RES => IDE_RES, IDE_RES => IDE_RES,
DTR => DTR, DTR => DTR,
@@ -671,11 +401,14 @@ PORT MAP(CLK33M => CLK33M,
WR_DATA => WR_DATA, WR_DATA => WR_DATA,
WR_GATE => WR_GATE, WR_GATE => WR_GATE,
DMA_DRQ => DMA_DRQ, DMA_DRQ => DMA_DRQ,
MIDI_TLR => MIDI_TLR); MIDI_TLR => MIDI_TLR
);
i_interrupt_handler : interrupt_handler i_interrupt_handler : work.interrupt_handler
PORT MAP(MAIN_CLK => MAIN_CLK, PORT MAP
(
MAIN_CLK => MAIN_CLK,
nFB_WR => nFB_WR, nFB_WR => nFB_WR,
nFB_CS1 => nFB_CS1, nFB_CS1 => nFB_CS1,
nFB_CS2 => nFB_CS2, nFB_CS2 => nFB_CS2,
@@ -700,40 +433,49 @@ PORT MAP(MAIN_CLK => MAIN_CLK,
INT_HANDLER_TA => INT_HANDLER_TA, INT_HANDLER_TA => INT_HANDLER_TA,
TIN0 => TIN0, TIN0 => TIN0,
ACP_CONF => ACP_CONF, ACP_CONF => ACP_CONF,
nIRQ => nIRQ); nIRQ => nIRQ
);
i_mfp_acia_clk_pll : altpll1 i_mfp_acia_clk_pll : work.altpll1
PORT MAP(inclk0 => MAIN_CLK, PORT MAP
(
inclk0 => MAIN_CLK,
c0 => CLK48M, c0 => CLK48M,
c1 => FDC_CLK, c1 => FDC_CLK,
c2 => CLK24M576, c2 => CLK24M576,
locked => SYNTHESIZED_WIRE_9); locked => pll1_locked
);
i_pll_reconfig : altpll_reconfig1 i_pll_reconfig : altpll_reconfig1
PORT MAP(reconfig => VIDEO_RECONFIG, PORT MAP
(
reconfig => VIDEO_RECONFIG,
read_param => VR_RD, read_param => VR_RD,
write_param => VR_WR, write_param => VR_WR,
pll_areset_in => '0', pll_areset_in => '0',
pll_scandataout => SYNTHESIZED_WIRE_0, pll_scandataout => scandataout,
pll_scandone => SYNTHESIZED_WIRE_1, pll_scandone => scandone,
clock => MAIN_CLK, clock => MAIN_CLK,
reset => SYNTHESIZED_WIRE_2, reset => reset,
counter_param => FB_ADR(8 DOWNTO 6), counter_param => FB_ADR(8 DOWNTO 6),
counter_type => FB_ADR(5 DOWNTO 2), counter_type => FB_ADR(5 DOWNTO 2),
data_in => FB_AD(24 DOWNTO 16), data_in => FB_AD(24 DOWNTO 16),
busy => VR_BUSY, busy => VR_BUSY,
pll_scandata => SYNTHESIZED_WIRE_5, pll_scandata => scandata,
pll_scanclk => SYNTHESIZED_WIRE_4, pll_scanclk => scanclk,
pll_scanclkena => SYNTHESIZED_WIRE_6, pll_scanclkena => scan_clkena,
pll_configupdate => SYNTHESIZED_WIRE_7, pll_configupdate => config_update,
pll_areset => SYNTHESIZED_WIRE_3, pll_areset => pll_reset,
data_out => VR_D); data_out => VR_D
);
i_video : video i_video : work.video
PORT MAP(MAIN_CLK => MAIN_CLK, PORT MAP
(
MAIN_CLK => MAIN_CLK,
nFB_CS1 => nFB_CS1, nFB_CS1 => nFB_CS1,
nFB_CS2 => nFB_CS2, nFB_CS2 => nFB_CS2,
nFB_CS3 => nFB_CS3, nFB_CS3 => nFB_CS3,
@@ -745,7 +487,7 @@ PORT MAP(MAIN_CLK => MAIN_CLK,
FB_ALE => FB_ALE, FB_ALE => FB_ALE,
DDR_SYNC_66M => DDR_SYNC_66M, DDR_SYNC_66M => DDR_SYNC_66M,
CLK33M => CLK33M, CLK33M => CLK33M,
CLK25M => CLK25M_ALTERA_SYNTHESIZED, CLK25M => clk25m_i,
CLK_VIDEO => CLK_VIDEO, CLK_VIDEO => CLK_VIDEO,
VR_BUSY => VR_BUSY, VR_BUSY => VR_BUSY,
DDRCLK => DDRCLK, DDRCLK => DDRCLK,
@@ -774,113 +516,114 @@ PORT MAP(MAIN_CLK => MAIN_CLK,
VB => VB, VB => VB,
VDM => VDM, VDM => VDM,
VG => VG, VG => VG,
VR => VR); VR => VR
);
i_video_clk_pll : altpll4 i_video_clk_pll : altpll4
PORT MAP(inclk0 => CLK48M, PORT MAP
areset => SYNTHESIZED_WIRE_3, (
scanclk => SYNTHESIZED_WIRE_4, inclk0 => CLK48M,
scandata => SYNTHESIZED_WIRE_5, areset => pll_reset,
scanclkena => SYNTHESIZED_WIRE_6, scanclk => scanclk,
configupdate => SYNTHESIZED_WIRE_7, scandata => scandata,
scanclkena => scan_clkena,
configupdate => config_update,
c0 => CLK_VIDEO, c0 => CLK_VIDEO,
scandataout => SYNTHESIZED_WIRE_0, scandataout => scandataout,
scandone => SYNTHESIZED_WIRE_1); scandone => scandone
);
inst1 : lpm_ff0 inst1 : work.lpm_ff0
PORT MAP(clock => DDR_SYNC_66M, PORT MAP
(
clock => DDR_SYNC_66M,
enable => FB_ALE, enable => FB_ALE,
data => FB_AD, data => FB_AD,
q => FB_ADR); q => FB_ADR
);
nMOT_ON <= NOT(MOT_ON);
nSTEP_DIR <= NOT(STEP_DIR);
nSTEP <= NOT(STEP);
nWR <= NOT(WR_DATA);
inst18 : work.lpm_counter0
PORT MAP
(
clock => CLK500k,
q => TIMEBASE
);
nWR_GATE <= NOT(WR_GATE);
nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA);
nMOT_ON <= NOT(MOT_ON); CLK33M <= MAIN_CLK;
reset <= NOT(nRSTO);
nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF;
inst29 : alt_iobuf
nSTEP_DIR <= NOT(STEP_DIR); PORT MAP
(
i => CLK2M,
nSTEP <= NOT(STEP);
nWR <= NOT(WR_DATA);
inst18 : lpm_counter0
PORT MAP(clock => CLK500k,
q => TIMEBASE);
nWR_GATE <= NOT(WR_GATE);
nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA);
CLK33M <= MAIN_CLK;
SYNTHESIZED_WIRE_2 <= NOT(nRSTO);
nRSTO <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_9 AND nRSTO_MCF;
inst29 : alt_iobuf
PORT MAP(i => CLK2M,
oe => CLK2M, oe => CLK2M,
io => MIDI_IN_PIN, io => MIDI_IN_PIN,
o => MIDI_IN); o => MIDI_IN
);
LED_FPGA_OK <= TIMEBASE(17); LED_FPGA_OK <= TIMEBASE(17);
nDDR_CLK <= NOT(DDRCLK(0));
inst5 : work.altddio_out3
nDDR_CLK <= NOT(DDRCLK(0)); PORT MAP
(
datain_h => VSYNC,
inst5 : altddio_out3
PORT MAP(datain_h => VSYNC,
datain_l => VSYNC, datain_l => VSYNC,
outclock => PIXEL_CLK, outclock => PIXEL_CLK,
dataout => VSYNC_PAD); dataout => VSYNC_PAD
);
inst6 : altddio_out3 inst6 : work.altddio_out3
PORT MAP(datain_h => HSYNC, PORT MAP
(
datain_h => HSYNC,
datain_l => HSYNC, datain_l => HSYNC,
outclock => PIXEL_CLK, outclock => PIXEL_CLK,
dataout => HSYNC_PAD); dataout => HSYNC_PAD
);
inst8 : altddio_out3 inst8 : work.altddio_out3
PORT MAP(datain_h => nBLANK, PORT MAP
(
datain_h => nBLANK,
datain_l => nBLANK, datain_l => nBLANK,
outclock => PIXEL_CLK, outclock => PIXEL_CLK,
dataout => nBLANK_PAD); dataout => nBLANK_PAD
);
inst9 : work.altddio_out3
inst9 : altddio_out3 PORT MAP
PORT MAP(datain_h => SYNTHESIZED_WIRE_10, (
datain_l => SYNTHESIZED_WIRE_11, datain_h => '0',
datain_l => '1',
outclock => PIXEL_CLK, outclock => PIXEL_CLK,
dataout => PIXEL_CLK_PAD); dataout => PIXEL_CLK_PAD
);
SD_CMD_D1 <= SD_CDM_D1; SD_CMD_D1 <= SD_CDM_D1;
DDR_CLK <= DDRCLK(0); DDR_CLK <= DDRCLK(0);
LPDIR <= LP_DIR; LPDIR <= LP_DIR;
CLK25M <= CLK25M_ALTERA_SYNTHESIZED; CLK25M <= clk25m_i;
CLKUSB <= CLK48M; CLKUSB <= CLK48M;
nSRCS <= nSRCS_i;
nIDE_RD <= nIDE_RD_i;
nIDE_WR <= nIDE_WR_i;
END rtl; END rtl;