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FPGA_by_Fredi/altpll_reconfig1.cmp

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+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll_reconfig1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		counter_param		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		counter_type		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		data_in		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset_in		: IN STD_LOGIC  := '0';
+		pll_scandataout		: IN STD_LOGIC ;
+		pll_scandone		: IN STD_LOGIC ;
+		read_param		: IN STD_LOGIC ;
+		reconfig		: IN STD_LOGIC ;
+		reset		: IN STD_LOGIC ;
+		write_param		: IN STD_LOGIC ;
+		busy		: OUT STD_LOGIC ;
+		data_out		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset		: OUT STD_LOGIC ;
+		pll_configupdate		: OUT STD_LOGIC ;
+		pll_scanclk		: OUT STD_LOGIC ;
+		pll_scanclkena		: OUT STD_LOGIC ;
+		pll_scandata		: OUT STD_LOGIC 
+	);
+end component;