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translate DDR_CTR to vhd

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This commit is contained in:
Markus Fröschle
2016-01-11 17:55:18 +00:00
parent 35d70dc637
commit 3ec978dff5
3 changed files with 1375 additions and 196 deletions
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6
FPGA_Quartus_13.1/Video/DDR_CTR.tdf
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@@ -657,10 +657,10 @@ BEGIN
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT( % FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) VIDEO_BASE_H & (0, VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]),
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); %
FB_AD[23..16] = lpm_bustri_BYT( FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[] VIDEO_BASE_L & VIDEO_BASE_L_D[]

1203
FPGA_Quartus_13.1/Video/DDR_CTR.vhd Executable file
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File diff suppressed because it is too large Load Diff

142
FPGA_Quartus_13.1/Video/video.vhd
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@@ -69,83 +69,108 @@ ENTITY video IS
); );
END video; END video;
ARCHITECTURE bdf_type OF video IS ARCHITECTURE rtl OF video IS
ATTRIBUTE black_box : BOOLEAN; ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN; ATTRIBUTE noopt : BOOLEAN;
COMPONENT mux41_0 COMPONENT mux41_0
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
END COMPONENT; );
END COMPONENT mux41_0;
ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;
COMPONENT mux41_1 COMPONENT mux41_1
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
END COMPONENT; );
END COMPONENT mux41_1;
ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; ATTRIBUTE black_box OF mux41_1: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; ATTRIBUTE noopt OF mux41_1: COMPONENT IS true;
COMPONENT mux41_2 COMPONENT mux41_2
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
D2 : IN std_logic; D2 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
END COMPONENT; );
END COMPONENT mux41_2;
ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; ATTRIBUTE black_box OF mux41_2: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; ATTRIBUTE noopt OF mux41_2: COMPONENT IS true;
COMPONENT mux41_3 COMPONENT mux41_3
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
D2 : IN std_logic; D2 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
END COMPONENT; );
END COMPONENT mux41_3;
ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; ATTRIBUTE black_box OF mux41_3: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; ATTRIBUTE noopt OF mux41_3: COMPONENT IS true;
COMPONENT mux41_4 COMPONENT mux41_4
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
D2 : IN std_logic; D2 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
);
END COMPONENT; END COMPONENT;
ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; ATTRIBUTE black_box OF mux41_4: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; ATTRIBUTE noopt OF mux41_4: COMPONENT IS true;
COMPONENT mux41_5 COMPONENT mux41_5
PORT(S0 : IN std_logic; PORT
(
S0 : IN std_logic;
D2 : IN std_logic; D2 : IN std_logic;
S1 : IN std_logic; S1 : IN std_logic;
D0 : IN std_logic; D0 : IN std_logic;
INH : IN std_logic; INH : IN std_logic;
D1 : IN std_logic; D1 : IN std_logic;
Q : OUT std_logic); Q : OUT std_logic
);
END COMPONENT; END COMPONENT;
ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; ATTRIBUTE black_box OF mux41_5: COMPONENT IS true;
ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; ATTRIBUTE noopt OF mux41_5: COMPONENT IS true;
COMPONENT altdpram2 COMPONENT altdpram2
PORT(wren_a : IN std_logic; PORT
(
wren_a : IN std_logic;
wren_b : IN std_logic; wren_b : IN std_logic;
clock_a : IN std_logic; clock_a : IN std_logic;
clock_b : IN std_logic; clock_b : IN std_logic;
@@ -159,7 +184,9 @@ ARCHITECTURE bdf_type OF video IS
END COMPONENT; END COMPONENT;
COMPONENT blitter COMPONENT blitter
PORT(nRSTO : IN std_logic; PORT
(
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic; MAIN_CLK : IN std_logic;
FB_ALE : IN std_logic; FB_ALE : IN std_logic;
nFB_WR : IN std_logic; nFB_WR : IN std_logic;
@@ -187,7 +214,9 @@ ARCHITECTURE bdf_type OF video IS
END COMPONENT; END COMPONENT;
COMPONENT ddr_ctr COMPONENT ddr_ctr
PORT(nFB_CS1 : IN std_logic; PORT
(
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic; nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic; nFB_CS3 : IN std_logic;
nFB_OE : IN std_logic; nFB_OE : IN std_logic;
@@ -227,7 +256,7 @@ ARCHITECTURE bdf_type OF video IS
VA : OUT std_logic_vector(12 DOWNTO 0); VA : OUT std_logic_vector(12 DOWNTO 0);
VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) VDM_SEL : OUT std_logic_vector(3 DOWNTO 0)
); );
END COMPONENT; END COMPONENT ddr_ctr;
COMPONENT altdpram1 COMPONENT altdpram1
PORT(wren_a : IN std_logic; PORT(wren_a : IN std_logic;
@@ -760,6 +789,7 @@ BEGIN
VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0);
VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8);
VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16);
SYNTHESIZED_WIRE_0 <= '0'; SYNTHESIZED_WIRE_0 <= '0';
SYNTHESIZED_WIRE_1 <= '0'; SYNTHESIZED_WIRE_1 <= '0';
SYNTHESIZED_WIRE_2 <= '0'; SYNTHESIZED_WIRE_2 <= '0';
@@ -1023,18 +1053,12 @@ BEGIN
result => ZR_C8B(0)); result => ZR_C8B(0));
CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8;
CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4;
CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61;
CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8;
CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4;
SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2;
@@ -1216,22 +1240,11 @@ BEGIN
data => VDP_IN(63 DOWNTO 32), data => VDP_IN(63 DOWNTO 32),
q => VDVZ(63 DOWNTO 32)); q => VDVZ(63 DOWNTO 32));
CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A;
CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18;
SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8;
SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8;
SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8;
SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8;
@@ -1499,40 +1512,10 @@ BEGIN
PROCESS(DDRCLK(0), DDR_WR) PROCESS(DDRCLK(0), DDR_WR)
BEGIN BEGIN
if (DDR_WR = '1') THEN IF (DDR_WR = '1') THEN
VDQS(3) <= DDRCLK(0); VDQS <= (OTHERS => DDRCLK(0));
ELSE ELSE
VDQS(3) <= 'Z'; VDQS <= (OTHERS => 'Z');
END IF;
END PROCESS;
PROCESS(DDRCLK(0),DDR_WR)
BEGIN
if (DDR_WR = '1') THEN
VDQS(2) <= DDRCLK(0);
ELSE
VDQS(2) <= 'Z';
END IF;
END PROCESS;
PROCESS(DDRCLK(0),DDR_WR)
BEGIN
if (DDR_WR = '1') THEN
VDQS(1) <= DDRCLK(0);
ELSE
VDQS(1) <= 'Z';
END IF;
END PROCESS;
PROCESS(DDRCLK(0),DDR_WR)
BEGIN
if (DDR_WR = '1') THEN
VDQS(0) <= DDRCLK(0);
ELSE
VDQS(0) <= 'Z';
END IF; END IF;
END PROCESS; END PROCESS;
@@ -1541,6 +1524,7 @@ BEGIN
BEGIN BEGIN
IF (rising_edge(DDRCLK(3))) THEN IF (rising_edge(DDRCLK(3))) THEN
DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL;
DDR_WR <= SR_DDR_WR;
END IF; END IF;
END PROCESS; END PROCESS;
@@ -1557,14 +1541,6 @@ BEGIN
q => CC24); q => CC24);
PROCESS(DDRCLK(3))
BEGIN
IF (rising_edge(DDRCLK(3))) THEN
DDR_WR <= SR_DDR_WR;
END IF;
END PROCESS;
PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
BEGIN BEGIN
IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
@@ -1764,4 +1740,4 @@ BEGIN
VIDEO_RAM_CTR => VIDEO_RAM_CTR); VIDEO_RAM_CTR => VIDEO_RAM_CTR);
PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED;
END bdf_type; END rtl;