Sync with Fredi's source 22/06/2017

Blitter work.

FPGA_by_Fredi/Video/BLITTER/lpm_ror128.inc

@@ -13,14 +13,12 @@
 --applicable agreement for further details.
 
 
-component lpm_fifoDZ
-	PORT
-	(
-		aclr		: IN STD_LOGIC ;
-		clock		: IN STD_LOGIC ;
-		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		rdreq		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
-	);
-end component;
+FUNCTION lpm_ror128 
+(
+	data[127..0],
+	distance[6..0]
+)
+
+RETURNS (
+	result[127..0]
+);

FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.cmp"]

FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf

@@ -0,0 +1,92 @@
+-- megafunction wizard: %LPM_CLSHIFT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_clshift 
+
+-- ============================================================
+-- File Name: lpm_ror128.tdf
+-- Megafunction Name(s):
+-- 			lpm_clshift
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_clshift.inc";
+
+
+
+SUBDESIGN lpm_ror128
+(
+	data[127..0]	 : INPUT;
+	distance[6..0]	 : INPUT;
+	result[127..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_clshift_component : lpm_clshift WITH (
+			LPM_SHIFTTYPE = "ROTATE",
+			LPM_TYPE = "LPM_CLSHIFT",
+			LPM_WIDTH = 128,
+			LPM_WIDTHDIST = 7
+			);
+
+BEGIN
+
+	result[127..0] = lpm_clshift_component.result[127..0];
+	lpm_clshift_component.distance[6..0] = distance[6..0];
+	lpm_clshift_component.direction = VCC;
+	lpm_clshift_component.data[127..0] = data[127..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "2"
+-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
+-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
+-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
+-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "ROTATE"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128_inst.tdf FALSE

FPGA_by_Fredi/Video/DDR_CTR.tdf.bak

@@ -1,659 +0,0 @@
-TITLE "DDR_CTR";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_BYT.inc";
-
--- FIFO WATER MARK
-CONSTANT FIFO_LWM = 0;
-CONSTANT FIFO_MWM = 1000;
-CONSTANT FIFO_HWM = 2000;
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN DDR_CTR
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	DDR_SYNC_66M : INPUT;
-	CLR_FIFO : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ADR[31..0] : INPUT;
-	BLITTER_SIG : INPUT;
-	BLITTER_WR : INPUT;
-	DDRCLK0 : INPUT;
-	CLK33M : INPUT;
-	FIFO_MW[10..0] : INPUT;
-	VA[12..0] : OUTPUT;
-	nVWE : OUTPUT;
-	nVRAS : OUTPUT;
-	nVCS : OUTPUT;
-	VCKE : OUTPUT;
-	nVCAS : OUTPUT;
-	FB_LE[3..0] : OUTPUT;
-	FB_VDOE[3..0] : OUTPUT;
-	SR_FIFO_WRE : OUTPUT;
-	SR_DDR_FB : OUTPUT;
-	SR_DDR_WR : OUTPUT;
-	SR_DDRWR_D_SEL : OUTPUT;
-	SR_VDMP[7..0] : OUTPUT;
-	VIDEO_DDR_TA : OUTPUT;
-	SR_BLITTER_DACK : OUTPUT;
-	BA[1..0] : OUTPUT;
-	DDRWR_D_SEL1 : OUTPUT;
-	VDM_SEL[3..0] : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
-													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
-												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
-												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
-												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
-																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
-												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
-	LINE					:NODE;
-	FB_B[3..0]				:NODE;
-	VCAS					:NODE;
-	VRAS					:NODE;
-	VWE						:NODE;
-	VA_P[12..0]				:DFF;
-	BA_P[1..0]				:DFF;
-	VA_S[12..0]				:DFF;
-	BA_S[1..0]				:DFF;
-	MCS[1..0]				:DFF;
-	CPU_DDR_SYNC			:DFF;
-	DDR_SEL					:NODE;
-	DDR_CS					:DFFE;
-	DDR_CONFIG				:NODE;
-	SR_DDR_WR				:DFF;
-	SR_DDRWR_D_SEL			:DFF;
-	SR_VDMP[7..0] 			:DFF;
-	CPU_ROW_ADR[12..0]		:NODE;
-	CPU_BA[1..0]			:NODE;
-	CPU_COL_ADR[9..0]		:NODE;
-	CPU_SIG					:NODE;
-	CPU_REQ					:DFF;
-	CPU_AC					:DFF;
-	BUS_CYC					:DFF;
-	BUS_CYC_END				:NODE;
-	BLITTER_REQ				:DFF;
-	BLITTER_AC				:DFF;
-	BLITTER_ROW_ADR[12..0]	:NODE;
-	BLITTER_BA[1..0]		:NODE;
-	BLITTER_COL_ADR[9..0]	:NODE;
-	FIFO_REQ				:DFF;
-	FIFO_AC					:DFF;
-	FIFO_ROW_ADR[12..0]		:NODE;
-	FIFO_BA[1..0]			:NODE;
-	FIFO_COL_ADR[9..0]		:NODE;
-	FIFO_ACTIVE				:NODE;
-	CLR_FIFO_SYNC			:DFF;
-	CLEAR_FIFO_CNT			:DFF;
-	STOP					:DFF;
-	SR_FIFO_WRE				:DFF;
-	FIFO_BANK_OK			:DFF;
-	FIFO_BANK_NOT_OK		:NODE;
-	DDR_REFRESH_ON			:NODE;
-	DDR_REFRESH_CNT[10..0]	:DFF;
-	DDR_REFRESH_REQ			:DFF;
-	DDR_REFRESH_SIG[3..0]	:DFFE;
-	REFRESH_TIME			:DFF;
-	VIDEO_BASE_L_D[7..0]	:DFFE;
-	VIDEO_BASE_L			:NODE;
-	VIDEO_BASE_M_D[7..0]	:DFFE;
-	VIDEO_BASE_M			:NODE;
-	VIDEO_BASE_H_D[7..0]	:DFFE;
-	VIDEO_BASE_H			:NODE;
-	VIDEO_BASE_X_D[2..0]	:DFFE;
-	VIDEO_ADR_CNT[22..0]	:DFFE;
-	VIDEO_CNT_L				:NODE;
-	VIDEO_CNT_M				:NODE;
-	VIDEO_CNT_H				:NODE;
-	VIDEO_BASE_ADR[22..0]	:NODE;
-	VIDEO_ACT_ADR[26..0]	:NODE;
-	
-BEGIN
-	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
-	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
-	FB_REGDDR.CLK = MAIN_CLK;
-	CASE FB_REGDDR IS
-		WHEN FR_WAIT => 
-			FB_LE0   = !nFB_WR;
-			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
-				FB_REGDDR = FR_S0;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S0 =>
-			IF DDR_CS THEN
-				FB_LE0   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				IF LINE THEN							
-					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
-					FB_REGDDR = FR_S1;
-				ELSE
-					BUS_CYC_END = VCC;
-					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-					FB_REGDDR = FR_WAIT;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;	
-			END IF;
-		WHEN FR_S1 => 
-			IF DDR_CS THEN
-				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
-				FB_LE1   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				FB_REGDDR = FR_S2;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S2 => 
-			IF DDR_CS THEN
-				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
-				FB_LE2   = !nFB_WR;
-				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
-					FB_REGDDR = FR_S2;
-				ELSE
-					VIDEO_DDR_TA = VCC;
-					FB_REGDDR = FR_S3;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S3 => 
-			IF DDR_CS THEN
-				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-				FB_LE3   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				BUS_CYC_END = VCC;
-				FB_REGDDR = FR_WAIT;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
--- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
-	VCKE = VIDEO_RAM_CTR0;
-	nVCS = !VIDEO_RAM_CTR1;
-	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
-	DDR_CONFIG = VIDEO_RAM_CTR3;	
-	FIFO_ACTIVE = VIDEO_RAM_CTR8;
---------------------------------
-	CPU_ROW_ADR[] = FB_ADR[26..14];
-	CPU_BA[] = FB_ADR[13..12];
-	CPU_COL_ADR[] = FB_ADR[11..2];
-	nVRAS = !VRAS;
-	nVCAS = !VCAS;
-	nVWE = !VWE;
-	SR_DDR_WR.CLK = DDRCLK0;
-	SR_DDRWR_D_SEL.CLK = DDRCLK0;
-	SR_VDMP[7..0].CLK = DDRCLK0;
-	SR_FIFO_WRE.CLK = DDRCLK0; 
-	CPU_AC.CLK = DDRCLK0;
-	FIFO_AC.CLK = DDRCLK0;
-	BLITTER_AC.CLK = DDRCLK0;
-	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
-	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
-	DDR_CS.CLK = MAIN_CLK;
-	DDR_CS.ENA = FB_ALE;
-	DDR_CS	 = DDR_SEL;
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
-	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
-			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
-			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SP<53>TER
-	CPU_REQ.CLK = DDR_SYNC_66M;
-	CPU_REQ = CPU_SIG 
-			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
-	BUS_CYC.CLK = DDRCLK0;
-	BUS_CYC = BUS_CYC & !BUS_CYC_END;
-	-- STATE MACHINE SYNCHRONISIEREN -----------------
-	MCS[].CLK = DDRCLK0;
-	MCS0 = MAIN_CLK;
-	MCS1 = MCS0;		
-	CPU_DDR_SYNC.CLK = DDRCLK0;
-	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
-	---------------------------------------------------
-	VA_S[].CLK = DDRCLK0;
-	BA_S[].CLK = DDRCLK0;
-	VA[] =  VA_S[];
-	BA[] =  BA_S[];
-	VA_P[].CLK = DDRCLK0;
-	BA_P[].CLK = DDRCLK0;
--- DDR STATE MACHINE  -----------------------------------------------
-	DDR_SM.CLK = DDRCLK0;
-	CASE DDR_SM IS
-		WHEN DS_T1 =>
-			IF DDR_REFRESH_REQ THEN
-				DDR_SM = DS_R2;
-			ELSE
-				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
-					IF DDR_CONFIG THEN							-- JA
-						DDR_SM = DS_C2;
-					ELSE
-						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
-							VA_S[] = CPU_ROW_ADR[];
-							BA_S[] = CPU_BA[];
-							CPU_AC = VCC;
-							BUS_CYC = VCC;
-							DDR_SM = DS_T2B;
-						ELSE
-							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
-								VA_P[] = FIFO_ROW_ADR[];
-								BA_P[] = FIFO_BA[];
-								FIFO_AC = VCC;						-- VORBESETZEN
-							ELSE
-								VA_P[] = BLITTER_ROW_ADR[];
-								BA_P[] = BLITTER_BA[];
-								BLITTER_AC = VCC;					-- VORBESETZEN
-							END IF;
-							DDR_SM = DS_T2A;
-						END IF;
-					END IF;
-				ELSE
-					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
-				END IF;
-			END IF;
-			
-		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
-			IF DDR_SEL & (nFB_WR # !LINE) THEN
-				VRAS = VCC;
-				VA[] = FB_AD[26..14];
-				BA[] = FB_AD[13..12]; 
-				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
-				CPU_AC = VCC;
-				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
-			ELSE
-				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
-				VA[] = VA_P[];
-				BA[] = BA_P[]; 
-				VA_S[10] = !(FIFO_AC & FIFO_REQ);
-				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
-				FIFO_AC = FIFO_AC & FIFO_REQ;
-				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
-			END IF;	
-			DDR_SM = DS_T3;
-
-		WHEN DS_T2B =>
-			VRAS = VCC;
-			FIFO_BANK_NOT_OK = VCC;
-			CPU_AC = VCC;
-			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
-			DDR_SM = DS_T3;
-
-		WHEN DS_T3 =>
-			CPU_AC = CPU_AC;
-			FIFO_AC = FIFO_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
-				DDR_SM = DS_T4W;
-			ELSE
-				IF CPU_AC THEN										-- CPU?
-					VA_S[9..0] = CPU_COL_ADR[];
-					BA_S[] = CPU_BA[];
-					DDR_SM = DS_T4R;												 
-				ELSE
-					IF FIFO_AC THEN									-- FIFO?
-						VA_S[9..0] = FIFO_COL_ADR[];
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T4F;
-					ELSE
-						IF BLITTER_AC THEN
-							VA_S[9..0] = BLITTER_COL_ADR[];
-							BA_S[] = BLITTER_BA[];
-							DDR_SM = DS_T4R;												 
-						ELSE
-							DDR_SM = DS_N8;
-						END IF;
-					END IF;
-				END IF;
-			END IF;
--- READ			
-		WHEN DS_T4R =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			SR_DDR_FB = CPU_AC;										-- READ DATEN F<>R CPU
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
-			DDR_SM = DS_T5R;	
-			
-		WHEN DS_T5R =>
- 			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
- 				VA_S[9..0] = FIFO_COL_ADR[];
- 				VA_S[10] = GND;										-- MANUEL PRECHARGE
- 				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
- 			ELSE	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- WRITE			
-		WHEN DS_T4W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
- 			DDR_SM = DS_T5W;
-			
-		WHEN DS_T5W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
-					   # BLITTER_AC & BLITTER_COL_ADR[];
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			BA_S[]  = CPU_AC     & CPU_BA[]
-				    # BLITTER_AC & BLITTER_BA[];
-			SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111";			-- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
-			SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111";			-- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
-			DDR_SM = DS_T6W;
-			
-		WHEN DS_T6W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			VWE  = VCC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
-			SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111";			-- WENN LINE DANN ACTIV 
-			DDR_SM = DS_T7W;
-
-		WHEN DS_T7W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
-			SR_DDRWR_D_SEL = VCC;									-- 2. H<>LFTE WRITE DATEN SELEKTIEREN
-			DDR_SM = DS_T8W;
-
-		WHEN DS_T8W =>								 
-			DDR_SM = DS_T9W;
-
-		WHEN DS_T9W =>								 
-			IF FIFO_REQ & FIFO_BANK_OK  THEN
-				VA_S[9..0] = FIFO_COL_ADR[];
-				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
-				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- FIFO READ 
-		WHEN DS_T4F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T5F;
-			
-		WHEN DS_T5F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
-					VA_S[9..0] = FIFO_COL_ADR[]+4;
-					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_S[] = FIFO_BA[];
-					DDR_SM = DS_T6F;
-				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
-			END IF;
-			
-		WHEN DS_T6F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T7F;
-																							 
-		WHEN DS_T7F =>
-			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
-				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
-			ELSE
-				IF FIFO_REQ THEN
-					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
-						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
-						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
-					ELSE
-						VA_S[9..0] = FIFO_COL_ADR[]+4;
-						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T8F;
-					END IF;											 
-				ELSE
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
-					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
-				END IF;
-			END IF;
-			
-		WHEN DS_T8F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
-				DDR_SM = DS_T5F;									-- JA->
-			ELSE
-				DDR_SM = DS_T9F;
-			END IF;																	 
-			
-		WHEN DS_T9F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
- 					VA_P[9..0] = FIFO_COL_ADR[]+4;
-					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_P[] = FIFO_BA[];
-					DDR_SM = DS_T10F;
- 				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
-				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
-			END IF;
-
-		WHEN DS_T10F =>
- 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
- 				VRAS = VCC;
- 				VA[] = FB_AD[26..14];
- 				BA[] = FB_AD[13..12]; 
- 				CPU_AC = VCC;
- 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
- 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
- 				DDR_SM = DS_T3;
- 			ELSE
-				VCAS = VCC;
-				VA[] = VA_P[];
-				BA[] = BA_P[];
-				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
-				DDR_SM = DS_T7F;
-			END IF;	
-
--- CONFIG CYCLUS
-		WHEN DS_C2 =>
-			DDR_SM = DS_C3;
-		WHEN DS_C3 =>
-			BUS_CYC = CPU_REQ;
-			DDR_SM = DS_C4;
-		WHEN DS_C4 =>
-			IF CPU_REQ THEN
-				DDR_SM = DS_C5;
-			ELSE
-				DDR_SM = DS_T1;
-			END IF;	
-		WHEN DS_C5 =>
-			DDR_SM = DS_C6;
-		WHEN DS_C6 =>
-			VA_S[] = FB_AD[12..0];
-			BA_S[] = FB_AD[14..13];
-			DDR_SM = DS_C7;
-		WHEN DS_C7 =>
-			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			DDR_SM = DS_N8;
--- CLOSE FIFO BANK
-		WHEN DS_CB6 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_N7;
-		WHEN DS_CB8 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- B<>NKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_T1;
--- REFRESH 70NS = 10 ZYCLEN
-		WHEN DS_R2 =>
-			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
-				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
-				VWE = VCC;		
-				VA[10] = VCC;
-				FIFO_BANK_NOT_OK = VCC;
-				DDR_SM = DS_R4;
-			ELSE
-				VCAS = VCC;
-				VRAS = VCC;
-				DDR_SM = DS_R3;
-			END IF;
-		WHEN DS_R3 =>
-			DDR_SM = DS_R4;
-		WHEN DS_R4 =>
-			DDR_SM = DS_R5;
-		WHEN DS_R5 =>
-			DDR_SM = DS_R6;
-		WHEN DS_R6 =>
-			DDR_SM = DS_N5;
--- LEERSCHLAUFE			
-		WHEN DS_N5 =>
-			DDR_SM = DS_N6;
-		WHEN DS_N6 =>
-			DDR_SM = DS_N7;
-		WHEN DS_N7 =>
-			DDR_SM = DS_N8;
-		WHEN DS_N8 =>
-			DDR_SM = DS_T1;
-	END CASE;
-
----------------------------------------------------------------
--- BLITTER ----------------------
------------------------------------------
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
-	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
-	BLITTER_BA1 = BLITTER_ADR13;
-	BLITTER_BA0 = BLITTER_ADR12;
-	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
-------------------------------------------------------------------------------	
--- FIFO ---------------------------------
---------------------------------------------------------
-	FIFO_REQ.CLK = DDRCLK0;
-	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
-			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
-	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
-	FIFO_BA1 	   = VIDEO_ADR_CNT9;
-	FIFO_BA0 	   = VIDEO_ADR_CNT8;
-	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
-	FIFO_BANK_OK.CLK = DDRCLK0;
-	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-	-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
-	CLR_FIFO_SYNC.CLK =DDRCLK0;
-	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
-	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
-	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
-	STOP.CLK = DDRCLK0;
-	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-	-- Z<>HLEN -----------------------------------------------
-	VIDEO_ADR_CNT[].CLK = DDRCLK0;
-	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
-	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
-					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
-	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
-	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
-	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
-	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
-	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-	-- AKTUELLE VIDEO ADRESSE
-	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
-	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
------------------------------------------------------------------------------------------
--- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
------------------------------------------------------------------------------------------
-	DDR_REFRESH_CNT[].CLK = CLK33M;
-	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- Z<>HLEN 0-2047 
-	REFRESH_TIME.CLK = DDRCLK0;
-	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
-	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
-	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
-	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
-					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
-	DDR_REFRESH_REQ.CLK = DDRCLK0;
-	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
------------------------------------------------------------	
--- VIDEO REGISTER -----------------------
----------------------------------------------------------------------------------------------------------------------
-	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
-	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
-	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
-
-	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
-	VIDEO_BASE_M_D[] = FB_AD[23..16];
-	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
-
-	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
-	VIDEO_BASE_H_D[] = FB_AD[23..16];
-	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
-	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_X_D[] = FB_AD[26..24];
-	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
-
-	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
-	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
-	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
-					  
-	FB_AD[31..24] = lpm_bustri_BYT(
-						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
-					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
-					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
-
-	FB_AD[23..16] = lpm_bustri_BYT(
-						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
-					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
-					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
-					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
-					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
-					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
-					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
-END;
-

FPGA_by_Fredi/Video/Doppelzeilen_Fifo.bsf

@@ -21,7 +21,7 @@ applicable agreement for further details.
 (header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 160 144)
-	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
+	(text "Doppelzeilen_Fifo" (rect 29 1 149 17)(font "Arial" (font_size 10)))
 	(text "inst" (rect 8 128 25 140)(font "Arial" ))
 	(port
 		(pt 0 32)
@@ -66,7 +66,6 @@ applicable agreement for further details.
 		(line (pt 160 32)(pt 144 32)(line_width 3))
 	)
 	(drawing
-		(text "(ack)" (rect 51 67 72 79)(font "Arial" ))
 		(text "128 bits x 512 words" (rect 58 116 144 128)(font "Arial" ))
 		(line (pt 16 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 128)(line_width 1))

FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc

@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION Doppelzeilen_Fifo 
+(
+	aclr,
+	clock,
+	data[127..0],
+	rdreq,
+	wrreq
+)
+
+RETURNS (
+	q[127..0]
+);

FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.inc"]

FPGA_by_Fredi/Video/Doppelzeilen_Fifo.vhd

@@ -1,10 +1,10 @@
--- megafunction wizard: %LPM_FIFO+%
+-- megafunction wizard: %FIFO%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
 -- MODULE: scfifo 
 
 -- ============================================================
--- File Name: lpm_fifoDZ.vhd
+-- File Name: Doppelzeilen_Fifo.vhd
 -- Megafunction Name(s):
 -- 			scfifo
 --
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_mf;
 USE altera_mf.all;
 
-ENTITY lpm_fifoDZ IS
+ENTITY Doppelzeilen_Fifo IS
 	PORT
 	(
 		aclr		: IN STD_LOGIC ;
@@ -49,10 +49,10 @@ ENTITY lpm_fifoDZ IS
 		wrreq		: IN STD_LOGIC ;
 		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
 	);
-END lpm_fifoDZ;
+END Doppelzeilen_Fifo;
 
 
-ARCHITECTURE SYN OF lpm_fifodz IS
+ARCHITECTURE SYN OF doppelzeilen_fifo IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
 
@@ -86,10 +86,10 @@ BEGIN
 
 	scfifo_component : scfifo
 	GENERIC MAP (
-		add_ram_output_register => "OFF",
+		add_ram_output_register => "ON",
 		intended_device_family => "Cyclone III",
 		lpm_numwords => 512,
-		lpm_showahead => "ON",
+		lpm_showahead => "OFF",
 		lpm_type => "scfifo",
 		lpm_width => 128,
 		lpm_widthu => 9,
@@ -117,38 +117,38 @@ END SYN;
 -- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
 -- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
 -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 -- Retrieval info: PRIVATE: Clock NUMERIC "0"
 -- Retrieval info: PRIVATE: Depth NUMERIC "512"
 -- Retrieval info: PRIVATE: Empty NUMERIC "0"
 -- Retrieval info: PRIVATE: Full NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
 -- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 -- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
--- Retrieval info: PRIVATE: Optimize NUMERIC "2"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
 -- Retrieval info: PRIVATE: UsedW NUMERIC "0"
 -- Retrieval info: PRIVATE: Width NUMERIC "128"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
 -- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
 -- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
 -- Retrieval info: PRIVATE: output_width NUMERIC "128"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
 -- Retrieval info: PRIVATE: rsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
 -- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
 -- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
 -- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
--- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
 -- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
@@ -168,11 +168,11 @@ END SYN;
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_wave*.jpg FALSE
 -- Retrieval info: LIB_FILE: altera_mf

FPGA_by_Fredi/Video/UNUSED

@@ -1,267 +0,0 @@
-
--- Clearbox generated Memory Initialization File (.mif)
-
-WIDTH=6;
-DEPTH=256;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	000  :   0F;
-	001  :   0E;
-	002  :   0D;
-	003  :   0C;
-	004  :   0B;
-	005  :   0A;
-	006  :   09;
-	007  :   08;
-	008  :   07;
-	009  :   06;
-	00a  :   05;
-	00b  :   04;
-	00c  :   03;
-	00d  :   02;
-	00e  :   01;
-	00f  :   00;
-	010  :   0F;
-	011  :   0E;
-	012  :   0D;
-	013  :   0C;
-	014  :   0B;
-	015  :   0A;
-	016  :   09;
-	017  :   08;
-	018  :   07;
-	019  :   06;
-	01a  :   05;
-	01b  :   04;
-	01c  :   03;
-	01d  :   02;
-	01e  :   01;
-	01f  :   00;
-	020  :   0F;
-	021  :   0E;
-	022  :   0D;
-	023  :   0C;
-	024  :   0B;
-	025  :   0A;
-	026  :   09;
-	027  :   08;
-	028  :   07;
-	029  :   06;
-	02a  :   05;
-	02b  :   04;
-	02c  :   03;
-	02d  :   02;
-	02e  :   01;
-	02f  :   00;
-	030  :   0F;
-	031  :   0E;
-	032  :   0D;
-	033  :   0C;
-	034  :   0B;
-	035  :   0A;
-	036  :   09;
-	037  :   08;
-	038  :   07;
-	039  :   06;
-	03a  :   05;
-	03b  :   04;
-	03c  :   03;
-	03d  :   02;
-	03e  :   01;
-	03f  :   00;
-	040  :   0F;
-	041  :   0E;
-	042  :   0D;
-	043  :   0C;
-	044  :   0B;
-	045  :   0A;
-	046  :   09;
-	047  :   08;
-	048  :   07;
-	049  :   06;
-	04a  :   05;
-	04b  :   04;
-	04c  :   03;
-	04d  :   02;
-	04e  :   01;
-	04f  :   00;
-	050  :   0F;
-	051  :   0E;
-	052  :   0D;
-	053  :   0C;
-	054  :   0B;
-	055  :   0A;
-	056  :   09;
-	057  :   08;
-	058  :   07;
-	059  :   06;
-	05a  :   05;
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-	05c  :   03;
-	05d  :   02;
-	05e  :   01;
-	05f  :   00;
-	060  :   0F;
-	061  :   0E;
-	062  :   0D;
-	063  :   0C;
-	064  :   0B;
-	065  :   0A;
-	066  :   09;
-	067  :   08;
-	068  :   07;
-	069  :   06;
-	06a  :   05;
-	06b  :   04;
-	06c  :   03;
-	06d  :   02;
-	06e  :   01;
-	06f  :   00;
-	070  :   0F;
-	071  :   0E;
-	072  :   0D;
-	073  :   0C;
-	074  :   0B;
-	075  :   0A;
-	076  :   09;
-	077  :   08;
-	078  :   07;
-	079  :   06;
-	07a  :   05;
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-	07c  :   03;
-	07d  :   02;
-	07e  :   01;
-	07f  :   00;
-	080  :   0F;
-	081  :   0E;
-	082  :   0D;
-	083  :   0C;
-	084  :   0B;
-	085  :   0A;
-	086  :   09;
-	087  :   08;
-	088  :   07;
-	089  :   06;
-	08a  :   05;
-	08b  :   04;
-	08c  :   03;
-	08d  :   02;
-	08e  :   01;
-	08f  :   00;
-	090  :   0F;
-	091  :   0E;
-	092  :   0D;
-	093  :   0C;
-	094  :   0B;
-	095  :   0A;
-	096  :   09;
-	097  :   08;
-	098  :   07;
-	099  :   06;
-	09a  :   05;
-	09b  :   04;
-	09c  :   03;
-	09d  :   02;
-	09e  :   01;
-	09f  :   00;
-	0a0  :   0F;
-	0a1  :   0E;
-	0a2  :   0D;
-	0a3  :   0C;
-	0a4  :   0B;
-	0a5  :   0A;
-	0a6  :   09;
-	0a7  :   08;
-	0a8  :   07;
-	0a9  :   06;
-	0aa  :   05;
-	0ab  :   04;
-	0ac  :   03;
-	0ad  :   02;
-	0ae  :   01;
-	0af  :   00;
-	0b0  :   0F;
-	0b1  :   0E;
-	0b2  :   0D;
-	0b3  :   0C;
-	0b4  :   0B;
-	0b5  :   0A;
-	0b6  :   09;
-	0b7  :   08;
-	0b8  :   07;
-	0b9  :   06;
-	0ba  :   05;
-	0bb  :   04;
-	0bc  :   03;
-	0bd  :   02;
-	0be  :   01;
-	0bf  :   00;
-	0c0  :   0F;
-	0c1  :   0E;
-	0c2  :   0D;
-	0c3  :   0C;
-	0c4  :   0B;
-	0c5  :   0A;
-	0c6  :   09;
-	0c7  :   08;
-	0c8  :   07;
-	0c9  :   06;
-	0ca  :   05;
-	0cb  :   04;
-	0cc  :   03;
-	0cd  :   02;
-	0ce  :   01;
-	0cf  :   00;
-	0d0  :   0F;
-	0d1  :   0E;
-	0d2  :   0D;
-	0d3  :   0C;
-	0d4  :   0B;
-	0d5  :   0A;
-	0d6  :   09;
-	0d7  :   08;
-	0d8  :   07;
-	0d9  :   06;
-	0da  :   05;
-	0db  :   04;
-	0dc  :   03;
-	0dd  :   02;
-	0de  :   01;
-	0df  :   00;
-	0e0  :   0F;
-	0e1  :   0E;
-	0e2  :   0D;
-	0e3  :   0C;
-	0e4  :   0B;
-	0e5  :   0A;
-	0e6  :   09;
-	0e7  :   08;
-	0e8  :   07;
-	0e9  :   06;
-	0ea  :   05;
-	0eb  :   04;
-	0ec  :   03;
-	0ed  :   02;
-	0ee  :   01;
-	0ef  :   00;
-	0f0  :   0F;
-	0f1  :   0E;
-	0f2  :   0D;
-	0f3  :   0C;
-	0f4  :   0B;
-	0f5  :   0A;
-	0f6  :   09;
-	0f7  :   08;
-	0f8  :   07;
-	0f9  :   06;
-	0fa  :   05;
-	0fb  :   04;
-	0fc  :   03;
-	0fd  :   02;
-	0fe  :   01;
-	0ff  :   00;
-END;

FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf

@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
 	VR_WR : OUTPUT;
 	VR_RD : OUTPUT;
 	CLR_FIFO : OUTPUT;
+	DPZF_CLKENA: OUTPUT;
 	FB_AD[31..0] : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
@@ -80,7 +81,7 @@ VARIABLE
 	ST_CLUT						:NODE;
 	FB_B[3..0]					:NODE;
 	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE[2..0]			:DFFE;
 	ST_SHIFT_MODE_CS			:NODE;
 	FALCON_SHIFT_MODE[10..0]	:DFFE;
 	FALCON_SHIFT_MODE_CS		:NODE;
@@ -105,20 +106,19 @@ VARIABLE
 	HSYNC_START					:DFF;
 	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
 	VSYNC						:DFF;
-	VSYNC_START					:DFFE;
-	VSYNC_I[2..0]				:DFFE;
+	VSYNC_I[2..0]				:DFF;
 	nBLANK						:DFF;
 	DISP_ON						:DFF;
-	DPO_ZL						:DFFE;
+	DPO_ZL						:DFF;
 	DPO_ON						:DFF;
 	DPO_OFF						:DFF;
 	VDTRON						:DFF;
-	VDO_ZL						:DFFE;
+	VDO_ZL						:DFF;
 	VDO_ON						:DFF;
 	VDO_OFF						:DFF;
-	VHCNT[11..0]				:DFF;
+	VHCNT[12..0]				:DFF;
 	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[10..0]				:DFFE;
+	VVCNT[12..0]				:DFFE;
 	VERZ[2..0][9..0]			:DFF;
 	RAND[6..0]					:DFF;
 	RAND_ON						:NODE;
@@ -130,67 +130,63 @@ VARIABLE
 	SYNC_PIX2					:DFF;
 	CCSEL[2..0]					:DFF;
 	COLOR16						:NODE;
-	COLOR24						:NODE;
--- ATARI RESOLUTION
-	ATARI_SYNC					:NODE;	 
-	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
-	ATARI_HH_CS					:NODE;
-	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
-	ATARI_VH_CS					:NODE;
-	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
-	ATARI_HL_CS					:NODE;
-	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
-	ATARI_VL_CS					:NODE;
+	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
+	TE							:NODE;
 -- HORIZONTAL
-	RAND_LINKS[11..0]			:NODE;
-	HDIS_START[11..0]			:NODE;
-	HDIS_END[11..0]				:NODE;  
-	RAND_RECHTS[11..0]			:NODE;
-	HS_START[11..0]				:NODE;
-	H_TOTAL[11..0]				:NODE;
-	HDIS_LEN[11..0]				:NODE;
-	MULF[5..0]					:NODE;
-	VDL_HHT[11..0]				:DFFE;
+	RAND_LINKS[12..0]			:NODE;
+	HDIS_START[12..0]			:NODE;
+	STARTP[12..0]				:NODE; 
+	HDIS_END[12..0]				:NODE;  
+	RAND_RECHTS[12..0]			:NODE;
+	MULF[12..0]					:NODE;
+	HS_START[12..0]				:NODE;
+	H_TOTAL[12..0]				:NODE;
+	HDIS_LEN[12..0]				:NODE;
+	WPL[15..0]					:NODE;
+	VDL_HHT[12..0]				:DFFE;
 	VDL_HHT_CS					:NODE;
-	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE[12..0]				:DFFE;
 	VDL_HBE_CS					:NODE;
-	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB[12..0]				:DFFE;
 	VDL_HDB_CS					:NODE;
-	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE[12..0]				:DFFE;
 	VDL_HDE_CS					:NODE;
-	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB[12..0]				:DFFE;
 	VDL_HBB_CS					:NODE;
-	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS[12..0]				:DFFE;
 	VDL_HSS_CS					:NODE;
 -- VERTIKAL
-	RAND_OBEN[10..0]			:NODE; 
-	VDIS_START[10..0]			:NODE; 
-	VDIS_END[10..0]				:NODE; 
-	RAND_UNTEN[10..0]			:NODE; 
-	VS_START[10..0]				:NODE; 
-	V_TOTAL[10..0]				:NODE;  
+	RAND_OBEN[12..0]			:NODE; 
+	VDIS_START[12..0]			:NODE; 
+	VDIS_END[12..0]				:NODE; 
+	RAND_UNTEN[12..0]			:NODE; 
+	VS_START[12..0]				:NODE; 
+	V_TOTAL[12..0]				:NODE;  
 	FALCON_VIDEO				:NODE;
 	ST_VIDEO					:NODE;
 	INTER_ZEI					:DFF;
-	DOP_ZEI						:DFF;
 	DOP_FIFO_CLR				:DFF;
 	
-	VDL_VBE[10..0]				:DFFE;
+	VIDEL_CS					:NODE;
+	VDL_VBE[12..0]				:DFFE;
 	VDL_VBE_CS					:NODE;
-	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB[12..0]				:DFFE;
 	VDL_VDB_CS					:NODE;
-	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE[12..0]				:DFFE;
 	VDL_VDE_CS					:NODE;
-	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB[12..0]				:DFFE;
 	VDL_VBB_CS					:NODE;
-	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS[12..0]				:DFFE;
 	VDL_VSS_CS					:NODE;
-	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT[12..0]				:DFFE;
 	VDL_VFT_CS					:NODE;
-	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT[12..0]				:DFFE;
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+	VDL_BPP_CS					:NODE;
+	VDL_PH_CS					:NODE;
+	VDL_PV_CS					:NODE;
 
 BEGIN
 -- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
 	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
 	FB_16B1 = FB_ADR[0]==1									-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- VIDEL CS
+	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
 -- ACP CLUT --
 	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
 -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
 	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[] = FB_AD[26..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
 -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
 	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
 	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-	-- HORIZONTAL TIMING 640x480
-	ATARI_HH[].CLK = MAIN_CLK;
-	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
-	ATARI_HH[] = FB_AD[];
-	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
-	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
-	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
-	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
-	ATARI_VH[].CLK = MAIN_CLK;
-	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
-	ATARI_VH[] = FB_AD[];
-	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
-	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
-	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
-	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
-	ATARI_HL[].CLK = MAIN_CLK;
-	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
-	ATARI_HL[] = FB_AD[];
-	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
-	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
-	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
-	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
-	ATARI_VL[].CLK = MAIN_CLK;
-	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
-	ATARI_VL[] = FB_AD[];
-	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
-	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
-	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
-	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
 -- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
 	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
 -- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
 ------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
 -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
 	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
 	FALCON_VIDEO	   = ACP_VCTR7;
+	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_VIDEO		   = ACP_VCTR6;
-	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
 	CCSEL[].CLK = PIXEL_CLK;
 	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
 			# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
 -- DIVERSE (VIDEO)-REGISTER ----------------------------
 -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
 --SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
 	BLITTER_ON = SYS_CTR3;
 --VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
 --VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- DATEN AUFL<46>SUNG
+	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
+	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
+	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
 -- HORIZONTAL
 -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[27..16];
-	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[] = FB_AD[28..16];
+	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
 -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[27..16];
-	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[] = FB_AD[28..16];
+	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
 -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[27..16];
-	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[] = FB_AD[28..16];
+	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
 -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[27..16];
-	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[] = FB_AD[28..16];
+	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
 -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[27..16];
-	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[] = FB_AD[28..16];
+	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
 -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[27..16];
-	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[] = FB_AD[28..16];
+	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
 -- VERTIKAL
 -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[26..16];
-	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[] = FB_AD[28..16];
+	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
 -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[26..16];
-	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[] = FB_AD[28..16];
+	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
 -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[26..16];
-	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[] = FB_AD[28..16];
+	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
 -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[26..16];
-	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[] = FB_AD[28..16];
+	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
 -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[26..16];
-	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[] = FB_AD[28..16];
+	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
 -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[26..16];
-	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[] = FB_AD[28..16];
+	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
 -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[24..16];
-	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[] = FB_AD[28..16];
+	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
 -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS & VDL_LOF[]
-					  # VDL_LWD_CS & VDL_LWD[]
-					  #	VDL_HBE_CS & (0,VDL_HBE[])
-					  #	VDL_HDB_CS & (0,VDL_HDB[])
-					  #	VDL_HDE_CS & (0,VDL_HDE[])
-					  #	VDL_HBB_CS & (0,VDL_HBB[])
-					  #	VDL_HSS_CS & (0,VDL_HSS[])
-					  #	VDL_HHT_CS & (0,VDL_HHT[])
-					  #	VDL_VBE_CS & (0,VDL_VBE[])
-					  #	VDL_VDB_CS & (0,VDL_VDB[])
-					  #	VDL_VDE_CS & (0,VDL_VDE[])
-					  #	VDL_VBB_CS & (0,VDL_VBB[])
-					  #	VDL_VSS_CS & (0,VDL_VSS[])
-					  #	VDL_VFT_CS & (0,VDL_VFT[])
-					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS & (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
- 					  #	ATARI_HH_CS & ATARI_HH[31..16]
-					  #	ATARI_VH_CS & ATARI_VH[31..16]
-					  #	ATARI_HL_CS & ATARI_HL[31..16]
-					  #	ATARI_VL_CS & ATARI_VL[31..16]
-					  #	CCR_CS & (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
-					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
-					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
-					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
-
+					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS 				& VDL_LOF[]
+					  # VDL_LWD_CS 				& WPL[]
+					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
+					  # VDL_PH_CS  				& (0,HDIS_LEN[])
+					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
+					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
+					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
+					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
+					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
+					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
+					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
+					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
+					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
+					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
+					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
+					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
+					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
+					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
+ 					  #	CCR_CS 					& (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
  	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
-					  #	ATARI_HH_CS & ATARI_HH[15..0]
-					  #	ATARI_VH_CS & ATARI_VH[15..0]
-					  #	ATARI_HL_CS & ATARI_HL[15..0]
-					  #	ATARI_VL_CS & ATARI_VL[15..0]
- 					  #	CCR_CS & CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
-
-	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
-			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
-				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
-				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-	
--- VIDEO AUSGABE SETZEN
+ 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
+ 					  #	CCR_CS 					& CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
+	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
+-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
 	CLK17M.CLK = CLK33M;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
-	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
-			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
-----------------------------------------------------------------
+	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
+	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9];
+-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK -----------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
-			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
-
- 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
-			# 4  & !ST_VIDEO & !VDL_VMD2
-			# 16 &  ST_VIDEO &  VDL_VMD2
-			# 32 &  ST_VIDEO & !VDL_VMD2;
-	 	
-	 	
-	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
-			   #  640 & !VDL_VMD2;
-					
--- DOPPELZEILENMODUS
-	DOP_ZEI.CLK = MAIN_CLK;
-	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
+-- MULTIPLIKATIONS FAKTOR ----------------------------------------
+ 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
+			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
+			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
+			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
+			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
+ -- BREITE IN PIXELN ------------------------------------------------	 	
+	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
+			   #  640 & !TE							& !ACP_VIDEO_ON
+			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
+	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
+-- DOPPELZEILENMODUS ---------------------------------------------
 	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
-					
-	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
-					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
-	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
-					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
-	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-					
-	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
-					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
-					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
-					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
-					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
-					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
-					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
-	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
-	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- Z<>HLER
+	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER UNGERADEN ZEILEN
+	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN F<>R DOP.ZEI.FIFO
+-- TIMING HORIZONTAL				
+	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
+	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
+					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
+	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
+					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
+					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
+	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
+					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2 + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
+	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2 + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
+-- TIMING VERTICAL 					
+	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+-- Z<>HLER ---------------------------------------------------------------------------
 	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[]-2);
+	LAST = VHCNT[]==(H_TOTAL[] - 1);
 	VHCNT[].CLK = PIXEL_CLK;
 	VHCNT[] = (VHCNT[] + 1) & !LAST;
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
 -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
 	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
 -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
-	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
 -- VERZ<52>GERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_START = VHCNT[]==HS_START[] - 2;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
-	VSYNC_START.ENA = LAST;
-	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
-	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
+	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
+	VSYNC_I[].CLK = PIXEL_CLK;
 	VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
 	VERZ[0][0] = DISP_ON;
---	VERZ[1][0] = HSYNC_I[]!=0;
-	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
-	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
+				# VDL_VCT6 & HSYNC_I[]==0;	
+	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
+				# VDL_VCT5 & VSYNC_I[]==0;	
 	nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
 	HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
 ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
+	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE L<>SCHEN (GENUG FR<46>H DAMIT ES GEF<45>LLT WERDEN KANN BIS ZUR NEUEN <20>BERTRAGUNG) 
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
 	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;

FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak

@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
 	VR_WR : OUTPUT;
 	VR_RD : OUTPUT;
 	CLR_FIFO : OUTPUT;
+	DPZF_CLKENA: OUTPUT;
 	FB_AD[31..0] : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
@@ -80,7 +81,7 @@ VARIABLE
 	ST_CLUT						:NODE;
 	FB_B[3..0]					:NODE;
 	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE[2..0]			:DFFE;
 	ST_SHIFT_MODE_CS			:NODE;
 	FALCON_SHIFT_MODE[10..0]	:DFFE;
 	FALCON_SHIFT_MODE_CS		:NODE;
@@ -105,20 +106,19 @@ VARIABLE
 	HSYNC_START					:DFF;
 	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
 	VSYNC						:DFF;
-	VSYNC_START					:DFFE;
-	VSYNC_I[2..0]				:DFFE;
+	VSYNC_I[2..0]				:DFF;
 	nBLANK						:DFF;
 	DISP_ON						:DFF;
-	DPO_ZL						:DFFE;
+	DPO_ZL						:DFF;
 	DPO_ON						:DFF;
 	DPO_OFF						:DFF;
 	VDTRON						:DFF;
-	VDO_ZL						:DFFE;
+	VDO_ZL						:DFF;
 	VDO_ON						:DFF;
 	VDO_OFF						:DFF;
-	VHCNT[11..0]				:DFF;
+	VHCNT[12..0]				:DFF;
 	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[10..0]				:DFFE;
+	VVCNT[12..0]				:DFFE;
 	VERZ[2..0][9..0]			:DFF;
 	RAND[6..0]					:DFF;
 	RAND_ON						:NODE;
@@ -130,67 +130,63 @@ VARIABLE
 	SYNC_PIX2					:DFF;
 	CCSEL[2..0]					:DFF;
 	COLOR16						:NODE;
-	COLOR24						:NODE;
--- ATARI RESOLUTION
-	ATARI_SYNC					:NODE;	 
-	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
-	ATARI_HH_CS					:NODE;
-	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
-	ATARI_VH_CS					:NODE;
-	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
-	ATARI_HL_CS					:NODE;
-	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
-	ATARI_VL_CS					:NODE;
+	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
+	TE							:NODE;
 -- HORIZONTAL
-	RAND_LINKS[11..0]			:NODE;
-	HDIS_START[11..0]			:NODE;
-	HDIS_END[11..0]				:NODE;  
-	RAND_RECHTS[11..0]			:NODE;
-	HS_START[11..0]				:NODE;
-	H_TOTAL[11..0]				:NODE;
-	HDIS_LEN[11..0]				:NODE;
-	MULF[5..0]					:NODE;
-	VDL_HHT[11..0]				:DFFE;
+	RAND_LINKS[12..0]			:NODE;
+	HDIS_START[12..0]			:NODE;
+	STARTP[12..0]				:NODE; 
+	HDIS_END[12..0]				:NODE;  
+	RAND_RECHTS[12..0]			:NODE;
+	MULF[12..0]					:NODE;
+	HS_START[12..0]				:NODE;
+	H_TOTAL[12..0]				:NODE;
+	HDIS_LEN[12..0]				:NODE;
+	WPL[15..0]					:NODE;
+	VDL_HHT[12..0]				:DFFE;
 	VDL_HHT_CS					:NODE;
-	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE[12..0]				:DFFE;
 	VDL_HBE_CS					:NODE;
-	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB[12..0]				:DFFE;
 	VDL_HDB_CS					:NODE;
-	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE[12..0]				:DFFE;
 	VDL_HDE_CS					:NODE;
-	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB[12..0]				:DFFE;
 	VDL_HBB_CS					:NODE;
-	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS[12..0]				:DFFE;
 	VDL_HSS_CS					:NODE;
 -- VERTIKAL
-	RAND_OBEN[10..0]			:NODE; 
-	VDIS_START[10..0]			:NODE; 
-	VDIS_END[10..0]				:NODE; 
-	RAND_UNTEN[10..0]			:NODE; 
-	VS_START[10..0]				:NODE; 
-	V_TOTAL[10..0]				:NODE;  
+	RAND_OBEN[12..0]			:NODE; 
+	VDIS_START[12..0]			:NODE; 
+	VDIS_END[12..0]				:NODE; 
+	RAND_UNTEN[12..0]			:NODE; 
+	VS_START[12..0]				:NODE; 
+	V_TOTAL[12..0]				:NODE;  
 	FALCON_VIDEO				:NODE;
 	ST_VIDEO					:NODE;
 	INTER_ZEI					:DFF;
-	DOP_ZEI						:DFF;
 	DOP_FIFO_CLR				:DFF;
 	
-	VDL_VBE[10..0]				:DFFE;
+	VIDEL_CS					:NODE;
+	VDL_VBE[12..0]				:DFFE;
 	VDL_VBE_CS					:NODE;
-	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB[12..0]				:DFFE;
 	VDL_VDB_CS					:NODE;
-	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE[12..0]				:DFFE;
 	VDL_VDE_CS					:NODE;
-	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB[12..0]				:DFFE;
 	VDL_VBB_CS					:NODE;
-	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS[12..0]				:DFFE;
 	VDL_VSS_CS					:NODE;
-	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT[12..0]				:DFFE;
 	VDL_VFT_CS					:NODE;
-	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT[12..0]				:DFFE;
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+	VDL_BPP_CS					:NODE;
+	VDL_PH_CS					:NODE;
+	VDL_PV_CS					:NODE;
 
 BEGIN
 -- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
 	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
 	FB_16B1 = FB_ADR[0]==1									-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- VIDEL CS
+	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
 -- ACP CLUT --
 	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
 -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
 	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[] = FB_AD[26..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
 -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
 	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
 	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-	-- HORIZONTAL TIMING 640x480
-	ATARI_HH[].CLK = MAIN_CLK;
-	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
-	ATARI_HH[] = FB_AD[];
-	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
-	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
-	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
-	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
-	ATARI_VH[].CLK = MAIN_CLK;
-	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
-	ATARI_VH[] = FB_AD[];
-	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
-	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
-	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
-	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
-	ATARI_HL[].CLK = MAIN_CLK;
-	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
-	ATARI_HL[] = FB_AD[];
-	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
-	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
-	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
-	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
-	ATARI_VL[].CLK = MAIN_CLK;
-	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
-	ATARI_VL[] = FB_AD[];
-	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
-	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
-	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
-	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
 -- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
 	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
 -- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
 ------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
 -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
 	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
 	FALCON_VIDEO	   = ACP_VCTR7;
+	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_VIDEO		   = ACP_VCTR6;
-	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
 	CCSEL[].CLK = PIXEL_CLK;
 	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
 			# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
 -- DIVERSE (VIDEO)-REGISTER ----------------------------
 -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
 --SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
-	BLITTER_ON = !SYS_CTR3;
+	BLITTER_ON = SYS_CTR3;
 --VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
 --VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- DATEN AUFL<46>SUNG
+	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
+	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
+	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
 -- HORIZONTAL
 -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[27..16];
-	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[] = FB_AD[28..16];
+	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
 -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[27..16];
-	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[] = FB_AD[28..16];
+	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
 -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[27..16];
-	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[] = FB_AD[28..16];
+	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
 -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[27..16];
-	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[] = FB_AD[28..16];
+	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
 -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[27..16];
-	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[] = FB_AD[28..16];
+	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
 -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[27..16];
-	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[] = FB_AD[28..16];
+	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
 -- VERTIKAL
 -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[26..16];
-	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[] = FB_AD[28..16];
+	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
 -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[26..16];
-	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[] = FB_AD[28..16];
+	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
 -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[26..16];
-	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[] = FB_AD[28..16];
+	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
 -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[26..16];
-	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[] = FB_AD[28..16];
+	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
 -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[26..16];
-	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[] = FB_AD[28..16];
+	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
 -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[26..16];
-	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[] = FB_AD[28..16];
+	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
 -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[24..16];
-	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[] = FB_AD[28..16];
+	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
 -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS & VDL_LOF[]
-					  # VDL_LWD_CS & VDL_LWD[]
-					  #	VDL_HBE_CS & (0,VDL_HBE[])
-					  #	VDL_HDB_CS & (0,VDL_HDB[])
-					  #	VDL_HDE_CS & (0,VDL_HDE[])
-					  #	VDL_HBB_CS & (0,VDL_HBB[])
-					  #	VDL_HSS_CS & (0,VDL_HSS[])
-					  #	VDL_HHT_CS & (0,VDL_HHT[])
-					  #	VDL_VBE_CS & (0,VDL_VBE[])
-					  #	VDL_VDB_CS & (0,VDL_VDB[])
-					  #	VDL_VDE_CS & (0,VDL_VDE[])
-					  #	VDL_VBB_CS & (0,VDL_VBB[])
-					  #	VDL_VSS_CS & (0,VDL_VSS[])
-					  #	VDL_VFT_CS & (0,VDL_VFT[])
-					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS & (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
- 					  #	ATARI_HH_CS & ATARI_HH[31..16]
-					  #	ATARI_VH_CS & ATARI_VH[31..16]
-					  #	ATARI_HL_CS & ATARI_HL[31..16]
-					  #	ATARI_VL_CS & ATARI_VL[31..16]
-					  #	CCR_CS & (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
-					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
-					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
-					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
-
+					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS 				& VDL_LOF[]
+					  # VDL_LWD_CS 				& WPL[]
+					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
+					  # VDL_PH_CS  				& (0,HDIS_LEN[])
+					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
+					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
+					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
+					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
+					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
+					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
+					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
+					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
+					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
+					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
+					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
+					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
+					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
+					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
+ 					  #	CCR_CS 					& (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
  	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
-					  #	ATARI_HH_CS & ATARI_HH[15..0]
-					  #	ATARI_VH_CS & ATARI_VH[15..0]
-					  #	ATARI_HL_CS & ATARI_HL[15..0]
-					  #	ATARI_VL_CS & ATARI_VL[15..0]
- 					  #	CCR_CS & CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
-
-	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
-			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
-				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
-				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-	
--- VIDEO AUSGABE SETZEN
+ 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
+ 					  #	CCR_CS 					& CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
+	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
+-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
 	CLK17M.CLK = CLK33M;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
-	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
-			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
-----------------------------------------------------------------
+	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
+	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9];
+-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK -----------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
-			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
-
- 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
-			# 4  & !ST_VIDEO & !VDL_VMD2
-			# 16 &  ST_VIDEO &  VDL_VMD2
-			# 32 &  ST_VIDEO & !VDL_VMD2;
-	 	
-	 	
-	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
-			   #  640 & !VDL_VMD2;
-					
--- DOPPELZEILENMODUS
-	DOP_ZEI.CLK = MAIN_CLK;
-	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
+-- MULTIPLIKATIONS FAKTOR ----------------------------------------
+ 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
+			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
+			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
+			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
+			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
+ -- BREITE IN PIXELN ------------------------------------------------	 	
+	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
+			   #  640 & !TE							& !ACP_VIDEO_ON
+			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
+	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
+-- DOPPELZEILENMODUS ---------------------------------------------
 	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
-					
-	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
-					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
-	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
-					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
-	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-					
-	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
-					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
-					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
-					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
-					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
-					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
-					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
-	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
-	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- Z<>HLER
+	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER UNGERADEN ZEILEN
+	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN F<>R DOP.ZEI.FIFO
+-- TIMING HORIZONTAL				
+	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
+	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
+					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
+	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
+					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
+					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
+	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
+					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
+	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
+-- TIMING VERTICAL 					
+	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+-- Z<>HLER ---------------------------------------------------------------------------
 	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[]-2);
+	LAST = VHCNT[]==(H_TOTAL[] - 1);
 	VHCNT[].CLK = PIXEL_CLK;
 	VHCNT[] = (VHCNT[] + 1) & !LAST;
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
 -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
 	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
 -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE <20>BERNEHMEN
-	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
 -- VERZ<52>GERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_START = VHCNT[]==HS_START[] - 2;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
-	VSYNC_START.ENA = LAST;
-	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
-	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterz<72>hlen bis 0
+	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
+	VSYNC_I[].CLK = PIXEL_CLK;
 	VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
 	VERZ[0][0] = DISP_ON;
---	VERZ[1][0] = HSYNC_I[]!=0;
-	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
-	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR M<>GLICH WENN BEIDE
+	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
+				# VDL_VCT6 & HSYNC_I[]==0;	
+	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
+				# VDL_VCT5 & VSYNC_I[]==0;	
 	nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
 	HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
 ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE L<>SCHEN
+	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE L<>SCHEN (GENUG FR<46>H DAMIT ES GEF<45>LLT WERDEN KANN BIS ZUR NEUEN <20>BERTRAGUNG) 
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
 	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL Z<>HLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;

FPGA_by_Fredi/Video/Video.bdf

@@ -6594,64 +6594,6 @@ applicable agreement for further details.
 		(line (pt 80 296)(pt 96 288)(line_width 1))
 	)
 )
-(symbol
-	(rect 2072 1176 2232 1320)
-	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
-	(text "inst63" (rect 8 128 37 140)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
-		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 16 56)(line_width 1))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
-		(text "rdreq" (rect 20 66 50 80)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 16 72)(line_width 1))
-	)
-	(port
-		(pt 0 96)
-		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 90 55 104)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 16 96)(line_width 1))
-	)
-	(port
-		(pt 0 120)
-		(input)
-		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 16 120)(line_width 1))
-	)
-	(port
-		(pt 160 32)
-		(output)
-		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
-		(line (pt 160 32)(pt 144 32)(line_width 3))
-	)
-	(drawing
-		(text "(ack)" (rect 51 67 75 79)(font "Arial" ))
-		(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
-		(line (pt 16 16)(pt 144 16)(line_width 1))
-		(line (pt 144 16)(pt 144 128)(line_width 1))
-		(line (pt 144 128)(pt 16 128)(line_width 1))
-		(line (pt 16 128)(pt 16 16)(line_width 1))
-		(line (pt 16 108)(pt 144 108)(line_width 1))
-		(line (pt 16 90)(pt 22 96)(line_width 1))
-		(line (pt 22 96)(pt 16 102)(line_width 1))
-	)
-)
 (symbol
 	(rect 1712 1328 1872 1496)
 	(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
@@ -6726,253 +6668,144 @@ applicable agreement for further details.
 		(line (pt 22 120)(pt 16 126)(line_width 1))
 	)
 )
-(block
-	(rect 1664 1664 2016 2600)
-	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" ))	(block_io "nRSTO" (input))
-	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "nFB_CS3" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "nFB_BURST" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "CLK33M" (input))
-	(block_io "CLK25M" (input))
-	(block_io "BLITTER_RUN" (input))
-	(block_io "CLK_VIDEO" (input))
-	(block_io "VR_D[8..0]" (input))
-	(block_io "VR_BUSY" (input))
-	(block_io "COLOR8" (output))
-	(block_io "ACP_CLUT_RD" (output))
-	(block_io "COLOR1" (output))
-	(block_io "FALCON_CLUT_RDH" (output))
-	(block_io "FALCON_CLUT_RDL" (output))
-	(block_io "FALCON_CLUT_WR[3..0]" (output))
-	(block_io "ST_CLUT_RD" (output))
-	(block_io "ST_CLUT_WR[1..0]" (output))
-	(block_io "CLUT_MUX_ADR[3..0]" (output))
-	(block_io "HSYNC" (output))
-	(block_io "VSYNC" (output))
-	(block_io "nBLANK" (output))
-	(block_io "nSYNC" (output))
-	(block_io "nPD_VGA" (output))
-	(block_io "FIFO_RDE" (output))
-	(block_io "COLOR2" (output))
-	(block_io "COLOR4" (output))
-	(block_io "PIXEL_CLK" (output))
-	(block_io "CLUT_OFF[3..0]" (output))
-	(block_io "BLITTER_ON" (output))
-	(block_io "VIDEO_RAM_CTR[15..0]" (output))
-	(block_io "VIDEO_MOD_TA" (output))
-	(block_io "CCR[23..0]" (output))
-	(block_io "CCSEL[2..0]" (output))
-	(block_io "ACP_CLUT_WR[3..0]" (output))
-	(block_io "INTER_ZEI" (output))
-	(block_io "DOP_FIFO_CLR" (output))
-	(block_io "VIDEO_RECONFIG" (output))
-	(block_io "VR_WR" (output))
-	(block_io "VR_RD" (output))
-	(block_io "CLR_FIFO" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(mapper
-		(pt 352 72)
-		(bidir)
-		)
-	(mapper
-		(pt 0 272)
-		(bidir)
-		)
-	(mapper
+(symbol
+	(rect 1656 1216 1720 1296)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst101" (rect 3 68 38 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(line (pt 0 24)(pt 12 24)(line_width 1))
+	)
+	(port
+		(pt 32 0)
+		(input)
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
+		(line (pt 32 4)(pt 32 0)(line_width 1))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(line (pt 52 24)(pt 64 24)(line_width 1))
+	)
+	(drawing
+		(line (pt 12 12)(pt 52 12)(line_width 1))
+		(line (pt 12 68)(pt 52 68)(line_width 1))
+		(line (pt 52 68)(pt 52 12)(line_width 1))
+		(line (pt 12 68)(pt 12 12)(line_width 1))
+		(line (pt 19 40)(pt 12 47)(line_width 1))
+		(line (pt 12 32)(pt 20 40)(line_width 1))
+		(circle (rect 28 4 36 12)(line_width 1))
+		(circle (rect 28 68 36 76)(line_width 1))
+	)
+)
+(symbol
+	(rect 2072 1176 2232 1320)
+	(text "Doppelzeilen_Fifo" (rect 29 1 149 17)(font "Arial" (font_size 10)))
+	(text "inst98" (rect 8 128 37 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
 		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 248)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 520)
-		(bidir)
-		)
-	(mapper
-		(pt 0 544)
-		(bidir)
-		)
-	(mapper
-		(pt 0 880)
-		(bidir)
-		)
-	(mapper
-		(pt 352 600)
-		(bidir)
-		)
-	(mapper
-		(pt 352 624)
-		(bidir)
-		)
-	(mapper
-		(pt 352 648)
-		(bidir)
-		)
-	(mapper
-		(pt 352 672)
-		(bidir)
-		)
-	(mapper
-		(pt 352 696)
-		(bidir)
-		)
-	(mapper
-		(pt 352 720)
-		(bidir)
-		)
-	(mapper
-		(pt 352 840)
-		(bidir)
-		)
-	(mapper
-		(pt 352 472)
-		(bidir)
-		)
-	(mapper
-		(pt 352 448)
-		(bidir)
-		)
-	(mapper
-		(pt 352 528)
-		(bidir)
-		)
-	(mapper
-		(pt 352 320)
-		(bidir)
-		)
-	(mapper
-		(pt 352 576)
-		(bidir)
-		)
-	(mapper
-		(pt 352 400)
-		(bidir)
-		)
-	(mapper
-		(pt 352 376)
-		(bidir)
-		)
-	(mapper
-		(pt 352 352)
-		(bidir)
-		)
-	(mapper
-		(pt 352 504)
-		(bidir)
-		)
-	(mapper
-		(pt 352 296)
-		(bidir)
-		)
-	(mapper
-		(pt 352 424)
-		(bidir)
-		)
-	(mapper
-		(pt 352 552)
-		(bidir)
-		)
-	(mapper
-		(pt 352 752)
-		(bidir)
-		)
-	(mapper
-		(pt 352 776)
-		(bidir)
-		)
-	(mapper
-		(pt 352 872)
-		(bidir)
-		)
-	(mapper
-		(pt 0 496)
-		(bidir)
-		)
-	(mapper
-		(pt 352 88)
-		(bidir)
-		)
-	(mapper
-		(pt 352 264)
-		(bidir)
-		)
-	(mapper
-		(pt 352 248)
-		(bidir)
-		)
-	(mapper
-		(pt 352 232)
-		(bidir)
-		)
-	(mapper
-		(pt 352 216)
-		(bidir)
-		)
-	(mapper
-		(pt 352 136)
-		(bidir)
-		)
-	(mapper
-		(pt 352 40)
-		(bidir)
-		)
-	(mapper
-		(pt 352 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 472)
-		(bidir)
-		)
-	(mapper
-		(pt 0 456)
-		(bidir)
-		)
-	(mapper
-		(pt 352 104)
-		(bidir)
-		)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 66 50 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 90 55 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 128)(line_width 1))
+		(line (pt 144 128)(pt 16 128)(line_width 1))
+		(line (pt 16 128)(pt 16 16)(line_width 1))
+		(line (pt 16 108)(pt 144 108)(line_width 1))
+		(line (pt 16 90)(pt 22 96)(line_width 1))
+		(line (pt 22 96)(pt 16 102)(line_width 1))
+	)
+)
+(symbol
+	(rect 1856 1208 1920 1256)
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst99" (rect 3 37 32 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16)(line_width 1))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32)(line_width 1))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24)(line_width 1))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12)(line_width 1))
+		(line (pt 14 37)(pt 31 37)(line_width 1))
+		(line (pt 14 12)(pt 14 37)(line_width 1))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+	)
 )
 (block
 	(rect 296 1872 560 2536)
@@ -7300,6 +7133,259 @@ applicable agreement for further details.
 		(bidir)
 		)
 )
+(block
+	(rect 1664 1664 2016 2600)
+	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" ))	(block_io "nRSTO" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "CLK33M" (input))
+	(block_io "CLK25M" (input))
+	(block_io "BLITTER_RUN" (input))
+	(block_io "CLK_VIDEO" (input))
+	(block_io "VR_D[8..0]" (input))
+	(block_io "VR_BUSY" (input))
+	(block_io "COLOR8" (output))
+	(block_io "ACP_CLUT_RD" (output))
+	(block_io "COLOR1" (output))
+	(block_io "FALCON_CLUT_RDH" (output))
+	(block_io "FALCON_CLUT_RDL" (output))
+	(block_io "FALCON_CLUT_WR[3..0]" (output))
+	(block_io "ST_CLUT_RD" (output))
+	(block_io "ST_CLUT_WR[1..0]" (output))
+	(block_io "CLUT_MUX_ADR[3..0]" (output))
+	(block_io "HSYNC" (output))
+	(block_io "VSYNC" (output))
+	(block_io "nBLANK" (output))
+	(block_io "nSYNC" (output))
+	(block_io "nPD_VGA" (output))
+	(block_io "FIFO_RDE" (output))
+	(block_io "COLOR2" (output))
+	(block_io "COLOR4" (output))
+	(block_io "PIXEL_CLK" (output))
+	(block_io "CLUT_OFF[3..0]" (output))
+	(block_io "BLITTER_ON" (output))
+	(block_io "VIDEO_RAM_CTR[15..0]" (output))
+	(block_io "VIDEO_MOD_TA" (output))
+	(block_io "CCR[23..0]" (output))
+	(block_io "CCSEL[2..0]" (output))
+	(block_io "ACP_CLUT_WR[3..0]" (output))
+	(block_io "INTER_ZEI" (output))
+	(block_io "DOP_FIFO_CLR" (output))
+	(block_io "VIDEO_RECONFIG" (output))
+	(block_io "VR_WR" (output))
+	(block_io "VR_RD" (output))
+	(block_io "CLR_FIFO" (output))
+	(block_io "DPZF_CLKENA" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 352 72)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 544)
+		(bidir)
+		)
+	(mapper
+		(pt 0 880)
+		(bidir)
+		)
+	(mapper
+		(pt 352 600)
+		(bidir)
+		)
+	(mapper
+		(pt 352 624)
+		(bidir)
+		)
+	(mapper
+		(pt 352 648)
+		(bidir)
+		)
+	(mapper
+		(pt 352 672)
+		(bidir)
+		)
+	(mapper
+		(pt 352 696)
+		(bidir)
+		)
+	(mapper
+		(pt 352 720)
+		(bidir)
+		)
+	(mapper
+		(pt 352 840)
+		(bidir)
+		)
+	(mapper
+		(pt 352 472)
+		(bidir)
+		)
+	(mapper
+		(pt 352 448)
+		(bidir)
+		)
+	(mapper
+		(pt 352 528)
+		(bidir)
+		)
+	(mapper
+		(pt 352 320)
+		(bidir)
+		)
+	(mapper
+		(pt 352 576)
+		(bidir)
+		)
+	(mapper
+		(pt 352 400)
+		(bidir)
+		)
+	(mapper
+		(pt 352 376)
+		(bidir)
+		)
+	(mapper
+		(pt 352 352)
+		(bidir)
+		)
+	(mapper
+		(pt 352 504)
+		(bidir)
+		)
+	(mapper
+		(pt 352 296)
+		(bidir)
+		)
+	(mapper
+		(pt 352 424)
+		(bidir)
+		)
+	(mapper
+		(pt 352 552)
+		(bidir)
+		)
+	(mapper
+		(pt 352 752)
+		(bidir)
+		)
+	(mapper
+		(pt 352 776)
+		(bidir)
+		)
+	(mapper
+		(pt 352 872)
+		(bidir)
+		)
+	(mapper
+		(pt 0 496)
+		(bidir)
+		)
+	(mapper
+		(pt 352 88)
+		(bidir)
+		)
+	(mapper
+		(pt 352 264)
+		(bidir)
+		)
+	(mapper
+		(pt 352 248)
+		(bidir)
+		)
+	(mapper
+		(pt 352 232)
+		(bidir)
+		)
+	(mapper
+		(pt 352 216)
+		(bidir)
+		)
+	(mapper
+		(pt 352 136)
+		(bidir)
+		)
+	(mapper
+		(pt 352 40)
+		(bidir)
+		)
+	(mapper
+		(pt 352 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 472)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 352 104)
+		(bidir)
+		)
+	(mapper
+		(pt 352 800)
+		(bidir)
+		)
+)
 (connector
 	(text "CLUT_ADR0" (rect 2786 1272 2849 1284)(font "Arial" ))
 	(pt 2776 1288)
@@ -8629,11 +8715,6 @@ applicable agreement for further details.
 	(pt 2512 1568)
 	(pt 2512 1728)
 )
-(connector
-	(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
-	(pt 1640 1448)
-	(pt 1712 1448)
-)
 (connector
 	(text "PIXEL_CLK" (rect 1938 1424 1994 1436)(font "Arial" ))
 	(pt 1928 1440)
@@ -10289,22 +10370,6 @@ applicable agreement for further details.
 	(pt 1800 1160)
 	(bus)
 )
-(connector
-	(pt 1608 1432)
-	(pt 1608 1232)
-)
-(connector
-	(pt 1600 1432)
-	(pt 1608 1432)
-)
-(connector
-	(pt 1608 1432)
-	(pt 1712 1432)
-)
-(connector
-	(pt 1608 1232)
-	(pt 2072 1232)
-)
 (connector
 	(pt 2072 1248)
 	(pt 1944 1248)
@@ -10591,6 +10656,57 @@ applicable agreement for further details.
 	(pt 848 2744)
 	(pt 928 2744)
 )
+(connector
+	(pt 1920 1232)
+	(pt 2072 1232)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1608 1240)
+)
+(connector
+	(pt 1608 1240)
+	(pt 1656 1240)
+)
+(connector
+	(pt 1624 1256)
+	(pt 1656 1256)
+)
+(connector
+	(pt 1624 1448)
+	(pt 1624 1256)
+)
+(connector
+	(pt 1600 1432)
+	(pt 1608 1432)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1712 1432)
+)
+(connector
+	(pt 1608 1448)
+	(pt 1624 1448)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
+	(pt 1624 1448)
+	(pt 1712 1448)
+)
+(connector
+	(pt 1720 1240)
+	(pt 1856 1240)
+)
+(connector
+	(text "DPZF_CLKENA" (rect 1754 1208 1833 1220)(font "Arial" ))
+	(pt 1856 1224)
+	(pt 1744 1224)
+)
+(connector
+	(text "DPZF_CLKENA" (rect 2026 2448 2105 2460)(font "Arial" ))
+	(pt 2128 2464)
+	(pt 2016 2464)
+)
 (junction (pt 2984 1688))
 (junction (pt 792 1192))
 (junction (pt 792 1312))
@@ -10615,3 +10731,4 @@ applicable agreement for further details.
 (junction (pt 3232 3024))
 (junction (pt 1968 1424))
 (junction (pt 1608 1432))
+(junction (pt 1624 1448))

FPGA_by_Fredi/Video/altdpram0_waveforms.html

@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram0.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/altdpram1_waveforms.html

@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/altdpram2_waveforms.html

@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram2.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/lpm_compare1_waveforms.html

@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for lpm_compare1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
-<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
-<P><FONT size=3></P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html

@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd".  The design "lpm_fifoDZ.vhd" has a depth of 512 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
-<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html

@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd".  The design "lpm_fifo_dc0.vhd" has a depth of 2048 words of 128 bits each. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
-<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>

FPGA_by_Fredi/Video/shiftreg_dpz.bsf

@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "shiftreg_dpz" (rect 37 1 119 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)

FPGA_by_Fredi/Video/shiftreg_dpz.inc

@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION shiftreg_dpz 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);

FPGA_by_Fredi/Video/shiftreg_dpz.qip

@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
 set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "shiftreg_dpz.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.inc"]

FPGA_by_Fredi/Video/shiftreg_dpz.vhd

@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: shiftreg_dpz.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY shiftreg_dpz IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END shiftreg_dpz;
+
+
+ARCHITECTURE SYN OF shiftreg_dpz IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 3
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm