Sync with Fredi's source 22/06/2017
Blitter work.
This commit is contained in:
David Gálvez
@@ -184,10 +184,14 @@ signal TDO : STD_LOGIC;
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signal SNDCS : STD_LOGIC;
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signal SNDCS_I : STD_LOGIC;
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signal SNDIR_I : STD_LOGIC;
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signal LP_DIR_X : STD_LOGIC;
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signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0);
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signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0);
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signal nLP_STR : STD_LOGIC;
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signal LP_STR_X : STD_LOGIC;
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signal LP_STR_NS1 : STD_LOGIC;
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signal LP_STR_NS0 : STD_LOGIC;
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signal LP_DIR_X : STD_LOGIC;
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signal LP_DIR_NS1 : STD_LOGIC;
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signal LP_DIR_NS0 : STD_LOGIC;
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-- DMA SOUND
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signal dma_snd_cs : STD_LOGIC;
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signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
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@@ -298,8 +302,7 @@ FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
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FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
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or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_TA = '1' else '0'; --SNDCS = '1' or
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SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
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'1' when IDE_CF_CS = '1' ELSE
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'1' when nFB_CS3 = '0' ELSE '0';
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'1' when IDE_CF_CS = '1' ELSE '0'; -- DARF NICHT AKTIV SEIN BEI ZUGRIFF AUF DRIVE 0 UND 1 DA KOMMEN DIE DATEN DIREKT VOM FPGA
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nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1';
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nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1';
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@@ -325,6 +328,22 @@ SD_CDM_D1 <= 'Z';
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----------------------------------------------------------------------------
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-- IDE
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----------------------------------------------------------------------------
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IDE_RES <= not ACP_CONF(25) and nRSTO; -- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO
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IDE_CF_CS <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 7) = x"1E000" else '0'; -- FFF0'0000-FFF0'007F
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IDE_DRIVE0 <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F00099" else '0'; -- FFF0'0099 (19+80!)
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IDE_DRIVE1 <= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F000D9" else '0'; -- FFF0'00D9 (19+40+80!)
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IDE_DCS <= '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else -- FFF0'000x 0-3
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'1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0000" else -- FFF0'000x 0-3
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'1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else -- FFF0'004x 0-3
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'1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0010" else '0'; -- FFF0'004x 0-3
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nCF_CS0 <= FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx00-1F
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nCF_CS1 <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx20-3F
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nIDE_CS0 <= FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx40-5F
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nIDE_CS1 <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx60-7F
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nDREQ0 <= '1';
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FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
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FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
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CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
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begin
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if nRSTO = '0' then
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@@ -336,7 +355,7 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
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end if;
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end process CMD_REG;
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CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY)
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CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY,IDE_DCS, IDE_CF_CS, FB_ADR, ACP_CONF, nFB_WR, FB_SIZE0, FB_SIZE1)
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begin
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case CMD_STATE is
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when IDLE =>
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@@ -453,23 +472,6 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
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end if;
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end case;
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end process CMD_DECODER;
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IDE_RES <= not ACP_CONF(25) and nRSTO; -- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO
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IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000-FFF0'007F
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IDE_DRIVE0 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"99" else '0'; -- FFF0'0099 (19+80!)
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IDE_DRIVE1 <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"D9" else '0'; -- FFF0'00D9 (19+40+80!)
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IDE_DCS <= '1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else -- FFF0'000x 0-3
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'1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"0" else -- FFF0'000x 0-3
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'1' when FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else -- FFF0'004x 0-3
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'1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"10" else '0'; -- FFF0'004x 0-3
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nCF_CS0 <= FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx00-1F
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nCF_CS1 <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); -- xxxx'xx20-3F
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nIDE_CS0 <= FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx40-5F
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nIDE_CS1 <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); -- xxxx'xx60-7F
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nDREQ0 <= '1';
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FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
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FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
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-----------------------------------------------------------------------------------------------------------------------------------------
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-- ACSI, SCSI UND FLOPPY WD1772
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-------------------------------------------------------------------------------------------------------------------------------------------
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@@ -915,7 +917,7 @@ KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1'; -- TAST
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FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else
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DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
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-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
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process(CLK2M, AMKB_RX, AMKB_REG)
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process(CLK2M, AMKB_RX, AMKB_TX, AMKB_REG, CLK500k)
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begin
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if rising_edge(CLK500k) then
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AMKB_TX <= AMKB_TX_sync;
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@@ -995,7 +997,7 @@ MIDI_OLR <= MIDI_OUT;
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GPIP_IN(3) => BLITTER_INT OR DSP_INT,
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GPIP_IN(2) => not CTS,
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GPIP_IN(1) => not DCD,
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GPIP_IN(0) => LP_BUSY,
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GPIP_IN(0) => LP_BUSY XOR ACP_CONF(1),
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-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
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-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
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-- Interrupt control:
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@@ -1032,7 +1034,8 @@ FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
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DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
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'0' when FDINT = '1' else
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'0' when SCSI_INT = '1' AND ACP_CONF(27) = '1' else '1';
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----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Sound
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----------------------------------------------------------------------------
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I_SOUND: WF2149IP_TOP_SOC
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@@ -1054,8 +1057,8 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
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IO_A_IN => x"00", -- All port pins are dedicated outputs.
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IO_A_OUT(7) => nnIDE_RES,
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IO_A_OUT(6) => LP_DIR_X,
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IO_A_OUT(5) => nLP_STR,
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IO_A_OUT(6) => LP_DIR_NS0,
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IO_A_OUT(5) => LP_STR_NS0,
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IO_A_OUT(4) => DTR,
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IO_A_OUT(3) => RTS,
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-- IO_A_OUT(2) => FDD_D1SEL,
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@@ -1075,17 +1078,38 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; --
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SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
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SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
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FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
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LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
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LP_DIR <= LP_DIR_X;
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LP_STR <= not nLP_STR;
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LP_D <= LP_D_X when (LP_DIR_X = '0' OR ACP_CONF(2) = '0') else "ZZZZZZZZ";
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LP_STR <= LP_STR_X XOR ACP_CONF(0);
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LP_DIR <= LP_DIR_X XOR ACP_CONF(3);
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-- spikes weg ------------------------------------------
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process(CLK2M,LP_STR_NS1,LP_STR_NS0,LP_STR_X)
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begin
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if rising_edge(CLK2M) then
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LP_STR_X <= (LP_STR_NS1 AND LP_STR_NS0) OR (LP_STR_X AND LP_STR_NS1);
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LP_STR_NS1 <= LP_STR_NS0;
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else
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LP_STR_X <= LP_STR_X;
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LP_STR_NS1 <= LP_STR_NS1;
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end if;
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END PROCESS;
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process(CLK2M,LP_DIR_NS1,LP_DIR_NS0,LP_DIR_X)
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begin
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if rising_edge(CLK2M) then
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LP_DIR_X <= (LP_DIR_NS1 AND LP_DIR_NS0) OR (LP_DIR_X AND LP_DIR_NS1);
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LP_DIR_NS1 <= LP_DIR_NS0;
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else
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LP_DIR_X <= LP_DIR_X;
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LP_DIR_NS1 <= LP_DIR_NS1;
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end if;
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END PROCESS;
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----------------------------------------------------------------------------
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-- DMA Sound register
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----------------------------------------------------------------------------
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dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0'; -- F8900-F893F
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process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
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process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, nFB_WR, FB_B1, sndmactl)
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begin
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if nRSTO = '0' THEN
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sndmactl <= x"00";
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@@ -1097,7 +1121,7 @@ dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';
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END PROCESS;
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FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
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process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
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process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, sndbashi)
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begin
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if nRSTO = '0' THEN
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sndbashi <= x"00";
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@@ -1220,7 +1244,6 @@ FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"
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----------------------------------------------------------------------------
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-- Paddle
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----------------------------------------------------------------------------
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paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0'; -- F9200-F923F
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FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
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@@ -1232,4 +1255,5 @@ FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B
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FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
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FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
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--****************************************************************
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END FalconIO_SDCard_IDE_CF_architecture;
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@@ -1,202 +0,0 @@
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-- megafunction wizard: %LPM_FIFO+%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: dcfifo_mixed_widths
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-- ============================================================
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-- File Name: dcfifo1.vhd
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-- Megafunction Name(s):
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-- dcfifo_mixed_widths
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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||||
--
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||||
-- 9.1 Build 222 10/21/2009 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2009 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
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LIBRARY ieee;
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||||
USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY dcfifo1 IS
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PORT
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(
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aclr : IN STD_LOGIC := '0';
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data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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||||
rdclk : IN STD_LOGIC ;
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||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
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||||
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
|
||||
);
|
||||
END dcfifo1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dcfifo1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
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||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT dcfifo_mixed_widths
|
||||
GENERIC (
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||||
intended_device_family : STRING;
|
||||
lpm_numwords : NATURAL;
|
||||
lpm_showahead : STRING;
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL;
|
||||
lpm_widthu : NATURAL;
|
||||
lpm_widthu_r : NATURAL;
|
||||
lpm_width_r : NATURAL;
|
||||
overflow_checking : STRING;
|
||||
rdsync_delaypipe : NATURAL;
|
||||
underflow_checking : STRING;
|
||||
use_eab : STRING;
|
||||
write_aclr_synch : STRING;
|
||||
wrsync_delaypipe : NATURAL
|
||||
);
|
||||
PORT (
|
||||
wrclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
aclr : IN STD_LOGIC ;
|
||||
rdclk : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
wrreq : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
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||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
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||||
wrusedw <= sub_wire0(3 DOWNTO 0);
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||||
q <= sub_wire1(7 DOWNTO 0);
|
||||
|
||||
dcfifo_mixed_widths_component : dcfifo_mixed_widths
|
||||
GENERIC MAP (
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_numwords => 16,
|
||||
lpm_showahead => "OFF",
|
||||
lpm_type => "dcfifo",
|
||||
lpm_width => 16,
|
||||
lpm_widthu => 4,
|
||||
lpm_widthu_r => 5,
|
||||
lpm_width_r => 8,
|
||||
overflow_checking => "ON",
|
||||
rdsync_delaypipe => 5,
|
||||
underflow_checking => "ON",
|
||||
use_eab => "ON",
|
||||
write_aclr_synch => "OFF",
|
||||
wrsync_delaypipe => 5
|
||||
)
|
||||
PORT MAP (
|
||||
wrclk => wrclk,
|
||||
rdreq => rdreq,
|
||||
aclr => aclr,
|
||||
rdclk => rdclk,
|
||||
wrreq => wrreq,
|
||||
data => data,
|
||||
wrusedw => sub_wire0,
|
||||
q => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: Depth NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Width NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
|
||||
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
|
||||
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
Reference in New Issue
Block a user