add config from 30-11-2018
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ragnar
165
FPGA_30_11_2018/video_out_syn.v
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165
FPGA_30_11_2018/video_out_syn.v
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// megafunction wizard: %ALTDDIO_OUT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altddio_out
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// ============================================================
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// File Name: video_out.v
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// Megafunction Name(s):
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// altddio_out
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2010 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//altddio_out DEVICE_FAMILY="Cyclone III" INVERT_OUTPUT="OFF" POWER_UP_HIGH="OFF" WIDTH=1 datain_h datain_l dataout outclock
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//VERSION_BEGIN 9.1SP2 cbx_altddio_out 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = IO 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"ANALYZE_METASTABILITY=OFF"} *)
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module video_out_ddio_out
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(
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datain_h,
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datain_l,
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dataout,
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outclock) /* synthesis synthesis_clearbox=1 */;
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input [0:0] datain_h;
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input [0:0] datain_l;
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output [0:0] dataout;
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input outclock;
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wire [0:0] wire_ddio_outa_dataout;
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cycloneiii_ddio_out ddio_outa_0
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(
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.clkhi(outclock),
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.clklo(outclock),
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.datainhi(datain_h),
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.datainlo(datain_l),
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.dataout(wire_ddio_outa_dataout[0:0]),
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.muxsel(outclock)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.areset(1'b0),
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.clk(1'b0),
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.ena(1'b1),
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.sreset(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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// synopsys translate_off
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,
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.devclrn(1'b1),
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.devpor(1'b1),
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.dffhi(),
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.dfflo()
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// synopsys translate_on
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);
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defparam
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ddio_outa_0.async_mode = "none",
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ddio_outa_0.power_up = "low",
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ddio_outa_0.sync_mode = "none",
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ddio_outa_0.use_new_clocking_model = "true",
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ddio_outa_0.lpm_type = "cycloneiii_ddio_out";
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assign
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dataout = wire_ddio_outa_dataout;
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endmodule //video_out_ddio_out
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module video_out (
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datain_h,
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datain_l,
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outclock,
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dataout)/* synthesis synthesis_clearbox = 1 */;
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input datain_h;
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input datain_l;
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input outclock;
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output dataout;
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wire [0:0] sub_wire0;
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire dataout = sub_wire1;
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wire sub_wire2 = datain_h;
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wire sub_wire3 = sub_wire2;
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wire sub_wire4 = datain_l;
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wire sub_wire5 = sub_wire4;
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video_out_ddio_out video_out_ddio_out_component (
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.outclock (outclock),
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.datain_h (sub_wire3),
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.datain_l (sub_wire5),
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.dataout (sub_wire0));
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: OE NUMERIC "0"
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// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
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// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
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// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
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// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
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// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
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// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
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// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
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// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
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// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
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// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
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// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
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// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
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// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
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// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
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// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out.vhd TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out.ppf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out.inc TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out.cmp TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out.bsf TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out_inst.vhd FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL video_out_syn.v TRUE
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// Retrieval info: LIB_FILE: altera_mf
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