Firebee/FPGA_Config
1
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

reformat

Browse Source
This commit is contained in:
Markus Fröschle
2016-01-12 17:11:07 +00:00
parent f1f893bc44
commit 29df555945
1 changed files with 554 additions and 369 deletions
Download Patch File Download Diff File Expand all files Collapse all files

459
FPGA_Quartus_13.1/Video/video.vhd
View File

@@ -1216,78 +1216,110 @@ BEGIN
inst15 : lpm_ff0 inst15 : lpm_ff0
PORT MAP(clock => DDR_SYNC_66M, PORT MAP
(
clock => DDR_SYNC_66M,
enable => FB_LE(2), enable => FB_LE(2),
data => FB_AD, data => FB_AD,
q => FB_DDR(63 DOWNTO 32)); q => FB_DDR(63 DOWNTO 32)
);
inst16 : lpm_ff0 inst16 : lpm_ff0
PORT MAP(clock => DDR_SYNC_66M, PORT MAP
(
clock => DDR_SYNC_66M,
enable => FB_LE(3), enable => FB_LE(3),
data => FB_AD, data => FB_AD,
q => FB_DDR(31 DOWNTO 0)); q => FB_DDR(31 DOWNTO 0)
);
inst17 : lpm_ff0 inst17 : lpm_ff0
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => DDR_FB(1), enable => DDR_FB(1),
data => VDP_IN(31 DOWNTO 0), data => VDP_IN(31 DOWNTO 0),
q => SYNTHESIZED_WIRE_11); q => SYNTHESIZED_WIRE_11
);
inst18 : lpm_ff0 inst18 : lpm_ff0
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => DDR_FB(0), enable => DDR_FB(0),
data => VDP_IN(63 DOWNTO 32), data => VDP_IN(63 DOWNTO 32),
q => SYNTHESIZED_WIRE_13); q => SYNTHESIZED_WIRE_13
);
inst19 : lpm_ff0 inst19 : lpm_ff0
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => DDR_FB(0), enable => DDR_FB(0),
data => VDP_IN(31 DOWNTO 0), data => VDP_IN(31 DOWNTO 0),
q => SYNTHESIZED_WIRE_14); q => SYNTHESIZED_WIRE_14
);
inst2 : altddio_out0 inst2 : altddio_out0
PORT MAP(outclock => DDRCLK(3), PORT MAP
(
outclock => DDRCLK(3),
datain_h => VDMP(7 DOWNTO 4), datain_h => VDMP(7 DOWNTO 4),
datain_l => VDMP(3 DOWNTO 0), datain_l => VDMP(3 DOWNTO 0),
dataout => VDM); dataout => VDM
);
inst20 : lpm_ff1 inst20 : lpm_ff1
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
data => VDVZ(31 DOWNTO 0), data => VDVZ(31 DOWNTO 0),
q => VDVZ(95 DOWNTO 64)); q => VDVZ(95 DOWNTO 64)
);
inst21 : lpm_mux0 inst21 : lpm_mux0
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data0x => FIFO_D(127 DOWNTO 96), data0x => FIFO_D(127 DOWNTO 96),
data1x => FIFO_D(95 DOWNTO 64), data1x => FIFO_D(95 DOWNTO 64),
data2x => FIFO_D(63 DOWNTO 32), data2x => FIFO_D(63 DOWNTO 32),
data3x => FIFO_D(31 DOWNTO 0), data3x => FIFO_D(31 DOWNTO 0),
sel => CLUT_MUX_ADR(1 DOWNTO 0), sel => CLUT_MUX_ADR(1 DOWNTO 0),
result => SYNTHESIZED_WIRE_48); result => SYNTHESIZED_WIRE_48
);
inst22 : lpm_mux5 inst22 : lpm_mux5
PORT MAP(data0x => FB_DDR(127 DOWNTO 64), PORT MAP
(
data0x => FB_DDR(127 DOWNTO 64),
data1x => FB_DDR(63 DOWNTO 0), data1x => FB_DDR(63 DOWNTO 0),
data2x => BLITTER_DOUT(127 DOWNTO 64), data2x => BLITTER_DOUT(127 DOWNTO 64),
data3x => BLITTER_DOUT(63 DOWNTO 0), data3x => BLITTER_DOUT(63 DOWNTO 0),
sel => DDRWR_D_SEL, sel => DDRWR_D_SEL,
result => VDP_OUT); result => VDP_OUT
);
inst23 : lpm_constant2 inst23 : lpm_constant2
PORT MAP( result => GDFX_TEMP_SIGNAL_16); PORT MAP
(
result => GDFX_TEMP_SIGNAL_16
);
inst24 : lpm_mux1 inst24 : lpm_mux1
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data0x => FIFO_D(127 DOWNTO 112), data0x => FIFO_D(127 DOWNTO 112),
data1x => FIFO_D(111 DOWNTO 96), data1x => FIFO_D(111 DOWNTO 96),
data2x => FIFO_D(95 DOWNTO 80), data2x => FIFO_D(95 DOWNTO 80),
@@ -1297,11 +1329,14 @@ BEGIN
data6x => FIFO_D(31 DOWNTO 16), data6x => FIFO_D(31 DOWNTO 16),
data7x => FIFO_D(15 DOWNTO 0), data7x => FIFO_D(15 DOWNTO 0),
sel => CLUT_MUX_ADR(2 DOWNTO 0), sel => CLUT_MUX_ADR(2 DOWNTO 0),
result => SYNTHESIZED_WIRE_7); result => SYNTHESIZED_WIRE_7
);
inst25 : lpm_mux2 inst25 : lpm_mux2
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data0x => FIFO_D(127 DOWNTO 120), data0x => FIFO_D(127 DOWNTO 120),
data10x => FIFO_D(47 DOWNTO 40), data10x => FIFO_D(47 DOWNTO 40),
data11x => FIFO_D(39 DOWNTO 32), data11x => FIFO_D(39 DOWNTO 32),
@@ -1319,29 +1354,37 @@ BEGIN
data8x => FIFO_D(63 DOWNTO 56), data8x => FIFO_D(63 DOWNTO 56),
data9x => FIFO_D(55 DOWNTO 48), data9x => FIFO_D(55 DOWNTO 48),
sel => CLUT_MUX_ADR, sel => CLUT_MUX_ADR,
result => SYNTHESIZED_WIRE_12); result => SYNTHESIZED_WIRE_12
);
inst26 : lpm_shiftreg4 inst26 : lpm_shiftreg4
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
shiftin => SR_FIFO_WRE, shiftin => SR_FIFO_WRE,
shiftout => FIFO_WRE); shiftout => FIFO_WRE
);
inst27 : lpm_latch0 inst27 : lpm_latch0
PORT MAP(gate => DDR_SYNC_66M, PORT MAP
(
gate => DDR_SYNC_66M,
data => SYNTHESIZED_WIRE_15, data => SYNTHESIZED_WIRE_15,
q => VDR); q => VDR
);
CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16;
inst3 : lpm_ff1 inst3 : lpm_ff1
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
data => VDP_IN(63 DOWNTO 32), data => VDP_IN(63 DOWNTO 32),
q => VDVZ(63 DOWNTO 32)); q => VDVZ(63 DOWNTO 32)
);
CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A;
CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18;
@@ -1350,206 +1393,272 @@ BEGIN
SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8;
SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8;
inst36 : lpm_ff6 inst36 : lpm_ff6
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => BLITTER_DACK(0), enable => BLITTER_DACK(0),
data => VDVZ, data => VDVZ,
q => BLITTER_DIN); q => BLITTER_DIN
);
VDOUT_OE <= DDR_WR OR SR_DDR_WR; VDOUT_OE <= DDR_WR OR SR_DDR_WR;
VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA;
inst4 : lpm_ff1 inst4 : lpm_ff1
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
data => VDVZ(63 DOWNTO 32), data => VDVZ(63 DOWNTO 32),
q => VDVZ(127 DOWNTO 96)); q => VDVZ(127 DOWNTO 96)
);
inst40 : mux41_0 inst40 : mux41_0
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR6A, D0 => CLUT_ADR6A,
INH => SYNTHESIZED_WIRE_19, INH => SYNTHESIZED_WIRE_19,
D1 => CLUT_ADR7A, D1 => CLUT_ADR7A,
Q => SYNTHESIZED_WIRE_54); Q => SYNTHESIZED_WIRE_54
);
inst41 : mux41_1 inst41 : mux41_1
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR5A, D0 => CLUT_ADR5A,
INH => SYNTHESIZED_WIRE_20, INH => SYNTHESIZED_WIRE_20,
D1 => CLUT_ADR6A, D1 => CLUT_ADR6A,
Q => SYNTHESIZED_WIRE_53); Q => SYNTHESIZED_WIRE_53
);
inst42 : mux41_2 inst42 : mux41_2
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
D2 => CLUT_ADR7A, D2 => CLUT_ADR7A,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR4A, D0 => CLUT_ADR4A,
INH => SYNTHESIZED_WIRE_21, INH => SYNTHESIZED_WIRE_21,
D1 => CLUT_ADR5A, D1 => CLUT_ADR5A,
Q => SYNTHESIZED_WIRE_52); Q => SYNTHESIZED_WIRE_52
);
inst43 : mux41_3 inst43 : mux41_3
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
D2 => CLUT_ADR6A, D2 => CLUT_ADR6A,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR3A, D0 => CLUT_ADR3A,
INH => SYNTHESIZED_WIRE_22, INH => SYNTHESIZED_WIRE_22,
D1 => CLUT_ADR4A, D1 => CLUT_ADR4A,
Q => SYNTHESIZED_WIRE_51); Q => SYNTHESIZED_WIRE_51
);
inst44 : mux41_4 inst44 : mux41_4
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
D2 => CLUT_ADR5A, D2 => CLUT_ADR5A,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR2A, D0 => CLUT_ADR2A,
INH => SYNTHESIZED_WIRE_23, INH => SYNTHESIZED_WIRE_23,
D1 => CLUT_ADR3A, D1 => CLUT_ADR3A,
Q => SYNTHESIZED_WIRE_50); Q => SYNTHESIZED_WIRE_50
);
inst45 : mux41_5 inst45 : mux41_5
PORT MAP(S0 => COLOR2, PORT MAP
(
S0 => COLOR2,
D2 => CLUT_ADR4A, D2 => CLUT_ADR4A,
S1 => COLOR4, S1 => COLOR4,
D0 => CLUT_ADR1A, D0 => CLUT_ADR1A,
INH => SYNTHESIZED_WIRE_24, INH => SYNTHESIZED_WIRE_24,
D1 => CLUT_ADR2A, D1 => CLUT_ADR2A,
Q => SYNTHESIZED_WIRE_49); Q => SYNTHESIZED_WIRE_49
);
inst46 : lpm_ff3 inst46 : lpm_ff3
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => SYNTHESIZED_WIRE_25, data => SYNTHESIZED_WIRE_25,
q => SYNTHESIZED_WIRE_43); q => SYNTHESIZED_WIRE_43
);
inst47 : lpm_ff3 inst47 : lpm_ff3
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => CCF, data => CCF,
q => SYNTHESIZED_WIRE_25); q => SYNTHESIZED_WIRE_25
);
inst49 : lpm_ff3 inst49 : lpm_ff3
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => SYNTHESIZED_WIRE_26, data => SYNTHESIZED_WIRE_26,
q => SYNTHESIZED_WIRE_42); q => SYNTHESIZED_WIRE_42
);
inst5 : altddio_out2 inst5 : altddio_out2
PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
outclock => PIXEL_CLK_ALTERA_SYNTHESIZED,
datain_h => SYNTHESIZED_WIRE_62, datain_h => SYNTHESIZED_WIRE_62,
datain_l => SYNTHESIZED_WIRE_62, datain_l => SYNTHESIZED_WIRE_62,
dataout => SYNTHESIZED_WIRE_65); dataout => SYNTHESIZED_WIRE_65
);
inst51 : lpm_bustri1 inst51 : lpm_bustri1
PORT MAP(enabledt => ST_CLUT_RD, PORT MAP
(
enabledt => ST_CLUT_RD,
data => SYNTHESIZED_WIRE_29, data => SYNTHESIZED_WIRE_29,
tridata => FB_AD(26 DOWNTO 24)); tridata => FB_AD(26 DOWNTO 24)
);
inst52 : lpm_ff3 inst52 : lpm_ff3
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => CCS, data => CCS,
q => SYNTHESIZED_WIRE_26); q => SYNTHESIZED_WIRE_26
);
inst53 : lpm_bustri_byt inst53 : lpm_bustri_byt
PORT MAP(enabledt => ACP_CLUT_RD, PORT MAP
(
enabledt => ACP_CLUT_RD,
data => SYNTHESIZED_WIRE_30, data => SYNTHESIZED_WIRE_30,
tridata => FB_AD(7 DOWNTO 0)); tridata => FB_AD(7 DOWNTO 0)
);
inst54 : lpm_constant0 inst54 : lpm_constant0
PORT MAP( result => CCS(20 DOWNTO 16)); PORT MAP
(
result => CCS(20 DOWNTO 16)
);
inst56 : lpm_bustri1 inst56 : lpm_bustri1
PORT MAP(enabledt => ST_CLUT_RD, PORT MAP
(
enabledt => ST_CLUT_RD,
data => SYNTHESIZED_WIRE_31, data => SYNTHESIZED_WIRE_31,
tridata => FB_AD(22 DOWNTO 20)); tridata => FB_AD(22 DOWNTO 20)
);
inst57 : lpm_bustri_byt inst57 : lpm_bustri_byt
PORT MAP(enabledt => ACP_CLUT_RD, PORT MAP
(
enabledt => ACP_CLUT_RD,
data => SYNTHESIZED_WIRE_32, data => SYNTHESIZED_WIRE_32,
tridata => FB_AD(15 DOWNTO 8)); tridata => FB_AD(15 DOWNTO 8)
);
inst58 : lpm_bustri_byt inst58 : lpm_bustri_byt
PORT MAP(enabledt => ACP_CLUT_RD, PORT MAP
(
enabledt => ACP_CLUT_RD,
data => SYNTHESIZED_WIRE_33, data => SYNTHESIZED_WIRE_33,
tridata => FB_AD(23 DOWNTO 16)); tridata => FB_AD(23 DOWNTO 16)
);
inst59 : lpm_constant0 inst59 : lpm_constant0
PORT MAP( result => CCS(12 DOWNTO 8)); PORT MAP
(
result => CCS(12 DOWNTO 8)
);
inst61 : lpm_bustri1 inst61 : lpm_bustri1
PORT MAP(enabledt => ST_CLUT_RD, PORT MAP
(
enabledt => ST_CLUT_RD,
data => SYNTHESIZED_WIRE_34, data => SYNTHESIZED_WIRE_34,
tridata => FB_AD(18 DOWNTO 16)); tridata => FB_AD(18 DOWNTO 16)
);
inst62 : lpm_muxdz inst62 : lpm_muxdz
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
clken => FIFO_RDE, clken => FIFO_RDE,
sel => INTER_ZEI, sel => INTER_ZEI,
data0x => SYNTHESIZED_WIRE_63, data0x => SYNTHESIZED_WIRE_63,
data1x => SYNTHESIZED_WIRE_36, data1x => SYNTHESIZED_WIRE_36,
result => FIFO_D); result => FIFO_D
);
inst63 : lpm_fifodz inst63 : lpm_fifodz
PORT MAP(wrreq => SYNTHESIZED_WIRE_60, PORT MAP
(
wrreq => SYNTHESIZED_WIRE_60,
rdreq => SYNTHESIZED_WIRE_38, rdreq => SYNTHESIZED_WIRE_38,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
aclr => DOP_FIFO_CLR, aclr => DOP_FIFO_CLR,
data => SYNTHESIZED_WIRE_63, data => SYNTHESIZED_WIRE_63,
q => SYNTHESIZED_WIRE_36); q => SYNTHESIZED_WIRE_36
);
inst64 : lpm_constant0 inst64 : lpm_constant0
PORT MAP( result => CCS(4 DOWNTO 0)); PORT MAP
(
result => CCS(4 DOWNTO 0)
);
SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40;
inst66 : lpm_bustri3 inst66 : lpm_bustri3
PORT MAP(enabledt => FALCON_CLUT_RDH, PORT MAP
(
enabledt => FALCON_CLUT_RDH,
data => SYNTHESIZED_WIRE_41, data => SYNTHESIZED_WIRE_41,
tridata => FB_AD(31 DOWNTO 26)); tridata => FB_AD(31 DOWNTO 26)
);
SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI;
SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI);
inst7 : lpm_mux6 inst7 : lpm_mux6
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data0x => SYNTHESIZED_WIRE_42, data0x => SYNTHESIZED_WIRE_42,
data1x => SYNTHESIZED_WIRE_43, data1x => SYNTHESIZED_WIRE_43,
data2x => (OTHERS => '0'), data2x => (OTHERS => '0'),
@@ -1559,34 +1668,47 @@ BEGIN
data6x => CC24(23 DOWNTO 0), data6x => CC24(23 DOWNTO 0),
data7x => BORDER_COLOR, data7x => BORDER_COLOR,
sel => CCSEL, sel => CCSEL,
result => SYNTHESIZED_WIRE_62); result => SYNTHESIZED_WIRE_62
);
inst70 : lpm_bustri3 inst70 : lpm_bustri3
PORT MAP(enabledt => FALCON_CLUT_RDH, PORT MAP
(
enabledt => FALCON_CLUT_RDH,
data => SYNTHESIZED_WIRE_44, data => SYNTHESIZED_WIRE_44,
tridata => FB_AD(23 DOWNTO 18)); tridata => FB_AD(23 DOWNTO 18)
);
inst71 : lpm_ff6 inst71 : lpm_ff6
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => FIFO_WRE, enable => FIFO_WRE,
data => VDVZ, data => VDVZ,
q => VDMA); q => VDMA
);
inst74 : lpm_bustri3 inst74 : lpm_bustri3
PORT MAP(enabledt => FALCON_CLUT_RDL, PORT MAP
(
enabledt => FALCON_CLUT_RDL,
data => SYNTHESIZED_WIRE_45, data => SYNTHESIZED_WIRE_45,
tridata => FB_AD(23 DOWNTO 18)); tridata => FB_AD(23 DOWNTO 18)
);
inst77 : lpm_constant1 inst77 : lpm_constant1
PORT MAP( result => CCF(1 DOWNTO 0)); PORT MAP
(
result => CCF(1 DOWNTO 0)
);
@@ -1595,22 +1717,34 @@ BEGIN
inst80 : lpm_constant1 inst80 : lpm_constant1
PORT MAP( result => CCF(9 DOWNTO 8)); PORT MAP
(
result => CCF(9 DOWNTO 8)
);
inst81 : lpm_mux4 inst81 : lpm_mux4
PORT MAP(sel => COLOR1, PORT MAP
(
sel => COLOR1,
data0x => ZR_C8(7 DOWNTO 1), data0x => ZR_C8(7 DOWNTO 1),
data1x => SYNTHESIZED_WIRE_47, data1x => SYNTHESIZED_WIRE_47,
result => ZR_C8B(7 DOWNTO 1)); result => ZR_C8B(7 DOWNTO 1)
);
inst82 : lpm_constant3 inst82 : lpm_constant3
PORT MAP( result => SYNTHESIZED_WIRE_47); PORT MAP
(
result => SYNTHESIZED_WIRE_47
);
inst83 : lpm_constant1 inst83 : lpm_constant1
PORT MAP( result => CCF(17 DOWNTO 16)); PORT MAP
(
result => CCF(17 DOWNTO 16)
);
PROCESS(DDRCLK(0), DDR_WR) PROCESS(DDRCLK(0), DDR_WR)
@@ -1633,15 +1767,21 @@ BEGIN
inst89 : lpm_shiftreg6 inst89 : lpm_shiftreg6
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
shiftin => SR_BLITTER_DACK, shiftin => SR_BLITTER_DACK,
q => BLITTER_DACK); q => BLITTER_DACK
);
inst9 : lpm_ff1 inst9 : lpm_ff1
PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, PORT MAP
(
clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
data => SYNTHESIZED_WIRE_48, data => SYNTHESIZED_WIRE_48,
q => CC24); q => CC24
);
PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
@@ -1653,9 +1793,12 @@ BEGIN
inst92 : lpm_shiftreg6 inst92 : lpm_shiftreg6
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
shiftin => SR_DDR_FB, shiftin => SR_DDR_FB,
q => DDR_FB); q => DDR_FB
);
PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
@@ -1667,10 +1810,13 @@ BEGIN
inst94 : lpm_ff6 inst94 : lpm_ff6
PORT MAP(clock => DDRCLK(0), PORT MAP
(
clock => DDRCLK(0),
enable => FIFO_WRE, enable => FIFO_WRE,
data => VDMA, data => VDMA,
q => VDMB); q => VDMB
);
PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
@@ -1683,77 +1829,106 @@ BEGIN
inst97 : lpm_ff5 inst97 : lpm_ff5
PORT MAP(clock => DDRCLK(2), PORT MAP
(
clock => DDRCLK(2),
data => SR_VDMP, data => SR_VDMP,
q => VDMP); q => VDMP
);
sr0 : lpm_shiftreg0 sr0 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_49, shiftin => SYNTHESIZED_WIRE_49,
data => FIFO_D(127 DOWNTO 112), data => FIFO_D(127 DOWNTO 112),
shiftout => CLUT_ADR(0)); shiftout => CLUT_ADR(0)
);
sr1 : lpm_shiftreg0 sr1 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_50, shiftin => SYNTHESIZED_WIRE_50,
data => FIFO_D(111 DOWNTO 96), data => FIFO_D(111 DOWNTO 96),
shiftout => CLUT_ADR1A); shiftout => CLUT_ADR1A
);
sr2 : lpm_shiftreg0 sr2 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_51, shiftin => SYNTHESIZED_WIRE_51,
data => FIFO_D(95 DOWNTO 80), data => FIFO_D(95 DOWNTO 80),
shiftout => CLUT_ADR2A); shiftout => CLUT_ADR2A
);
sr3 : lpm_shiftreg0 sr3 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_52, shiftin => SYNTHESIZED_WIRE_52,
data => FIFO_D(79 DOWNTO 64), data => FIFO_D(79 DOWNTO 64),
shiftout => CLUT_ADR3A); shiftout => CLUT_ADR3A
);
sr4 : lpm_shiftreg0 sr4 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_53, shiftin => SYNTHESIZED_WIRE_53,
data => FIFO_D(63 DOWNTO 48), data => FIFO_D(63 DOWNTO 48),
shiftout => CLUT_ADR4A); shiftout => CLUT_ADR4A
);
sr5 : lpm_shiftreg0 sr5 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => SYNTHESIZED_WIRE_54, shiftin => SYNTHESIZED_WIRE_54,
data => FIFO_D(47 DOWNTO 32), data => FIFO_D(47 DOWNTO 32),
shiftout => CLUT_ADR5A); shiftout => CLUT_ADR5A
);
sr6 : lpm_shiftreg0 sr6 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => CLUT_ADR7A, shiftin => CLUT_ADR7A,
data => FIFO_D(31 DOWNTO 16), data => FIFO_D(31 DOWNTO 16),
shiftout => CLUT_ADR6A); shiftout => CLUT_ADR6A
);
sr7 : lpm_shiftreg0 sr7 : lpm_shiftreg0
PORT MAP(load => SYNTHESIZED_WIRE_64, PORT MAP
(
load => SYNTHESIZED_WIRE_64,
clock => PIXEL_CLK_ALTERA_SYNTHESIZED, clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
shiftin => CLUT_ADR(0), shiftin => CLUT_ADR(0),
data => FIFO_D(15 DOWNTO 0), data => FIFO_D(15 DOWNTO 0),
shiftout => CLUT_ADR7A); shiftout => CLUT_ADR7A
);
ST_CLUT_BLUE : altdpram0 ST_CLUT_BLUE : altdpram0
PORT MAP(wren_a => ST_CLUT_WR(1), PORT MAP
(
wren_a => ST_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_55, wren_b => SYNTHESIZED_WIRE_55,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -1762,11 +1937,14 @@ BEGIN
data_a => FB_AD(18 DOWNTO 16), data_a => FB_AD(18 DOWNTO 16),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_34, q_a => SYNTHESIZED_WIRE_34,
q_b => CCS(7 DOWNTO 5)); q_b => CCS(7 DOWNTO 5)
);
ST_CLUT_GREEN : altdpram0 ST_CLUT_GREEN : altdpram0
PORT MAP(wren_a => ST_CLUT_WR(1), PORT MAP
(
wren_a => ST_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_56, wren_b => SYNTHESIZED_WIRE_56,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -1775,11 +1953,14 @@ BEGIN
data_a => FB_AD(22 DOWNTO 20), data_a => FB_AD(22 DOWNTO 20),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_31, q_a => SYNTHESIZED_WIRE_31,
q_b => CCS(15 DOWNTO 13)); q_b => CCS(15 DOWNTO 13)
);
ST_CLUT_RED : altdpram0 ST_CLUT_RED : altdpram0
PORT MAP(wren_a => ST_CLUT_WR(0), PORT MAP
(
wren_a => ST_CLUT_WR(0),
wren_b => SYNTHESIZED_WIRE_57, wren_b => SYNTHESIZED_WIRE_57,
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
@@ -1788,11 +1969,14 @@ BEGIN
data_a => FB_AD(26 DOWNTO 24), data_a => FB_AD(26 DOWNTO 24),
data_b => (OTHERS => '0'), data_b => (OTHERS => '0'),
q_a => SYNTHESIZED_WIRE_29, q_a => SYNTHESIZED_WIRE_29,
q_b => CCS(23 DOWNTO 21)); q_b => CCS(23 DOWNTO 21)
);
i_video_mod_mux_clutctr : video_mod_mux_clutctr i_video_mod_mux_clutctr : video_mod_mux_clutctr
PORT MAP(nRSTO => nRSTO, PORT MAP
(
nRSTO => nRSTO,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
nFB_CS1 => nFB_CS1, nFB_CS1 => nFB_CS1,
nFB_CS2 => nFB_CS2, nFB_CS2 => nFB_CS2,
@@ -1840,7 +2024,8 @@ BEGIN
CLUT_OFF => CLUT_OFF, CLUT_OFF => CLUT_OFF,
FALCON_CLUT_WR => FALCON_CLUT_WR, FALCON_CLUT_WR => FALCON_CLUT_WR,
ST_CLUT_WR => ST_CLUT_WR, ST_CLUT_WR => ST_CLUT_WR,
VIDEO_RAM_CTR => VIDEO_RAM_CTR); VIDEO_RAM_CTR => VIDEO_RAM_CTR
);
PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED;
END rtl; END rtl;