diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf
index af39682..5353743 100644
--- a/FPGA_Quartus_13.1/firebee1.qsf
+++ b/FPGA_Quartus_13.1/firebee1.qsf
@@ -677,7 +677,6 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
 set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd
 set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
 set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
@@ -864,4 +863,5 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip
 set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
 set_global_assignment -name QIP_FILE lpm_counter1.qip
 set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
-set_global_assignment -name VHDL_FILE flexbus_register.vhd
\ No newline at end of file
+set_global_assignment -name VHDL_FILE flexbus_register.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd
index c488e1b..d7aea7e 100644
--- a/FPGA_Quartus_13.1/flexbus_register.vhd
+++ b/FPGA_Quartus_13.1/flexbus_register.vhd
@@ -2,50 +2,79 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library work;
+use work.firebee_utils_pkg.all;
+
 entity flexbus_register is
     generic
     (
         reg_width       : integer := 11;
         match_address   : std_logic_vector(31 downto 0) := (others => '0');
-        match_mask      : std_logic_vector(31 downto 0) := (others => '1');
+        num_ignore      : integer range 0 to 31;
         match_fbcs      : integer := 0
     );
     port
     (
         clk             : in std_logic;
+        
+        -- FlexBus signals
         fb_addr         : in std_logic_vector(31 downto 0);
-        fb_data         : inout std_logic_vector(31 downto 0);
-        fb_cs           : in std_logic_vector(5 downto 1);
+        fb_ad_in        : in std_logic_vector(31 downto 0);
+        fb_ad_out       : out std_logic_vector(31 downto 0);
+        fb_cs_n         : in std_logic_vector(5 downto 1);
         fb_wr_n         : in std_logic;
-        fb_ta_n         : out std_logic;
-        reg_value       : inout std_logic_vector(reg_width - 1 downto 0);
-        cs              : out std_logic := '0'
+        fb_oe_n         : in std_logic;
+        fb_size         : in std_logic_vector(1 downto 0);
+        
+        register_ta     : out std_logic
     );
 end entity flexbus_register;
     
 architecture rtl of flexbus_register is
     signal fbcs_match       : std_logic;
     signal address_match    : std_logic;
+    signal fb_b             : std_logic_vector(3 downto 0);         -- byte selects
+    signal cs               : std_logic;
+    signal reg_value        : std_logic_vector(reg_width - 1 downto 0);
 begin
-    fbcs_match <= '1' when fb_cs(match_fbcs) = '1' else '0';
-    address_match <= '1' when (fb_addr and match_mask) = (match_address and match_mask) else '0';
+    --  byte selects
+    --  HWORD
+    --  HHBYT
+    --  LONG UND LINE
+    fb_b(0) <= (fb_size(1) and (not fb_size(0)) and (not fb_addr(1))) or
+               ((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and (not fb_addr(0))) or
+               ((not fb_size(1)) and (not fb_size(0))) or
+               (fb_size(1) and fb_size(0));
+
+    --  HWORD
+    --  HLBYT
+    --  LONG UND LINE
+    fb_b(1) <= (fb_size(1) and (not fb_size(0) and (not fb_addr(1)))) or
+               ((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and fb_addr(0)) or
+               ((not fb_size(1)) and (not fb_size(0))) or
+               (fb_size(1) and fb_size(0));
+
+    --  LWORD
+    --  LHBYT
+    --  LONG UND LINE
+    fb_b(2) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or
+               ((not fb_size(1)) and fb_size(0) and fb_addr(1) and (not fb_addr(0))) or
+               ((not fb_size(1)) and (not fb_size(0))) or (fb_size(1) and fb_size(0));
+
+    --  LWORD
+    --  LLBYT
+    --  LONG UND LINE
+    fb_b(3) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or
+               ((not fb_size(1)) and fb_size(0) and fb_addr(1) and fb_addr(0)) or
+               ((not fb_size(1)) and (not fb_size(0))) or
+               (fb_size(1) and fb_size(0));
+
+    fbcs_match <= '1' when not(fb_cs_n(match_fbcs)) = '1' else '0';
+    address_match <= f_addr_cmp_mask(fb_addr, match_address, num_ignore);
     
     p_register_access : process(all)
     begin
         if rising_edge(clk) then
-            if fbcs_match = '1' and address_match = '1' then
-                cs <= '1';
-                if fb_wr_n = '0' then   -- write access
-                    reg_value <= fb_data(reg_width - 1 downto 0);
-                else                    -- read access
-                    fb_data(reg_width - 1 downto 0) <= reg_value;
-                    fb_ta_n <= '0';
-                end if;
-            else
-                fb_data <= (others => 'Z');
-                fb_ta_n <= 'Z';
-                cs <= '0';
-            end if;
         end if;
     end process p_register_access;
 end architecture rtl;
\ No newline at end of file