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start of flexbus_register implementation to simplify that

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This commit is contained in:
Markus Fröschle
2016-01-17 20:28:18 +00:00
parent ddad975d6f
commit 21a4a80fb7
6 changed files with 353 additions and 421 deletions
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22
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
View File

@@ -276,7 +276,8 @@ ARCHITECTURE rtl OF ddr_ctr IS
SIGNAL VRAS : std_logic;
SIGNAL VCAS : std_logic;
SIGNAL LINE : std_logic;
SIGNAL v_bash : std_logic_vector(7 DOWNTO 0);
SIGNAL v_bash_cs : std_logic;
-- Sub Module Interface Section
@@ -573,6 +574,25 @@ BEGIN
END IF;
END PROCESS;
i_vbash : work.flexbus_register
GENERIC MAP
(
reg_width => 8,
match_address => x"ffff8604",
match_mask => x"0000fffe", -- byte register
match_fbcs => 1
)
PORT MAP
(
clk => clk33m,
fb_addr => fb_adr,
fb_data => fb_ad,
fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
fb_wr_n => nfb_wr,
data => v_bash,
cs => v_bash_cs
);
-- Start of original equations
LINE <= FB_SIZE0 and FB_SIZE1;

386
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -270,11 +270,14 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic;
SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic;
SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic;
SIGNAL ACP_VCTR0_clk_ctrl : std_logic;
SIGNAL ACP_VCTR24_ena_ctrl : std_logic;
SIGNAL ACP_VCTR16_ena_ctrl : std_logic;
SIGNAL ACP_VCTR8_ena_ctrl : std_logic;
SIGNAL ACP_VCTR6_ena_ctrl : std_logic;
SIGNAL ACP_VCTR0_ena_ctrl : std_logic;
SIGNAL ATARI_HH0_clk_ctrl : std_logic;
SIGNAL ATARI_HH24_ena_ctrl : std_logic;
SIGNAL ATARI_HH16_ena_ctrl : std_logic;
@@ -299,7 +302,6 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL VR_DOUT0_ena_ctrl : std_logic;
SIGNAL VR_FRQ0_clk_ctrl : std_logic;
SIGNAL VR_FRQ0_ena_ctrl : std_logic;
SIGNAL ACP_VCTR6_ena_ctrl : std_logic;
SIGNAL CCSEL0_clk_ctrl : std_logic;
SIGNAL BORDER_COLOR0_clk_ctrl : std_logic;
SIGNAL BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl,
@@ -580,49 +582,23 @@ BEGIN
END IF;
END PROCESS;
PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
if ACP_VCTR24_ena_ctrl='1' THEN
(ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28),
ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25),
ACP_VCTR_q(24)) <= ACP_VCTR_d(31 DOWNTO 24);
PROCESS (ACP_VCTR0_clk_ctrl)
BEGIN
IF rising_edge(ACP_VCTR0_clk_ctrl) THEN
IF ACP_VCTR24_ena_ctrl = '1' THEN
ACP_VCTR_q(31 DOWNTO 24) <= ACP_VCTR_d(31 DOWNTO 24);
END IF;
IF ACP_VCTR16_ena_ctrl = '1' THEN
ACP_VCTR_q(23 DOWNTO 16) <= ACP_VCTR_d(23 DOWNTO 16);
END IF;
END PROCESS;
PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
if ACP_VCTR16_ena_ctrl='1' THEN
(ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20),
ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17),
ACP_VCTR_q(16)) <= ACP_VCTR_d(23 DOWNTO 16);
IF ACP_VCTR8_ena_ctrl = '1' THEN
ACP_VCTR_q(15 DOWNTO 8) <= ACP_VCTR_d(15 DOWNTO 8);
END IF;
IF ACP_VCTR6_ena_ctrl = '1' THEN
ACP_VCTR_q(7 DOWNTO 6) <= ACP_VCTR_d(7 DOWNTO 6);
END IF;
END PROCESS;
PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
if ACP_VCTR8_ena_ctrl='1' THEN
(ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12),
ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8))
<= ACP_VCTR_d(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
if ACP_VCTR6_ena_ctrl='1' THEN
(ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 DOWNTO 6);
END IF;
END IF;
END PROCESS;
PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
if ACP_VCTR0_ena_ctrl='1' THEN
(ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2),
ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 DOWNTO 0);
IF ACP_VCTR0_ena_ctrl = '1' THEN
ACP_VCTR_q(5 DOWNTO 0) <= ACP_VCTR_d(5 DOWNTO 0);
END IF;
END IF;
END PROCESS;
@@ -841,218 +817,116 @@ BEGIN
END IF;
END PROCESS;
PROCESS (ATARI_HH0_clk_ctrl) BEGIN
if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
if ATARI_HH24_ena_ctrl='1' THEN
(ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28),
ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25),
ATARI_HH_q(24)) <= ATARI_HH_d(31 DOWNTO 24);
PROCESS (ATARI_HH0_clk_ctrl)
BEGIN
IF rising_edge(ATARI_HH0_clk_ctrl) THEN
IF ATARI_HH24_ena_ctrl = '1' THEN
ATARI_HH_q(31 DOWNTO 24) <= ATARI_HH_d(31 DOWNTO 24);
END IF;
IF ATARI_HH16_ena_ctrl = '1' THEN
ATARI_HH_q(23 DOWNTO 16) <= ATARI_HH_d(23 DOWNTO 16);
END IF;
IF ATARI_HH8_ena_ctrl = '1' THEN
ATARI_HH_q(15 DOWNTO 8) <= ATARI_HH_d(15 DOWNTO 8);
END IF;
IF ATARI_HH0_ena_ctrl = '1' THEN
ATARI_HH_q(7 DOWNTO 0) <= ATARI_HH_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HH0_clk_ctrl) BEGIN
if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
if ATARI_HH16_ena_ctrl='1' THEN
(ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20),
ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17),
ATARI_HH_q(16)) <= ATARI_HH_d(23 DOWNTO 16);
PROCESS (ATARI_VH0_clk_ctrl)
BEGIN
IF rising_edge(ATARI_VH0_clk_ctrl) THEN
IF ATARI_VH24_ena_ctrl = '1' THEN
ATARI_VH_q(31 DOWNTO 24) <= ATARI_VH_d(31 DOWNTO 24);
END IF;
IF ATARI_VH16_ena_ctrl = '1' THEN
ATARI_VH_q(23 DOWNTO 16) <= ATARI_VH_d(23 DOWNTO 16);
END IF;
END PROCESS;
PROCESS (ATARI_HH0_clk_ctrl) BEGIN
if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
if ATARI_HH8_ena_ctrl='1' THEN
(ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12),
ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8))
<= ATARI_HH_d(15 DOWNTO 8);
IF ATARI_VH8_ena_ctrl = '1' THEN
ATARI_VH_q(15 DOWNTO 8) <= ATARI_VH_d(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HH0_clk_ctrl) BEGIN
if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
if ATARI_HH0_ena_ctrl='1' THEN
(ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4),
ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0))
<= ATARI_HH_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VH0_clk_ctrl) BEGIN
if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
if ATARI_VH24_ena_ctrl='1' THEN
(ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28),
ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25),
ATARI_VH_q(24)) <= ATARI_VH_d(31 DOWNTO 24);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VH0_clk_ctrl) BEGIN
if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
if ATARI_VH16_ena_ctrl='1' THEN
(ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20),
ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17),
ATARI_VH_q(16)) <= ATARI_VH_d(23 DOWNTO 16);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VH0_clk_ctrl) BEGIN
if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
if ATARI_VH8_ena_ctrl='1' THEN
(ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12),
ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8))
<= ATARI_VH_d(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VH0_clk_ctrl) BEGIN
if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
if ATARI_VH0_ena_ctrl='1' THEN
(ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4),
ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0))
<= ATARI_VH_d(7 DOWNTO 0);
IF ATARI_VH0_ena_ctrl='1' THEN
ATARI_VH_q(7 DOWNTO 0) <= ATARI_VH_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HL0_clk_ctrl) BEGIN
if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
if ATARI_HL24_ena_ctrl='1' THEN
(ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28),
ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25),
ATARI_HL_q(24)) <= ATARI_HL_d(31 DOWNTO 24);
IF rising_edge(ATARI_HL0_clk_ctrl) THEN
IF ATARI_HL24_ena_ctrl = '1' THEN
ATARI_HL_q(31 DOWNTO 24) <= ATARI_HL_d(31 DOWNTO 24);
END IF;
IF ATARI_HL16_ena_ctrl = '1' THEN
ATARI_HL_q(23 DOWNTO 16) <= ATARI_HL_d(23 DOWNTO 16);
END IF;
IF ATARI_HL8_ena_ctrl = '1' THEN
ATARI_HL_q(15 DOWNTO 8) <= ATARI_HL_d(15 DOWNTO 8);
END IF;
IF ATARI_HL0_ena_ctrl = '1' THEN
ATARI_HL_q(7 DOWNTO 0) <= ATARI_HL_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HL0_clk_ctrl) BEGIN
if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
if ATARI_HL16_ena_ctrl='1' THEN
(ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20),
ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17),
ATARI_HL_q(16)) <= ATARI_HL_d(23 DOWNTO 16);
PROCESS (ATARI_VL0_clk_ctrl)
BEGIN
IF rising_edge(ATARI_VL0_clk_ctrl) THEN
IF ATARI_VL24_ena_ctrl = '1' THEN
ATARI_VL_q(31 DOWNTO 24) <= ATARI_VL_d(31 DOWNTO 24);
END IF;
IF ATARI_VL16_ena_ctrl = '1' THEN
ATARI_VL_q(23 DOWNTO 16) <= ATARI_VL_d(23 DOWNTO 16);
END IF;
IF ATARI_VL8_ena_ctrl = '1' THEN
ATARI_VL_q(15 DOWNTO 8) <= ATARI_VL_d(15 DOWNTO 8);
END IF;
IF ATARI_VL0_ena_ctrl = '1' THEN
ATARI_VL_q(7 DOWNTO 0) <= ATARI_VL_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HL0_clk_ctrl) BEGIN
if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
if ATARI_HL8_ena_ctrl='1' THEN
(ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12),
ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8))
<= ATARI_HL_d(15 DOWNTO 8);
PROCESS (HHT0_clk_ctrl)
BEGIN
IF rising_edge(HHT0_clk_ctrl) THEN
IF HHT8_ena_ctrl = '1' THEN
HHT_q(11 DOWNTO 8) <= HHT_d(11 DOWNTO 8);
END IF;
IF HHT0_ena_ctrl = '1' THEN
HHT_q(7 DOWNTO 0) <= HHT_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_HL0_clk_ctrl) BEGIN
if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
if ATARI_HL0_ena_ctrl='1' THEN
(ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4),
ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0))
<= ATARI_HL_d(7 DOWNTO 0);
PROCESS (HBE0_clk_ctrl)
BEGIN
IF rising_edge(HBE0_clk_ctrl) THEN
IF HBE8_ena_ctrl = '1' THEN
HBE_q(11 DOWNTO 8) <= HBE_d(11 DOWNTO 8);
END IF;
IF HBE0_ena_ctrl = '1' THEN
HBE_q(7 DOWNTO 0) <= HBE_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VL0_clk_ctrl) BEGIN
if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
if ATARI_VL24_ena_ctrl='1' THEN
(ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28),
ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25),
ATARI_VL_q(24)) <= ATARI_VL_d(31 DOWNTO 24);
PROCESS (HDB0_clk_ctrl)
BEGIN
IF rising_edge(HDB0_clk_ctrl) THEN
IF HDB8_ena_ctrl = '1' THEN
HDB_q(11 DOWNTO 8) <= HDB_d(11 DOWNTO 8);
END IF;
IF HDB0_ena_ctrl = '1' THEN
HDB_q(7 DOWNTO 0) <= HDB_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VL0_clk_ctrl) BEGIN
if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
if ATARI_VL16_ena_ctrl='1' THEN
(ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20),
ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17),
ATARI_VL_q(16)) <= ATARI_VL_d(23 DOWNTO 16);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VL0_clk_ctrl) BEGIN
if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
if ATARI_VL8_ena_ctrl='1' THEN
(ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12),
ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8))
<= ATARI_VL_d(15 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (ATARI_VL0_clk_ctrl) BEGIN
if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
if ATARI_VL0_ena_ctrl='1' THEN
(ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4),
ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0))
<= ATARI_VL_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (HHT0_clk_ctrl) BEGIN
if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN
if HHT8_ena_ctrl='1' THEN
(HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (HHT0_clk_ctrl) BEGIN
if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN
if HHT0_ena_ctrl='1' THEN
(HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2),
HHT_q(1), HHT_q(0)) <= HHT_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (HBE0_clk_ctrl) BEGIN
if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN
if HBE8_ena_ctrl='1' THEN
(HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (HBE0_clk_ctrl) BEGIN
if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN
if HBE0_ena_ctrl='1' THEN
(HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2),
HBE_q(1), HBE_q(0)) <= HBE_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (HDB0_clk_ctrl) BEGIN
if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN
if HDB8_ena_ctrl='1' THEN
(HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 DOWNTO 8);
END IF;
END IF;
END PROCESS;
PROCESS (HDB0_clk_ctrl) BEGIN
if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN
if HDB0_ena_ctrl='1' THEN
(HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2),
HDB_q(1), HDB_q(0)) <= HDB_d(7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
PROCESS (HDE0_clk_ctrl) BEGIN
PROCESS (HDE0_clk_ctrl)
BEGIN
if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN
if HDE8_ena_ctrl='1' THEN
(HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8);
@@ -1362,10 +1236,11 @@ BEGIN
ACP_VCTR0_clk_ctrl <= MAIN_CLK;
-- $400/4
ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
"00000000000000000100000000");
ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000");
ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8);
ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0);
ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR);
ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR);
ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR);
@@ -1465,9 +1340,8 @@ BEGIN
ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not
ACP_VIDEO_ON);
ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON);
ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or
(ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and
(not nFB_WR) and FB_AD(0));
ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0));
FALCON_VIDEO <= ACP_VCTR_q(7);
FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16);
ST_VIDEO <= ACP_VCTR_q(6);
@@ -1661,19 +1535,16 @@ BEGIN
-- VCNTRL
-- $82C2 / 2 Falcon resolution control register VCNTRL
VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) =
"1111100000101100001");
VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100001");
VCNTRL0_clk_ctrl <= MAIN_CLK;
VCNTRL_d <= FB_AD(19 DOWNTO 16);
VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3);
-- - REGISTER OUT
-- low word register access
u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" &
ST_SHIFT_MODE_q & "00000000")) or (sizeIt(FALCON_SHIFT_MODE_CS,16) and
std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or
(sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6
DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or
u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or
(sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or
(sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or
(sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or
(sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or
(sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or
@@ -1688,23 +1559,19 @@ BEGIN
(sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or
(sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or
(sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or
(sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" &
VCNTRL_q)) or (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or
(sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or
(sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or
(sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 DOWNTO 16)) or
(sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 DOWNTO 16)) or
(sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 DOWNTO 16)) or
(sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 DOWNTO 16)) or
(sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" &
BORDER_COLOR_q(23 DOWNTO 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and
std_logic_vector'("0000000" & VR_DOUT_q)) or
(sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY &
"0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010"));
u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or
BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS
or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS
or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or
VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE);
(sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 DOWNTO 16))) or
(sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or
(sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010"));
u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or
VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE);
FB_AD(31 DOWNTO 16) <= u0_tridata;
-- high word register access
@@ -1714,18 +1581,17 @@ BEGIN
(sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 DOWNTO 0)) or
(sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 DOWNTO 0)) or
(sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 DOWNTO 0));
u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS
or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
FB_AD(15 DOWNTO 0) <= u1_tridata;
VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or
ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or
ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS;
-- VIDEO AUSGABE SETZEN
CLK17M_clk <= CLK33M;
CLK17M_d <= not CLK17M_q;
CLK13M_clk <= CLK25M;
CLK13M_d <= not CLK13M_q;
@@ -1733,17 +1599,13 @@ BEGIN
-- 320 pixels, 25.175 MHz,
-- 640 pixels, 32 MHz, VGA monitor
-- 640 pixels, 25.175 MHz, VGA monitor
PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO)
and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or (CLK17M_q and (not
ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and
(not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and
(FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not
VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or
ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0)))
or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO
8) = "00")) or (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and
ACP_VCTR_q(9 DOWNTO 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and
ACP_VCTR_q(9));
PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or
(CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or
(CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or
(CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or
(to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "00")) or
(to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "01")) or
(CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9));
-- ------------------------------------------------------------
-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK

6
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -675,6 +675,9 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
set_global_assignment -name AHDL_FILE altpll4.tdf
set_global_assignment -name SDC_FILE firebee_groups.sdc
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
@@ -857,6 +860,5 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
set_global_assignment -name VHDL_FILE flexbus_register.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

144
FPGA_Quartus_13.1/firebee1.vhd
View File

@@ -205,90 +205,90 @@ ARCHITECTURE rtl OF firebee1 IS
COMPONENT altpll_reconfig1
PORT
(
clock : IN STD_LOGIC ;
counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset_in : IN STD_LOGIC := '0';
pll_scandataout : IN STD_LOGIC ;
pll_scandone : IN STD_LOGIC ;
read_param : IN STD_LOGIC ;
reconfig : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
write_param : IN STD_LOGIC ;
busy : OUT STD_LOGIC ;
data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
pll_areset : OUT STD_LOGIC ;
pll_configupdate : OUT STD_LOGIC ;
pll_scanclk : OUT STD_LOGIC ;
pll_scanclkena : OUT STD_LOGIC ;
pll_scandata : OUT STD_LOGIC
clock : IN std_logic ;
counter_param : IN std_logic_vector (2 DOWNTO 0);
counter_type : IN std_logic_vector (3 DOWNTO 0);
data_in : IN std_logic_vector (8 DOWNTO 0);
pll_areset_in : IN std_logic := '0';
pll_scandataout : IN std_logic ;
pll_scandone : IN std_logic ;
read_param : IN std_logic ;
reconfig : IN std_logic ;
reset : IN std_logic ;
write_param : IN std_logic ;
busy : OUT std_logic ;
data_out : OUT std_logic_vector (8 DOWNTO 0);
pll_areset : OUT std_logic ;
pll_configupdate : OUT std_logic ;
pll_scanclk : OUT std_logic ;
pll_scanclkena : OUT std_logic ;
pll_scandata : OUT std_logic
);
END COMPONENT altpll_reconfig1;
COMPONENT altpll4
PORT
(
areset : IN STD_LOGIC := '0';
configupdate : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
scanclk : IN STD_LOGIC := '1';
scanclkena : IN STD_LOGIC := '0';
scandata : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC ;
scandataout : OUT STD_LOGIC ;
scandone : OUT STD_LOGIC
areset : IN std_logic := '0';
configupdate : IN std_logic := '0';
inclk0 : IN std_logic := '0';
scanclk : IN std_logic := '1';
scanclkena : IN std_logic := '0';
scandata : IN std_logic := '0';
c0 : OUT std_logic ;
locked : OUT std_logic ;
scandataout : OUT std_logic ;
scandone : OUT std_logic
);
END COMPONENT altpll4;
COMPONENT Video
COMPONENT video
PORT
(
FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
MAIN_CLK : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nRSTO : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_SYNC_66M : IN STD_LOGIC;
CLK33M : IN STD_LOGIC;
CLK25M : IN STD_LOGIC;
CLK_VIDEO : IN STD_LOGIC;
VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
VR_BUSY : IN STD_LOGIC;
VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
nBLANK : OUT STD_LOGIC;
VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
nVWE : OUT STD_LOGIC;
nVCAS : OUT STD_LOGIC;
nVRAS : OUT STD_LOGIC;
nVCS : OUT STD_LOGIC;
VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
nPD_VGA : OUT STD_LOGIC;
VCKE : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
HSYNC : OUT STD_LOGIC;
nSYNC : OUT STD_LOGIC;
VIDEO_TA : OUT STD_LOGIC;
PIXEL_CLK : OUT STD_LOGIC;
BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
VIDEO_RECONFIG : OUT STD_LOGIC;
VR_WR : OUT STD_LOGIC;
VR_RD : OUT STD_LOGIC;
VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
MAIN_CLK : IN std_logic;
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
nFB_WR : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
nRSTO : IN std_logic;
nFB_OE : IN std_logic;
FB_ALE : IN std_logic;
DDRCLK : IN std_logic_vector(3 DOWNTO 0);
DDR_SYNC_66M : IN std_logic;
CLK33M : IN std_logic;
CLK25M : IN std_logic;
CLK_VIDEO : IN std_logic;
VR_D : IN std_logic_vector(8 DOWNTO 0);
VR_BUSY : IN std_logic;
VG : OUT std_logic_vector(7 DOWNTO 0);
VB : OUT std_logic_vector(7 DOWNTO 0);
VR : OUT std_logic_vector(7 DOWNTO 0);
nBLANK : OUT std_logic;
VA : OUT std_logic_vector(12 DOWNTO 0);
nVWE : OUT std_logic;
nVCAS : OUT std_logic;
nVRAS : OUT std_logic;
nVCS : OUT std_logic;
VDM : OUT std_logic_vector(3 DOWNTO 0);
nPD_VGA : OUT std_logic;
VCKE : OUT std_logic;
VSYNC : OUT std_logic;
HSYNC : OUT std_logic;
nSYNC : OUT std_logic;
VIDEO_TA : OUT std_logic;
PIXEL_CLK : OUT std_logic;
BA : OUT std_logic_vector(1 DOWNTO 0);
VIDEO_RECONFIG : OUT std_logic;
VR_WR : OUT std_logic;
VR_RD : OUT std_logic;
VDQS : INOUT std_logic_vector(3 DOWNTO 0);
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
VD : INOUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
END COMPONENT video;
BEGIN
nDREQ1 <= nDACK1;

4
FPGA_Quartus_13.1/firebee_groups.sdc
View File

@@ -112,8 +112,8 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.5
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.5
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5
derive_clock_uncertainty

48
FPGA_Quartus_13.1/flexbus_register.vhd Normal file
View File

@@ -0,0 +1,48 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY flexbus_register IS
GENERIC
(
reg_width : integer := 11;
match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
match_fbcs : integer := 0
);
PORT
(
clk : IN std_logic;
fb_addr : IN std_logic_vector(31 DOWNTO 0);
fb_data : IN std_logic_vector(31 DOWNTO 0);
fb_cs : IN std_logic_vector(5 DOWNTO 1);
fb_wr_n : IN std_logic;
data : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
cs : OUT std_logic := '0'
);
END ENTITY flexbus_register;
ARCHITECTURE rtl OF flexbus_register IS
SIGNAL fbcs_match : std_logic;
SIGNAL address_match : std_logic;
SIGNAL reg_value : std_logic_vector(reg_width - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0';
address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0';
p_register_access : PROCESS(ALL)
BEGIN
IF rising_edge(clk) THEN
IF fbcs_match = '1' and address_match = '1' THEN
cs <= '1';
IF fb_wr_n = '0' THEN -- write access
reg_value <= fb_data(reg_width - 1 DOWNTO 0);
ELSE -- read access
data <= reg_value;
END IF;
ELSE
cs <= '0';
END IF;
END IF;
END PROCESS p_register_access;
END ARCHITECTURE rtl;