formatting

FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd

@@ -21,10 +21,8 @@
 -- Created on Fri Oct 16 15:40:59 2009
 
 LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-
---  Entity Declaration
+    USE ieee.std_logic_1164.ALL;
+    USE ieee.numeric_std.ALL;
 
 ENTITY blitter IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
@@ -59,9 +57,7 @@ ENTITY blitter IS
 END BLITTER;
 
 
---  Architecture Body
-
-ARCHITECTURE BLITTER_architecture OF blitter IS
+ARCHITECTURE rtl OF blitter IS
 
 	
 BEGIN
@@ -72,4 +68,4 @@ BEGIN
 	BLITTER_WR <= '0';
 	BLITTER_TA <= '0';
 
-END BLITTER_architecture;
+END rtl;