This commit is contained in:
aschi54
352
FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak
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352
FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak
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TITLE "DDR_CTR_BLITTER";
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-- CREATED BY FREDI ASCHWANDEN
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INCLUDE "lpm_bustri_BYT.inc";
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-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
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SUBDESIGN DDR_CTR_BLITTER
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(
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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FB_ADR[31..0] : INPUT;
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nFB_CS1 : INPUT;
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nFB_CS2 : INPUT;
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nFB_CS3 : INPUT;
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nFB_OE : INPUT;
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FB_SIZE0 : INPUT;
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FB_SIZE1 : INPUT;
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nRSTO : INPUT;
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MAIN_CLK : INPUT;
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FIFO_FULL : INPUT;
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FB_ALE : INPUT;
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nFB_WR : INPUT;
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DDR_SYNC_66M : INPUT;
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VSYNC : INPUT;
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BLITTER_ON : INPUT;
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VIDEO_RAM_CTR[15..0] : INPUT;
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VDVZ[127..0] : INPUT;
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DDRCLK[3..0] : INPUT;
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BA0 : OUTPUT;
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BA1 : OUTPUT;
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VA[12..0] : OUTPUT;
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nVWE : OUTPUT;
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nVRAS : OUTPUT;
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nVCS : OUTPUT;
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VCKE : OUTPUT;
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nVCAS : OUTPUT;
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FIFO_WRE : OUTPUT;
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FB_LE[3..0] : OUTPUT;
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FB_VDOE[3..0] : OUTPUT;
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START_CYC_RDWR : OUTPUT;
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DDR_WR : OUTPUT;
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CLEAR_FIFO_CNT : OUTPUT;
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BLITTER_RUN : OUTPUT;
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BLITTER_DOUT[127..0] : OUTPUT;
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BLITTER_LE[3..0] : OUTPUT;
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BLITTER_RDE : OUTPUT;
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DDRWR_D_SEL[1..0] : OUTPUT;
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VDMP[7..0] : OUTPUT;
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FB_AD[31..0] : BIDIR;
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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)
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VARIABLE
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FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
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DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
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LINE :NODE;
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FB_B[3..0] :NODE;
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VCAS :NODE;
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VRAS :NODE;
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VWE :NODE;
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VA[12..0] :NODE;
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BA0 :NODE;
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BA1 :NODE;
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DDR_WR :DFF;
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DDR_SEL :NODE;
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DDR_CONFIG :NODE;
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DDRWR_D_SEL[1..0] :DFF;
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CPU_ROW_ADR[12..0] :NODE;
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CPU_BA0 :NODE;
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CPU_BA1 :NODE;
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CPU_COL_ADR[9..0] :NODE;
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CPU_SIG :NODE;
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CPU_REQ :DFF;
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BLITTER_SIG :NODE;
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BLITTER_REQ :DFF;
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BLITTER_RUN :DFF;
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BLITTER_WR :DFF;
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BLITTER_ROW_ADR[12..0] :NODE;
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BLITTER_BA0 :NODE;
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BLITTER_BA1 :NODE;
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BLITTER_COL_ADR[9..0] :NODE;
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FIFO_SIG :NODE;
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FIFO_REQ :DFF;
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FIFO_ROW_ADR[12..0] :NODE;
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FIFO_BA0 :NODE;
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FIFO_BA1 :NODE;
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FIFO_COL_ADR[9..0] :NODE;
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FIFO_WRE :DFF;
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FIFO_ACTIVE :NODE;
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CLEAR_FIFO_CNT :DFF;
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STOP :DFF;
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DDR_REFRESH_ON :NODE;
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VIDEO_BASE_L_D[3..0] :DFFE;
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VIDEO_BASE_L :NODE;
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VIDEO_BASE_M_D[7..0] :DFFE;
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VIDEO_BASE_M :NODE;
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VIDEO_BASE_H_D[7..0] :DFFE;
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VIDEO_BASE_H :NODE;
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VIDEO_BASE_X_D[7..0] :DFFE;
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VIDEO_ADR_CNT[27..0] :DFFE;
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VIDEO_CNT_L :NODE;
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VIDEO_CNT_M :NODE;
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VIDEO_CNT_H :NODE;
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VIDEO_BASE_ADR[27..0] :NODE;
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BEGIN
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LINE = FB_SIZE0 & FB_SIZE1;
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-- BYT SELECT
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FB_B0 = FB_ADR[1..0]==0; -- ADR==0
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FB_B1 = FB_ADR[1..0]==1 -- ADR==1
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# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B2 = FB_ADR[1..0]==2 -- ADR==2
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B3 = FB_ADR[1..0]==3 -- ADR==3
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# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
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FB_REGDDR.CLK = MAIN_CLK;
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CASE FB_REGDDR IS
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WHEN FR_WAIT =>
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IF DDR_SEL THEN
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FB_REGDDR = FR_S0;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S0 =>
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FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
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FB_LE0 = !nFB_WR;
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IF LINE THEN
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FB_REGDDR = FR_S1;
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ELSE
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FB_REGDDR = FR_WAIT;
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END IF;
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WHEN FR_S1 =>
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FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
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FB_LE1 = !nFB_WR;
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FB_REGDDR = FR_S2;
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WHEN FR_S2 =>
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FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
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FB_LE2 = !nFB_WR;
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FB_REGDDR = FR_S3;
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WHEN FR_S3 =>
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FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
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FB_LE3 = !nFB_WR;
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FB_REGDDR = FR_WAIT;
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END CASE;
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-- DDR STEUERUNG -----------------------------------------------------
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-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
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VCKE = VIDEO_RAM_CTR0;
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nVCS = !VIDEO_RAM_CTR1;
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FIFO_ACTIVE = VIDEO_RAM_CTR2;
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DDR_CONFIG = VIDEO_RAM_CTR3;
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DDR_REFRESH_ON = VIDEO_RAM_CTR4;
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--------------------------------
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CPU_ROW_ADR[] = FB_ADR[26..14];
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CPU_BA1 = FB_ADR13;
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CPU_BA0 = FB_ADR12;
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CPU_COL_ADR[] = FB_ADR[11..2];
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nVRAS = !VRAS;
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nVCAS = !VCAS;
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nVWE = !VWE;
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DDR_WR.CLK = DDRCLK0;
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-- SELECT LOGIC
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DDR_SEL = FB_ALE & FB_AD[31..29]==B"011";
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-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
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CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS
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# FR_S0 & !nFB_WR -- WRITE SP<53>TER AUCH CONFIG
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# FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE
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CPU_REQ = CPU_SIG;
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CPU_REQ.CLK = DDR_SYNC_66M;
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DDR_D_SEL[].CLK = DDRCLK3;
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-- DDR STATE MACHINE -----------------------------------------------
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DDR_SM.CLK = DDRCLK0;
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CASE DDR_SM IS
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WHEN DS_T1 =>
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IF MAIN_CLK THEN
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DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4)
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DDR_SM = DS_T2;
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ELSE
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DDR_SM = DS_LS; -- SYNCHRONISIEREN
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END IF;
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WHEN DS_T2 =>
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IF !DDR_CONFIG THEN
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VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
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VA[] = CPU_SIG & CPU_ROW_ADR[]
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# BLITTER_SIG & BLITTER_ROW_ADR[]
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# FIFO_SIG & FIFO_ROW_ADR[];
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BA0 = CPU_SIG & CPU_BA0
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# BLITTER_SIG & BLITTER_BA0
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# FIFO_SIG & FIFO_BA0;
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BA1 = CPU_SIG & CPU_BA1
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# BLITTER_SIG & BLITTER_BA1
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# FIFO_SIG & FIFO_BA1;
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VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS
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BLITTER_REQ = BLITTER_SIG;
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FIFO_REQ = FIFO_SIG;
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END IF;
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IF MAIN_CLK THEN
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DDR_SM = DS_T3;
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ELSE
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DDR_SM = DS_LS;
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END IF;
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WHEN DS_T3 =>
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IF DDR_CONFIG & CPU_REQ THEN
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VRAS = FB_AD18;
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VCAS = FB_AD17;
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VWE = FB_AD16;
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BA1 = FB_AD14;
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BA0 = FB_AD13;
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VA[] = FB_AD[12..0];
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END IF;
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IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
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DDR_SM = DS_LS;
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ELSE
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BLITTER_REQ = BLITTER_SIG;
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FIFO_REQ = FIFO_SIG;
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DDR_SM = DS_T4;
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END IF;
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WHEN DS_T4 =>
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FIFO_REQ = FIFO_SIG;
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VCAS = VCC;
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VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
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VA[9..0] = CPU_REQ & CPU_COL_ADR[]
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# BLITTER_REQ & BLITTER_COL_ADR[]
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# FIFO_REQ & FIFO_COL_ADR[];
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VA10 = VCC; -- AUTO PRECHARGE
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BA0 = CPU_REQ & CPU_BA0
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# BLITTER_REQ & BLITTER_BA0
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# FIFO_REQ & FIFO_BA0;
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BA1 = CPU_REQ & CPU_BA1
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# BLITTER_REQ & BLITTER_BA1
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# FIFO_REQ & FIFO_BA1;
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DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
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FIFO_REQ = FIFO_SIG;
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IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
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DDR_SM = DS_T5; -- JA->
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ELSE
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DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
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END IF;
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WHEN DS_T5 =>
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FIFO_REQ = FIFO_SIG;
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DDR_SM = DS_T6;
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WHEN DS_T6 =>
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IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ
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VRAS = VCC;
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VA[] = CPU_ROW_ADR[];
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BA1 = CPU_BA1;
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BA0 = CPU_BA0;
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DDR_SM = DS_T3;
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ELSE
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FIFO_REQ = FIFO_SIG;
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VCAS = VCC;
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VA[9..0] = FIFO_COL_ADR[];
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VA10 = VCC; -- AUTO PRECHARGE
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BA0 = FIFO_BA0;
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BA1 = FIFO_BA1;
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FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133
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IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE?
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DDR_SM = DS_T5; -- JA->
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ELSE
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DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN
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END IF;
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END IF;
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WHEN DS_LS =>
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IF !MAIN_CLK THEN -- LEERSTATE UND SYNC
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DDR_SM = DS_T1;
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ELSE
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DDR_SM = DS_LS;
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END IF;
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END CASE;
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------------------------------------------------------------------------------
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-- FIFO ---------------------------------
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FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
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FIFO_REQ.CLK = DDR_SYNC_66M;
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FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
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FIFO_BA1 = VIDEO_ADR_CNT11;
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FIFO_BA0 = VIDEO_ADR_CNT10;
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FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
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-- Z<>HLER R<>CKSETZEN WENN VSYNC ----------------
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CLEAR_FIFO_CNT.CLK = DDRCLK0;
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CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
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STOP.CLK = DDRCLK0;
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STOP = VSYNC # CLEAR_FIFO_CNT;
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VIDEO_ADR_CNT[].CLK = DDRCLK0;
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VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET
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# !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS
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VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
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FIFO_WRE.CLK = DDRCLK0;
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---------------------------------------------------------------
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-- BLITTER BUS IST 128 BIT BREIT ------
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BLITTER_SIG = GND & !CPU_SIG;
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BLITTER_REQ.CLK = DDR_SYNC_66M;
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BLITTER_RUN.CLK = DDRCLK0;
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BLITTER_RUN = GND;
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BLITTER_WR.CLK = DDRCLK0;
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BLITTER_WR = GND;
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DDRWR_D_SEL1 = BLITTER_WR;
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BLITTER_ROW_ADR[] = H"0";
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BLITTER_BA1 = GND;
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BLITTER_BA0 = GND;
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BLITTER_COL_ADR[] = H"0";
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BLITTER_DOUT[] = H"0";
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BLITTER_LE[] = H"0";
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-----------------------------------------------------------
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-- VIDEO REGISTER -----------------------
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---------------------------------------------------------------------------------------------------------------------
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VIDEO_BASE_L_D[].CLK = MAIN_CLK;
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VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2
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VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN
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VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
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VIDEO_BASE_M_D[].CLK = MAIN_CLK;
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VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2
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VIDEO_BASE_M_D[] = FB_AD[23..16];
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VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
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VIDEO_BASE_H_D[].CLK = MAIN_CLK;
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VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2
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VIDEO_BASE_H_D[] = FB_AD[23..16];
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VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
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VIDEO_BASE_X_D[].CLK = MAIN_CLK;
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VIDEO_BASE_X_D[] = FB_AD[31..24];
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VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
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VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2
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VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2
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VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2
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FB_AD[31..24] = lpm_bustri_BYT(
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VIDEO_BASE_H & VIDEO_BASE_X_D[]
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# VIDEO_CNT_H & VIDEO_ADR_CNT[27..20]
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,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
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FB_AD[23..16] = lpm_bustri_BYT(
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VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000")
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# VIDEO_BASE_M & VIDEO_BASE_M_D[]
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# VIDEO_BASE_H & VIDEO_BASE_H_D[]
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# VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000")
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# VIDEO_CNT_M & VIDEO_ADR_CNT[11..4]
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# VIDEO_CNT_H & VIDEO_ADR_CNT[19..12]
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,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
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VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
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VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
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VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
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VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[];
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END;
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