Firebee/FPGA_Config
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This commit is contained in:
Markus Fröschle
2016-04-26 19:34:39 +00:00
parent fa4a3f686c
commit 1a972f2c64
2 changed files with 755 additions and 751 deletions
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10
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
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@@ -496,7 +496,7 @@ architecture rtl of video_mod_mux_clutctr is
-- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller -- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller
-- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise -- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise
function f_addr_cmp(addr_const : std_logic_vector; addr : std_logic_vector; ignore : integer) return boolean is function f_addr_cmp(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant ignore : integer) return boolean is
variable c_len : integer := addr_const'high; variable c_len : integer := addr_const'high;
variable a_len : integer := addr'high; variable a_len : integer := addr'high;
variable len : integer; variable len : integer;
@@ -1508,8 +1508,12 @@ begin
-- 3 zeilen vsync length -- 3 zeilen vsync length
-- runterzählen bis 0 -- runterzählen bis 0
VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or VSYNC_I_d <= x"3" when VSYNC_START_q = '1' else
((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= '0' else
(others => '0');
-- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or
-- ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3));
(VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0));
(VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1));