Firebee/FPGA_Config
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simplify processes

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This commit is contained in:
Markus Fröschle
2016-01-15 08:37:40 +00:00
parent f11629ac29
commit 11bd410c15
2 changed files with 29 additions and 19 deletions
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26
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
View File

@@ -603,25 +603,27 @@ BEGIN
VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0);
BEGIN BEGIN
FB_REGDDR_d <= FB_REGDDR_q; FB_REGDDR_d <= FB_REGDDR_q;
(FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); fb_vdoe <= (OTHERS => '0');
(FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), fb_le <= (OTHERS => '0');
VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); video_ddr_ta <= '0';
bus_cyc_end <= '0';
stdVec3 := FB_REGDDR_q; stdVec3 := FB_REGDDR_q;
CASE stdVec3 IS CASE stdVec3 IS
WHEN "000" => WHEN "000" =>
FB_LE(0) <= not nFB_WR; FB_LE(0) <= not nFB_WR;
-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' THEN IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' THEN
FB_REGDDR_d <= "001"; FB_REGDDR_d <= "001";
ELSE ELSE
FB_REGDDR_d <= "000"; FB_REGDDR_d <= "000";
END IF; END IF;
WHEN "001" => WHEN "001" =>
IF (DDR_CS_q)='1' THEN IF DDR_CS_q = '1' THEN
FB_LE(0) <= not nFB_WR; FB_LE(0) <= not nFB_WR;
VIDEO_DDR_TA <= vcc; VIDEO_DDR_TA <= vcc;
IF (LINE)='1' THEN IF LINE ='1' THEN
FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG);
FB_REGDDR_d <= "010"; FB_REGDDR_d <= "010";
ELSE ELSE
@@ -634,7 +636,7 @@ BEGIN
END IF; END IF;
WHEN "010" => WHEN "010" =>
IF (DDR_CS_q)='1' THEN IF DDR_CS_q = '1' THEN
FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG);
FB_LE(1) <= not nFB_WR; FB_LE(1) <= not nFB_WR;
VIDEO_DDR_TA <= vcc; VIDEO_DDR_TA <= vcc;
@@ -644,12 +646,12 @@ BEGIN
END IF; END IF;
WHEN "011" => WHEN "011" =>
IF (DDR_CS_q)='1' THEN IF DDR_CS_q ='1' THEN
FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG);
FB_LE(2) <= not nFB_WR; FB_LE(2) <= not nFB_WR;
-- BEI LINE WRITE EVT. WARTEN -- BEI LINE WRITE EVT. WARTEN
IF ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' THEN IF ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' THEN
FB_REGDDR_d <= "011"; FB_REGDDR_d <= "011";
ELSE ELSE
VIDEO_DDR_TA <= vcc; VIDEO_DDR_TA <= vcc;
@@ -660,7 +662,7 @@ BEGIN
END IF; END IF;
WHEN "100" => WHEN "100" =>
IF (DDR_CS_q)='1' THEN IF DDR_CS_q = '1' THEN
FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG);
FB_LE(3) <= not nFB_WR; FB_LE(3) <= not nFB_WR;
VIDEO_DDR_TA <= vcc; VIDEO_DDR_TA <= vcc;
@@ -672,7 +674,7 @@ BEGIN
WHEN others => WHEN others =>
END CASE; END CASE;
stdVec3 := (others=>'0'); -- no storage needed stdVec3 := (OTHERS => '0'); -- no storage needed
END PROCESS; END PROCESS;
-- DDR STEUERUNG ----------------------------------------------------- -- DDR STEUERUNG -----------------------------------------------------
@@ -690,6 +692,7 @@ BEGIN
nVRAS <= not VRAS; nVRAS <= not VRAS;
nVCAS <= not VCAS; nVCAS <= not VCAS;
nVWE <= not VWE; nVWE <= not VWE;
SR_DDR_WR_clk <= DDRCLK0; SR_DDR_WR_clk <= DDRCLK0;
SR_DDRWR_D_SEL_clk <= DDRCLK0; SR_DDRWR_D_SEL_clk <= DDRCLK0;
SR_VDMP0_clk_ctrl <= DDRCLK0; SR_VDMP0_clk_ctrl <= DDRCLK0;
@@ -697,6 +700,7 @@ BEGIN
CPU_AC_clk <= DDRCLK0; CPU_AC_clk <= DDRCLK0;
FIFO_AC_clk <= DDRCLK0; FIFO_AC_clk <= DDRCLK0;
BLITTER_AC_clk <= DDRCLK0; BLITTER_AC_clk <= DDRCLK0;
DDRWR_D_SEL1 <= BLITTER_AC_q; DDRWR_D_SEL1 <= BLITTER_AC_q;
-- SELECT LOGIC -- SELECT LOGIC

22
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -118,19 +118,25 @@ derive_clock_uncertainty
# Set Input Delay # Set Input Delay
#************************************************************** #**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} #set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#************************************************************** #**************************************************************
# Set Output Delay # Set Output Delay
#************************************************************** #**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}
#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
# video RAM access # video RAM access
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}]