From 0fe61bedef44acc3cbb068490696c7abb3019984 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 15 Jan 2016 17:38:29 +0000 Subject: [PATCH] fix output delay --- FPGA_Quartus_13.1/firebee1.sdc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index a8f4131..189849d 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -130,8 +130,8 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs # Set Output Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} @@ -139,20 +139,20 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_output #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} # video RAM access -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} #************************************************************** # Set Clock Groups