90 lines
3.8 KiB
C
90 lines
3.8 KiB
C
#ifndef _CACHE_H_
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#define _CACHE_H_
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/*
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* cache.h
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#include <bas_types.h>
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/*
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* CACR Cache Control Register
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*/
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#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
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#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
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#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
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#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
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#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
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#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
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#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
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#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
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#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
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#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
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#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
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#define CF_CACR_IVO (0x00100000) /* Invalidate only */
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#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
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#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
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#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
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#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
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#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
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#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
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#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
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#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
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#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
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#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
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#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
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#define CF_CACR_DF (0x00000010) /* Disable FPU */
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#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
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#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
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#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
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#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
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#define ICACHE_SIZE 0x8000 /* instruction - 32k */
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#define DCACHE_SIZE 0x8000 /* data - 32k */
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#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
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#define CACHE_SETS 0x0200 /* 512 sets */
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#define CACHE_WAYS 0x0004 /* 4 way */
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#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
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CF_CACR_BCINVA+ \
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CF_CACR_ICINVA)
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#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
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CF_CACR_BEC+ \
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CF_CACR_IEC+ \
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CF_CACR_DESB+ \
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CF_CACR_EUSP)
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extern void flush_and_invalidate_caches(void);
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extern uint32_t cacr_get(void);
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extern void cacr_set(uint32_t);
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extern void flush_icache_range(void *address, size_t size);
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extern void flush_dcache_range(void *address, size_t size);
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extern void flush_cache_range(void *address, size_t size);
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#endif /* _CACHE_H_ */
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