1037 lines
36 KiB
C
1037 lines
36 KiB
C
/*
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
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* VA Linux Systems Inc., Fremont, California.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors:
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* Kevin E. Martin <martin@xfree86.org>
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* Rickard E. Faith <faith@valinux.com>
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* Alan Hourihane <alanh@fairlite.demon.co.uk>
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*
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* Credits:
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*
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* Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source
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* code to his Radeon driver. Portions of this file are based on the
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* initialization code for that driver.
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*
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* References:
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*
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* !!!! FIXME !!!!
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* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
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* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
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* 1999.
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*
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* RAGE 128 Software Development Manual (Technical Reference Manual P/N
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* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
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*
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* Notes on unimplemented XAA optimizations:
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*
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* SetClipping: This has been removed as XAA expects 16bit registers
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* for full clipping.
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* TwoPointLine: The Radeon supports this. Not Bresenham.
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* DashedLine with non-power-of-two pattern length: Apparently, there is
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* no way to set the length of the pattern -- it is always
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* assumed to be 8 or 32 (or 1024?).
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* ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference
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* Manual where it states that monochrome expansion of frame
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* buffer data is not supported.
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* Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8
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* pattern from frame buffer memory.
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*
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*/
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// #define DEBUG
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#include "debug.h"
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#include "fb.h"
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#include "radeonfb.h"
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static struct {
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int32_t rop;
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int32_t pattern;
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} RADEON_ROP[] = {
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{ ROP3_ZERO, ROP3_ZERO }, /* GXclear */
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{ ROP3_DSa, ROP3_DPa }, /* Gxand */
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{ ROP3_SDna, ROP3_PDna }, /* GXandReverse */
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{ ROP3_S, ROP3_P }, /* GXcopy */
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{ ROP3_DSna, ROP3_DPna }, /* GXandInverted */
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{ ROP3_D, ROP3_D }, /* GXnoop */
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{ ROP3_DSx, ROP3_DPx }, /* GXxor */
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{ ROP3_DSo, ROP3_DPo }, /* GXor */
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{ ROP3_DSon, ROP3_DPon }, /* GXnor */
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{ ROP3_DSxn, ROP3_PDxn }, /* GXequiv */
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{ ROP3_Dn, ROP3_Dn }, /* GXinvert */
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{ ROP3_SDno, ROP3_PDno }, /* GXorReverse */
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{ ROP3_Sn, ROP3_Pn }, /* GXcopyInverted */
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{ ROP3_DSno, ROP3_DPno }, /* GXorInverted */
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{ ROP3_DSan, ROP3_DPan }, /* GXnand */
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{ ROP3_ONE, ROP3_ONE } /* GXset */
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};
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#define ACCEL_MMIO
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#define ACCEL_PREAMBLE()
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#define BEGIN_ACCEL(n) radeon_wait_for_fifo(rinfo, (n))
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#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
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#define FINISH_ACCEL()
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/* MMIO:
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*
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* Wait for the graphics engine to be completely idle: the FIFO has
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* drained, the Pixel Cache is flushed, and the engine is idle. This is
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* a standard "sync" function that will make the hardware "quiescent".
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*/
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void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo)
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{
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int32_t i = 0;
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/* Wait for the engine to go idle */
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radeon_wait_for_fifo_function(rinfo, 64);
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while(1)
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{
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for(i = 0; i < RADEON_TIMEOUT; i++)
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{
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if (!(INREG(RBBM_STATUS) & RBBM_ACTIVE))
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{
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radeon_engine_flush(rinfo);
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return;
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}
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}
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radeon_engine_reset(rinfo);
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radeon_engine_restore(rinfo);
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}
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}
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#if 0
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/* This callback is required for multiheader cards using XAA */
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void RADEONRestoreAccelStateMMIO(struct fb_info *info)
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{
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struct radeonfb_info *rinfo = info->par;
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// unsigned long pitch64 = ((info->var.xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
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OUTREG(DEFAULT_OFFSET, (((INREG(DISPLAY_BASE_ADDR) + rinfo->fb_local_base) >> 10) | (rinfo->pitch << 22)));
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/* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */
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RADEONWaitForIdleMMIO(rinfo);
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}
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#endif
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/* Setup for XAA SolidFill */
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void radeon_setup_for_solid_fill(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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/* Save for later clipping */
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rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
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| GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].pattern);
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BEGIN_ACCEL(4);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
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OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, color);
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OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
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OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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FINISH_ACCEL();
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}
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/* Subsequent XAA SolidFillRect */
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void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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#ifdef RADEON_TILING
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
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| ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
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#else
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BEGIN_ACCEL(2);
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#endif
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OUT_ACCEL_REG(DST_Y_X, (y << 16) | x);
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OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (w << 16) | h);
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FINISH_ACCEL();
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}
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/* Setup for XAA solid lines */
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void radeon_setup_for_solid_line_mmio(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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/* Save for later clipping */
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rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
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| GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].pattern);
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if (rinfo->family >= CHIP_FAMILY_RV200)
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{
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BEGIN_ACCEL(1);
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OUT_ACCEL_REG(DST_LINE_PATCOUNT, 0x55 << BRES_CNTL_SHIFT);
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}
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
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OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, color);
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OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
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FINISH_ACCEL();
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}
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/* Subsequent XAA solid horizontal and vertical lines */
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void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir)
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{
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struct radeonfb_info *rinfo = info->par;
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int32_t w = 1;
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int32_t h = 1;
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ACCEL_PREAMBLE();
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if (dir == DEGREES_0)
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w = len;
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else
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h = len;
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#ifdef RADEON_TILING
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BEGIN_ACCEL(4);
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OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
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| ((rinfo->tilingEnabled && (y <= info->var.xres_virtual)) ? DST_TILE_MACRO : 0));
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#else
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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#endif
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OUT_ACCEL_REG(DST_Y_X, (y << 16) | x);
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OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (w << 16) | h);
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FINISH_ACCEL();
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}
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/* Subsequent XAA solid TwoPointLine line */
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void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info,
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int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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/* TODO: Check bounds -- RADEON only has 14 bits */
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if (!(flags & OMIT_LAST))
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radeon_subsequent_solid_hor_vert_line_mmio(info, xb, yb, 1, DEGREES_0);
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#ifdef RADEON_TILING
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
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| ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
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#else
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BEGIN_ACCEL(2);
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#endif
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OUT_ACCEL_REG(DST_LINE_START, (ya << 16) | xa);
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OUT_ACCEL_REG(DST_LINE_END, (yb << 16) | xb);
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FINISH_ACCEL();
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}
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/* Setup for XAA dashed lines
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* NOTE: Since we can only accelerate lines with power-of-2 patterns of * length <= 32
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*/
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void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int32_t fg, int32_t bg,
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int32_t rop, uint32_t planemask, int32_t length, unsigned char *pattern)
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{
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struct radeonfb_info *rinfo = info->par;
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unsigned long pat = *(unsigned long *) pattern;
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ACCEL_PREAMBLE();
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/* Save for determining whether or not to draw last pixel */
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rinfo->dashLen = length;
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rinfo->dashPattern = pat;
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if (rinfo->big_endian)
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{
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switch (length)
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{
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case 2: pat |= (pat >> 2); /* fall through */
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case 4: pat |= (pat >> 4); /* fall through */
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case 8: pat |= (pat >> 8); /* fall through */
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case 16: pat |= (pat >> 16);
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}
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}
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else
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{
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switch (length)
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{
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case 2: pat |= (pat << 2); /* fall through */
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case 4: pat |= (pat << 4); /* fall through */
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case 8: pat |= (pat << 8); /* fall through */
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case 16: pat |= (pat << 16);
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}
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}
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/* Save for later clipping */
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rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
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| (bg == -1 ? GMC_BRUSH_32X1_MONO_FG_LA : GMC_BRUSH_32X1_MONO_FG_BG)
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| RADEON_ROP[rop].pattern | GMC_BYTE_LSB_TO_MSB);
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rinfo->dash_fg = fg;
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rinfo->dash_bg = bg;
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BEGIN_ACCEL((bg == -1) ? 4 : 5);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
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OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
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OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg);
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if (bg != -1)
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OUT_ACCEL_REG(DP_BRUSH_BKGD_CLR, bg);
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OUT_ACCEL_REG(BRUSH_DATA0, pat);
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FINISH_ACCEL();
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}
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/* Helper function to draw last point for dashed lines */
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static void RADEONDashedLastPelMMIO(struct fb_info *info,
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int32_t x, int32_t y, int32_t fg)
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{
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struct radeonfb_info *rinfo = info->par;
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unsigned long dp_gui_master_cntl = rinfo->dp_gui_master_cntl_clip;
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ACCEL_PREAMBLE();
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dp_gui_master_cntl &= ~GMC_BRUSH_DATATYPE_MASK;
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dp_gui_master_cntl |= GMC_BRUSH_SOLID_COLOR;
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dp_gui_master_cntl &= ~GMC_SRC_DATATYPE_MASK;
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dp_gui_master_cntl |= GMC_SRC_DATATYPE_COLOR;
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#ifdef RADEON_TILING
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BEGIN_ACCEL(8);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, dp_gui_master_cntl);
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OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
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| ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
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#else
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BEGIN_ACCEL(7);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, dp_gui_master_cntl);
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OUT_ACCEL_REG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
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#endif
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OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg);
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OUT_ACCEL_REG(DST_Y_X, (y << 16) | x);
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OUT_ACCEL_REG(DST_WIDTH_HEIGHT, (1 << 16) | 1);
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/* Restore old values */
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
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OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, rinfo->dash_fg);
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FINISH_ACCEL();
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}
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/* Subsequent XAA dashed line */
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void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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/* TODO: Check bounds -- RADEON only has 14 bits */
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if (!(flags & OMIT_LAST))
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{
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int32_t deltax = xa - xb;
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int32_t deltay = ya - yb;
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int32_t shift;
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if (deltax < 0)
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deltax = -deltax;
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if (deltay < 0)
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deltay = -deltay;
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if (deltax > deltay)
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shift = deltax;
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else
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shift = deltay;
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shift += phase;
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shift %= rinfo->dashLen;
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if ((rinfo->dashPattern >> shift) & 1)
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RADEONDashedLastPelMMIO(info, xb, yb, rinfo->dash_fg);
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else if (rinfo->dash_bg != -1)
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RADEONDashedLastPelMMIO(info, xb, yb, rinfo->dash_bg);
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}
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#ifdef RADEON_TILING
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BEGIN_ACCEL(4);
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OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
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| ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
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#else
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BEGIN_ACCEL(3);
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#endif
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OUT_ACCEL_REG(DST_LINE_START, (ya << 16) | xa);
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OUT_ACCEL_REG(DST_LINE_PATCOUNT, phase);
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OUT_ACCEL_REG(DST_LINE_END, (yb << 16) | xb);
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FINISH_ACCEL();
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}
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/* Set up for transparency
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*
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* Mmmm, Seems as though the transparency compare is opposite to r128.
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* It should only draw when source != trans_color, this is the opposite
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* of that.
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*/
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static void radeon_set_transparency_mmio(struct radeonfb_info *rinfo, int32_t trans_color)
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{
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if (trans_color != -1)
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{
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ACCEL_PREAMBLE();
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(CLR_CMP_CLR_SRC, trans_color);
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OUT_ACCEL_REG(CLR_CMP_MSK, 0xffffffff);
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OUT_ACCEL_REG(CLR_CMP_CNTL, (SRC_CMP_EQ_COLOR | CLR_CMP_SRC_SOURCE));
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FINISH_ACCEL();
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}
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}
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/* Setup for XAA screen-to-screen copy */
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void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
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int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color)
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{
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struct radeonfb_info *rinfo = info->par;
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ACCEL_PREAMBLE();
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rinfo->xdir = xdir;
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rinfo->ydir = ydir;
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/* Save for later clipping */
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#ifdef RADEON_TILING
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rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
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| GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop
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| DP_SRC_SOURCE_MEMORY | GMC_SRC_PITCH_OFFSET_CNTL);
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#else
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rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
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| GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop | DP_SRC_SOURCE_MEMORY);
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#endif
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BEGIN_ACCEL(3);
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OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
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OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
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OUT_ACCEL_REG(DP_CNTL, ((xdir >= 0 ? DST_X_LEFT_TO_RIGHT : 0) | (ydir >= 0 ? DST_Y_TOP_TO_BOTTOM : 0)));
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FINISH_ACCEL();
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rinfo->trans_color = trans_color;
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if (trans_color != -1)
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radeon_set_transparency_mmio(rinfo, trans_color);
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}
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/* Subsequent XAA screen-to-screen copy */
|
|
void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
ACCEL_PREAMBLE();
|
|
if (rinfo->xdir < 0)
|
|
xa += w - 1, xb += w - 1;
|
|
|
|
if (rinfo->ydir < 0)
|
|
ya += h - 1, yb += h - 1;
|
|
|
|
#ifdef RADEON_TILING
|
|
BEGIN_ACCEL(5);
|
|
OUT_ACCEL_REG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (yb <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
#else
|
|
BEGIN_ACCEL(3);
|
|
#endif
|
|
OUT_ACCEL_REG(SRC_Y_X, (ya << 16) | xa);
|
|
OUT_ACCEL_REG(DST_Y_X, (yb << 16) | xb);
|
|
OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w);
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* XAA screen-to-screen copy */
|
|
void radeon_screen_to_screen_copy_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
int32_t xdir = xa - xb;
|
|
int32_t ydir = ya - yb;
|
|
ACCEL_PREAMBLE();
|
|
if (xdir < 0)
|
|
xa += w - 1, xb += w - 1;
|
|
if (ydir < 0)
|
|
ya += h - 1, yb += h - 1;
|
|
#ifdef RADEON_TILING
|
|
/* Save for later clipping */
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop
|
|
| DP_SRC_SOURCE_MEMORY | GMC_SRC_PITCH_OFFSET_CNTL);
|
|
BEGIN_ACCEL(8);
|
|
|
|
OUT_ACCEL_REG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (ya <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (yb <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
#else
|
|
/* Save for later clipping */
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop | DP_SRC_SOURCE_MEMORY);
|
|
BEGIN_ACCEL(6);
|
|
#endif
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
|
|
OUT_ACCEL_REG(DP_WRITE_MSK, -1);
|
|
OUT_ACCEL_REG(DP_CNTL, ((xdir >= 0 ? DST_X_LEFT_TO_RIGHT : 0) | (ydir >= 0 ? DST_Y_TOP_TO_BOTTOM : 0)));
|
|
OUT_ACCEL_REG(SRC_Y_X, (ya << 16) | xa);
|
|
OUT_ACCEL_REG(DST_Y_X, (yb << 16) | xb);
|
|
OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w);
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Setup for XAA mono 8x8 pattern color expansion. Patterns with
|
|
* transparency use `bg == -1'. This routine is only used if the XAA
|
|
* pixmap cache is turned on.
|
|
*/
|
|
void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, int32_t patternx, int32_t patterny,
|
|
int32_t fg, int32_t bg, int32_t rop, uint32_t planemask)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
unsigned char pattern[8];
|
|
|
|
ACCEL_PREAMBLE();
|
|
if (rinfo->big_endian)
|
|
{
|
|
/* Take care of endianness */
|
|
pattern[0] = (patternx & 0x000000ff);
|
|
pattern[1] = (patternx & 0x0000ff00) >> 8;
|
|
pattern[2] = (patternx & 0x00ff0000) >> 16;
|
|
pattern[3] = (patternx & 0xff000000) >> 24;
|
|
pattern[4] = (patterny & 0x000000ff);
|
|
pattern[5] = (patterny & 0x0000ff00) >> 8;
|
|
pattern[6] = (patterny & 0x00ff0000) >> 16;
|
|
pattern[7] = (patterny & 0xff000000) >> 24;
|
|
/* Save for later clipping */
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| (bg == -1 ? GMC_BRUSH_8X8_MONO_FG_LA : GMC_BRUSH_8X8_MONO_FG_BG)
|
|
| RADEON_ROP[rop].pattern | GMC_BYTE_MSB_TO_LSB);
|
|
}
|
|
else
|
|
/* Save for later clipping */
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| (bg == -1 ? GMC_BRUSH_8X8_MONO_FG_LA : GMC_BRUSH_8X8_MONO_FG_BG)
|
|
| RADEON_ROP[rop].pattern);
|
|
BEGIN_ACCEL((bg == -1) ? 5 : 6);
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
|
|
OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
|
|
OUT_ACCEL_REG(DP_BRUSH_FRGD_CLR, fg);
|
|
if (bg != -1)
|
|
OUT_ACCEL_REG(DP_BRUSH_BKGD_CLR, bg);
|
|
if (rinfo->big_endian)
|
|
{
|
|
OUT_ACCEL_REG(BRUSH_DATA0, &pattern[0]);
|
|
OUT_ACCEL_REG(BRUSH_DATA1, &pattern[4]);
|
|
}
|
|
else
|
|
{
|
|
OUT_ACCEL_REG(BRUSH_DATA0, patternx);
|
|
OUT_ACCEL_REG(BRUSH_DATA1, patterny);
|
|
}
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Subsequent XAA 8x8 pattern color expansion. Because they are used in
|
|
* the setup function, `patternx' and `patterny' are not used here.
|
|
*/
|
|
void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, int32_t patternx, int32_t patterny,
|
|
int32_t x, int32_t y, int32_t w, int32_t h)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
ACCEL_PREAMBLE();
|
|
#ifdef RADEON_TILING
|
|
BEGIN_ACCEL(4);
|
|
OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
#else
|
|
BEGIN_ACCEL(3);
|
|
#endif
|
|
OUT_ACCEL_REG(BRUSH_Y_X, (patterny << 8) | patternx);
|
|
OUT_ACCEL_REG(DST_Y_X, (y << 16) | x);
|
|
OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | w);
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Setup for XAA indirect CPU-to-screen color expansion (indirect).
|
|
* Because of how the scratch buffer is initialized, this is really a
|
|
* mainstore-to-screen color expansion. Transparency is supported when
|
|
* `bg == -1'.
|
|
*/
|
|
void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
|
int32_t fg, int32_t bg, int32_t rop, uint32_t planemask)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
ACCEL_PREAMBLE();
|
|
/* Save for later clipping */
|
|
if (rinfo->big_endian)
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| GMC_DST_CLIPPING | GMC_BRUSH_NONE
|
|
| (bg == -1 ? GMC_SRC_DATATYPE_MONO_FG_LA : GMC_SRC_DATATYPE_MONO_FG_BG)
|
|
| RADEON_ROP[rop].rop | GMC_BYTE_MSB_TO_LSB | DP_SRC_SOURCE_HOST_DATA);
|
|
else
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| GMC_DST_CLIPPING | GMC_BRUSH_NONE
|
|
| (bg == -1 ? GMC_SRC_DATATYPE_MONO_FG_LA : GMC_SRC_DATATYPE_MONO_FG_BG)
|
|
| RADEON_ROP[rop].rop | GMC_BYTE_LSB_TO_MSB | DP_SRC_SOURCE_HOST_DATA);
|
|
if (rinfo->big_endian)
|
|
{
|
|
BEGIN_ACCEL(5);
|
|
OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_NONE);
|
|
}
|
|
else
|
|
BEGIN_ACCEL(4);
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
|
|
OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
|
|
OUT_ACCEL_REG(DP_SRC_FRGD_CLR, fg);
|
|
OUT_ACCEL_REG(DP_SRC_BKGD_CLR, bg);
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Subsequent XAA indirect CPU-to-screen color expansion. This is only
|
|
* called once for each rectangle.
|
|
*/
|
|
void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
|
int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
ACCEL_PREAMBLE();
|
|
rinfo->scanline_h = h;
|
|
rinfo->scanline_words = (w + 31) >> 5;
|
|
#ifdef RADEON_TILING
|
|
BEGIN_ACCEL(5);
|
|
OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
#else
|
|
BEGIN_ACCEL(4);
|
|
#endif
|
|
OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x + skipleft) & 0xffff));
|
|
OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x + w) & 0xffff));
|
|
OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
|
|
/* Have to pad the width here and use clipping engine */
|
|
OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + 31) & ~31));
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Subsequent XAA indirect CPU-to-screen color expansion and indirect
|
|
* image write. This is called once for each scanline.
|
|
*/
|
|
void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *src)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
int32_t left = rinfo->scanline_words;
|
|
volatile unsigned long *d;
|
|
ACCEL_PREAMBLE();
|
|
--rinfo->scanline_h;
|
|
while(left)
|
|
{
|
|
if (left <= 8)
|
|
{
|
|
/* Last scanline - finish write to DATA_LAST */
|
|
if (rinfo->scanline_h == 0)
|
|
{
|
|
BEGIN_ACCEL(left);
|
|
/* Unrolling doesn't improve performance */
|
|
for (d = ADDRREG(HOST_DATA_LAST) - (left - 1); left; --left)
|
|
*d++ = *src++;
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
BEGIN_ACCEL(left);
|
|
/* Unrolling doesn't improve performance */
|
|
for(d = ADDRREG(HOST_DATA7) - (left - 1); left; --left)
|
|
*d++ = *src++;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
BEGIN_ACCEL(8);
|
|
/* Unrolling doesn't improve performance */
|
|
d = ADDRREG(HOST_DATA0);
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
*d++ = *src++;
|
|
left -= 8;
|
|
}
|
|
}
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Setup for XAA indirect image write */
|
|
void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, int32_t rop, uint32_t planemask,
|
|
int32_t trans_color, int32_t bpp)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
ACCEL_PREAMBLE();
|
|
rinfo->scanline_bpp = bpp;
|
|
/* Save for later clipping */
|
|
rinfo->dp_gui_master_cntl_clip = (rinfo->dp_gui_master_cntl
|
|
| GMC_DST_CLIPPING | GMC_BRUSH_NONE | GMC_SRC_DATATYPE_COLOR | RADEON_ROP[rop].rop
|
|
| GMC_BYTE_MSB_TO_LSB | DP_SRC_SOURCE_HOST_DATA);
|
|
if (rinfo->big_endian)
|
|
{
|
|
BEGIN_ACCEL(3);
|
|
if (bpp == 16)
|
|
OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_16BIT);
|
|
else if (bpp == 32)
|
|
OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_32BIT);
|
|
else
|
|
OUT_ACCEL_REG(RBBM_GUICNTL, HOST_DATA_SWAP_NONE);
|
|
}
|
|
else
|
|
BEGIN_ACCEL(2);
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
|
|
OUT_ACCEL_REG(DP_WRITE_MSK, planemask);
|
|
FINISH_ACCEL();
|
|
rinfo->trans_color = trans_color;
|
|
if (trans_color != -1)
|
|
radeon_set_transparency_mmio(rinfo, trans_color);
|
|
}
|
|
|
|
/* Subsequent XAA indirect image write. This is only called once for each rectangle. */
|
|
void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
int32_t shift = 0; /* 32bpp */
|
|
ACCEL_PREAMBLE();
|
|
if (rinfo->bpp == 8)
|
|
shift = 3;
|
|
else if (rinfo->bpp == 16)
|
|
shift = 1;
|
|
rinfo->scanline_h = h;
|
|
rinfo->scanline_words = (w * rinfo->scanline_bpp + 31) >> 5;
|
|
#ifdef RADEON_TILING
|
|
BEGIN_ACCEL(5);
|
|
OUT_ACCEL_REG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset
|
|
| ((rinfo->tilingEnabled && (y <= info->var.yres_virtual)) ? DST_TILE_MACRO : 0));
|
|
#else
|
|
BEGIN_ACCEL(4);
|
|
#endif
|
|
OUT_ACCEL_REG(SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
|
|
OUT_ACCEL_REG(SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
|
|
OUT_ACCEL_REG(DST_Y_X, (y << 16) | (x & 0xffff));
|
|
/* Have to pad the width here and use clipping engine */
|
|
OUT_ACCEL_REG(DST_HEIGHT_WIDTH, (h << 16) | ((w + shift) & ~shift));
|
|
FINISH_ACCEL();
|
|
}
|
|
|
|
/* Set up the clipping rectangle */
|
|
void radeon_set_clipping_rectangle_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
unsigned long tmp1 = 0;
|
|
unsigned long tmp2 = 0;
|
|
ACCEL_PREAMBLE();
|
|
if (xa < 0)
|
|
{
|
|
tmp1 = (-xa) & 0x3fff;
|
|
tmp1 |= SC_SIGN_MASK_LO;
|
|
}
|
|
else
|
|
tmp1 = xa;
|
|
if (ya < 0)
|
|
{
|
|
tmp1 |= (((-ya) & 0x3fff) << 16);
|
|
tmp1 |= SC_SIGN_MASK_HI;
|
|
}
|
|
else
|
|
tmp1 |= (ya << 16);
|
|
xb++; yb++;
|
|
if (xb < 0)
|
|
{
|
|
tmp2 = (-xb) & 0x3fff;
|
|
tmp2 |= SC_SIGN_MASK_LO;
|
|
}
|
|
else
|
|
tmp2 = xb;
|
|
if (yb < 0)
|
|
{
|
|
tmp2 |= (((-yb) & 0x3fff) << 16);
|
|
tmp2 |= SC_SIGN_MASK_HI;
|
|
}
|
|
else
|
|
tmp2 |= (yb << 16);
|
|
BEGIN_ACCEL(3);
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl_clip | GMC_DST_CLIPPING));
|
|
OUT_ACCEL_REG(SC_TOP_LEFT, tmp1);
|
|
OUT_ACCEL_REG(SC_BOTTOM_RIGHT, tmp2);
|
|
FINISH_ACCEL();
|
|
if (rinfo->trans_color != -1)
|
|
radeon_set_transparency_mmio(rinfo, rinfo->trans_color);
|
|
}
|
|
|
|
/* Disable the clipping rectangle */
|
|
void radeon_disable_clipping_mmio(struct fb_info *info)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
|
|
ACCEL_PREAMBLE();
|
|
BEGIN_ACCEL(3);
|
|
OUT_ACCEL_REG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_master_cntl_clip);
|
|
OUT_ACCEL_REG(SC_TOP_LEFT, 0);
|
|
OUT_ACCEL_REG(SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX));
|
|
FINISH_ACCEL();
|
|
if (rinfo->trans_color != -1)
|
|
radeon_set_transparency_mmio(rinfo, rinfo->trans_color);
|
|
}
|
|
|
|
#if 0
|
|
|
|
/* Change surfaces
|
|
The idea here is to only set up front buffer as tiled, and back/depth buffer when needed.
|
|
Everything else is left as untiled. This means we need to use eplicit src/dst pitch control
|
|
when blitting, based on the src/target address, and can no longer use a default offset.
|
|
But OTOH we don't need to dynamically change surfaces (for xv for instance), and some
|
|
ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works...
|
|
All surface addresses are relative to MC_FB_LOCATION
|
|
*/
|
|
void RADEONChangeSurfaces(struct fb_info *info)
|
|
{
|
|
struct radeonfb_info *rinfo = info->par;
|
|
int32_t cpp = rinfo->bpp >> 3;
|
|
/* depth/front/back pitch must be identical (and the same as displayWidth) */
|
|
int32_t width_bytes = info->var.xres_virtual * cpp;
|
|
int32_t bufferSize = (((((info->var.yres_virtual + 15) & ~15) * width_bytes) + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
|
|
uint32_t depth_pattern, color_pattern, swap_pattern, surf_info;
|
|
if (rinfo->big_endian)
|
|
{
|
|
switch(rinfo->bpp)
|
|
{
|
|
case 16:
|
|
swap_pattern = SURF_AP0_SWP_16BPP | SURF_AP1_SWP_16BPP;
|
|
break;
|
|
case 32:
|
|
swap_pattern = SURF_AP0_SWP_32BPP | SURF_AP1_SWP_32BPP;
|
|
break;
|
|
default:
|
|
swap_pattern = 0;
|
|
}
|
|
}
|
|
else
|
|
swap_pattern = 0;
|
|
if (rinfo->family < CHIP_FAMILY_R200)
|
|
{
|
|
color_pattern = SURF_TILE_COLOR_MACRO;
|
|
if (cpp == 2)
|
|
depth_pattern = SURF_TILE_DEPTH_16BPP;
|
|
else
|
|
depth_pattern = SURF_TILE_DEPTH_32BPP;
|
|
}
|
|
else if (rinfo->family >= CHIP_FAMILY_R300)
|
|
{
|
|
color_pattern = R300_SURF_TILE_COLOR_MACRO;
|
|
if (cpp == 2)
|
|
depth_pattern = R300_SURF_TILE_COLOR_MACRO;
|
|
else
|
|
depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP;
|
|
}
|
|
else
|
|
{
|
|
color_pattern = R200_SURF_TILE_COLOR_MACRO;
|
|
if (cpp == 2)
|
|
depth_pattern = R200_SURF_TILE_DEPTH_16BPP;
|
|
else
|
|
depth_pattern = R200_SURF_TILE_DEPTH_32BPP;
|
|
}
|
|
/* we don't need anything like WaitForFifo, no? */
|
|
#ifdef RADEON_TILING
|
|
if (rinfo->tilingEnabled)
|
|
{
|
|
if (rinfo->family >= CHIP_FAMILY_R300)
|
|
surf_info = swap_pattern | (width_bytes / 8) | color_pattern;
|
|
else
|
|
surf_info = swap_pattern | (width_bytes / 16) | color_pattern;
|
|
}
|
|
else
|
|
#endif
|
|
surf_info = 0;
|
|
OUTREG(SURFACE0_INFO, surf_info);
|
|
OUTREG(SURFACE0_LOWER_BOUND, 0);
|
|
OUTREG(SURFACE0_UPPER_BOUND, bufferSize - 1);
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* The FIFO has 64 slots. This routines waits until at least `entries'
|
|
* of these slots are empty.
|
|
*/
|
|
void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int32_t entries)
|
|
{
|
|
int32_t i;
|
|
while(1)
|
|
{
|
|
for(i = 0; i < RADEON_TIMEOUT; i++)
|
|
{
|
|
rinfo->fifo_slots = INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK;
|
|
if (rinfo->fifo_slots >= entries)
|
|
return;
|
|
}
|
|
radeon_engine_reset(rinfo);
|
|
radeon_engine_restore(rinfo);
|
|
}
|
|
}
|
|
|
|
/* Flush all dirty data in the Pixel Cache to memory */
|
|
void radeon_engine_flush(struct radeonfb_info *rinfo)
|
|
{
|
|
int32_t i;
|
|
OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, ~RB2D_DC_FLUSH_ALL);
|
|
for(i = 0; i < RADEON_TIMEOUT; i++)
|
|
{
|
|
if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Reset graphics card to known state
|
|
*/
|
|
void radeon_engine_reset(struct radeonfb_info *rinfo)
|
|
{
|
|
unsigned long clock_cntl_index;
|
|
unsigned long mclk_cntl;
|
|
unsigned long rbbm_soft_reset;
|
|
unsigned long host_path_cntl;
|
|
|
|
radeon_engine_flush(rinfo);
|
|
clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
|
|
/* Some ASICs have bugs with dynamic-on feature, which are
|
|
* ASIC-version dependent, so we force all blocks on for now
|
|
*/
|
|
if (rinfo->has_CRTC2)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
tmp = INPLL(SCLK_CNTL);
|
|
OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) | CP_MAX_DYN_STOP_LAT | SCLK_FORCEON_MASK));
|
|
if (rinfo->family == CHIP_FAMILY_RV200)
|
|
{
|
|
tmp = INPLL(SCLK_MORE_CNTL);
|
|
OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);
|
|
}
|
|
}
|
|
mclk_cntl = INPLL(MCLK_CNTL);
|
|
OUTPLL(MCLK_CNTL, (mclk_cntl | FORCEON_MCLKA
|
|
| FORCEON_MCLKB
|
|
| FORCEON_YCLKA
|
|
| FORCEON_YCLKB
|
|
| FORCEON_MC
|
|
| FORCEON_AIC));
|
|
|
|
/*
|
|
* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
|
|
* unexpected behaviour on some machines. Here we use
|
|
* HOST_PATH_CNTL to reset it.
|
|
*/
|
|
host_path_cntl = INREG(HOST_PATH_CNTL);
|
|
|
|
rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
|
|
if ((rinfo->family == CHIP_FAMILY_R300) || (rinfo->family == CHIP_FAMILY_R350)
|
|
|| (rinfo->family == CHIP_FAMILY_RV350))
|
|
{
|
|
unsigned long tmp;
|
|
|
|
OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_E2));
|
|
INREG(RBBM_SOFT_RESET);
|
|
OUTREG(RBBM_SOFT_RESET, 0);
|
|
tmp = INREG(RB2D_DSTCACHE_MODE);
|
|
OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
|
|
}
|
|
else
|
|
{
|
|
OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | SOFT_RESET_CP
|
|
| SOFT_RESET_HI | SOFT_RESET_SE | SOFT_RESET_RE
|
|
| SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB));
|
|
|
|
INREG(RBBM_SOFT_RESET);
|
|
|
|
OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset & (unsigned long) ~(SOFT_RESET_CP | SOFT_RESET_HI | SOFT_RESET_SE
|
|
| SOFT_RESET_RE | SOFT_RESET_PP | SOFT_RESET_E2 | SOFT_RESET_RB)));
|
|
INREG(RBBM_SOFT_RESET);
|
|
}
|
|
OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
|
|
INREG(HOST_PATH_CNTL);
|
|
OUTREG(HOST_PATH_CNTL, host_path_cntl);
|
|
|
|
if ((rinfo->family != CHIP_FAMILY_R300)
|
|
&& (rinfo->family != CHIP_FAMILY_R350)
|
|
&& (rinfo->family != CHIP_FAMILY_RV350))
|
|
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
|
|
|
|
OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
|
OUTPLL(MCLK_CNTL, mclk_cntl);
|
|
}
|
|
|
|
/*
|
|
* Restore the acceleration hardware to its previous state
|
|
*/
|
|
void radeon_engine_restore(struct radeonfb_info *rinfo)
|
|
{
|
|
BEGIN_ACCEL(1);
|
|
/* NOTE: The following RB2D_DSTCACHE_MODE setting will cause the
|
|
* R300 to hang. ATI does not see a reason to change it from the
|
|
* default BIOS settings (even on non-R300 cards). This setting
|
|
* might be removed in future versions of the Radeon driver.
|
|
*/
|
|
/* Turn of all automatic flushing - we'll do it all */
|
|
if ((rinfo->family != CHIP_FAMILY_R300)
|
|
&& (rinfo->family != CHIP_FAMILY_R350)
|
|
&& (rinfo->family != CHIP_FAMILY_RV350))
|
|
OUTREG(RB2D_DSTCACHE_MODE, 0);
|
|
|
|
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
|
|
|
|
BEGIN_ACCEL(3);
|
|
OUTREG(DEFAULT_PITCH_OFFSET, rinfo->dst_pitch_offset);
|
|
OUTREG(DST_PITCH_OFFSET, rinfo->dst_pitch_offset);
|
|
OUTREG(SRC_PITCH_OFFSET, rinfo->dst_pitch_offset);
|
|
|
|
BEGIN_ACCEL(1);
|
|
if (rinfo->big_endian)
|
|
OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
|
|
else
|
|
OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
|
|
/* Restore SURFACE_CNTL - only the first head contains valid data */
|
|
OUTREG(SURFACE_CNTL, rinfo->state.surface_cntl);
|
|
|
|
BEGIN_ACCEL(2);
|
|
OUTREG(DEFAULT_SC_TOP_LEFT, 0);
|
|
OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX));
|
|
|
|
BEGIN_ACCEL(1);
|
|
OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR));
|
|
|
|
BEGIN_ACCEL(7);
|
|
OUTREG(DST_LINE_START, 0);
|
|
OUTREG(DST_LINE_END, 0);
|
|
OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
|
|
radeon_wait_for_idle_mmio(rinfo);
|
|
}
|
|
|
|
/* Initialize the acceleration hardware */
|
|
void radeon_engine_init(struct radeonfb_info *rinfo)
|
|
{
|
|
unsigned long temp;
|
|
|
|
OUTREG(RB3D_CNTL, 0);
|
|
radeon_engine_reset(rinfo);
|
|
temp = radeon_get_dstbpp(rinfo->depth);
|
|
#ifdef RADEON_TILING
|
|
rinfo->dp_gui_master_cntl = ((temp << GMC_DST_DATATYPE_SHIFT) | GMC_CLR_CMP_CNTL_DIS | GMC_DST_PITCH_OFFSET_CNTL);
|
|
#else
|
|
rinfo->dp_gui_master_cntl = ((temp << GMC_DST_DATATYPE_SHIFT) | GMC_CLR_CMP_CNTL_DIS);
|
|
#endif
|
|
radeon_engine_restore(rinfo);
|
|
}
|
|
|