551 lines
23 KiB
ArmAsm
551 lines
23 KiB
ArmAsm
/*
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* initialize exception vectors
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Created on: 26.02.2013
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* Author: Markus Fröschle
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*/
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#include "startcf.h"
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#if MACHINE_FIREBEE
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#include "firebee.h"
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#elif MACHINE_M5484LITE
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#include "m5484l.h"
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#endif /* MACHINE_FIREBEE */
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.extern __SUP_SP
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.extern _rom_entry
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.extern __RAMBAR0
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.extern _rt_mod
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.extern _rt_ssp
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.extern _rt_usp
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.extern _rt_vbr
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.extern _mmutr_miss
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.extern __MBAR
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.extern __MMUBAR
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.extern _video_tlb
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.extern _video_sbt
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.extern _flush_and_invalidate_caches
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.extern _get_bas_drivers
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/* PCI interrupt handlers */
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.extern _irq5_handler
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.extern _irq6_handler
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.extern _irq7_handler
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.global _vec_init
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.global _std_exc_vec /* needed by driver_vec.c */
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/* Register read/write equates */
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/* MMU */
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.equ MCF_MMU_MMUCR, __MMUBAR
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.equ MCF_MMU_MMUOR, __MMUBAR+0x04
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.equ MCF_MMU_MMUSR, __MMUBAR+0x08
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.equ MCF_MMU_MMUAR, __MMUBAR+0x10
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.equ MCF_MMU_MMUTR, __MMUBAR+0x14
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.equ MCF_MMU_MMUDR, __MMUBAR+0x18
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/* EPORT flag register */
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.equ MCF_EPORT_EPFR, __MBAR+0xf0c
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/* FEC1 port output data direction register */
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.equ MCF_GPIO_PODR_FEC1L, __MBAR+0xa07
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/* PSC0 transmit buffer register */
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.equ MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c
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/* GPT mode select register */
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.equ MCF_GPT0_GMS, __MBAR+0x800
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/* Slice timer 0 count register */
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.equ MCF_SLT0_SCNT, __MBAR+0x908
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// interrupt sources
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.equ INT_SOURCE_EPORT_EPF1,1 // edge port flag 1
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.equ INT_SOURCE_EPORT_EPF2,2 // edge port flag 2
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.equ INT_SOURCE_EPORT_EPF3,3 // edge port flag 3
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.equ INT_SOURCE_EPORT_EPF4,4 // edge port flag 4
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.equ INT_SOURCE_EPORT_EPF5,5 // edge port flag 5
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.equ INT_SOURCE_EPORT_EPF6,6 // edge port flag 6
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.equ INT_SOURCE_EPORT_EPF7,7 // edge port flag 7
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.equ INT_SOURCE_USB_EP0ISR,15 // USB endpoint 0 interrupt
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.equ INT_SOURCE_USB_EP1ISR,16 // USB endpoint 1 interrupt
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.equ INT_SOURCE_USB_EP2ISR,17 // USB endpoint 2 interrupt
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.equ INT_SOURCE_USB_EP3ISR,18 // USB endpoint 3 interrupt
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.equ INT_SOURCE_USB_EP4ISR,19 // USB endpoint 4 interrupt
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.equ INT_SOURCE_USB_EP5ISR,20 // USB endpoint 5 interrupt
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.equ INT_SOURCE_USB_EP6ISR,21 // USB endpoint 6 interrupt
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.equ INT_SOURCE_USB_USBISR,22 // USB general interrupt
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.equ INT_SOURCE_USB_USBAISR,23 // USB core interrupt
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.equ INT_SOURCE_USB_ANY,24 // OR of all USB interrupts
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.equ INT_SOURCE_USB_DSPI_OVF,25 // DSPI overflow or underflow
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.equ INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt
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.equ INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt
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.equ INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt
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.equ INT_SOURCE_USB_DSPI_TCF,29 // transfer complete interrupt
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.equ INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt
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.equ INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt
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.equ INT_SOURCE_PSC3,32 // PSC3 interrupt
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.equ INT_SOURCE_PSC2,33 // PSC2 interrupt
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.equ INT_SOURCE_PSC1,34 // PSC1 interrupt
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.equ INT_SOURCE_PSC0,35 // PSC0 interrupt
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.equ INT_SOURCE_CTIMERS,36 // combined source for comm timers
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.equ INT_SOURCE_SEC,37 // SEC interrupt
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.equ INT_SOURCE_FEC1,38 // FEC1 interrupt
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.equ INT_SOURCE_FEC0,39 // FEC0 interrupt
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.equ INT_SOURCE_I2C,40 // I2C interrupt
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.equ INT_SOURCE_PCIARB,41 // PCI arbiter interrupt
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.equ INT_SOURCE_CBPCI,42 // COMM bus PCI interrupt
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.equ INT_SOURCE_XLBPCI,43 // XLB PCI interrupt
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.equ INT_SOURCE_XLBARB,47 // XLBARB to PCI interrupt
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.equ INT_SOURCE_DMA,48 // multichannel DMA interrupt
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.equ INT_SOURCE_CAN0_ERROR,49 // FlexCAN error interrupt
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.equ INT_SOURCE_CAN0_BUSOFF,50 // FlexCAN bus off interrupt
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.equ INT_SOURCE_CAN0_MBOR,51 // message buffer ORed interrupt
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.equ INT_SOURCE_SLT1,53 // slice timer 1 interrupt
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.equ INT_SOURCE_SLT0,54 // slice timer 0 interrupt
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.equ INT_SOURCE_CAN1_ERROR,55 // FlexCAN error interrupt
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.equ INT_SOURCE_CAN1_BUSOFF,56 // FlexCAN bus off interrupt
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.equ INT_SOURCE_CAN1_MBOR,57 // message buffer ORed interrupt
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.equ INT_SOURCE_GPT3,59 // GPT3 timer interrupt
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.equ INT_SOURCE_GPT2,60 // GPT2 timer interrupt
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.equ INT_SOURCE_GPT1,61 // GPT1 timer interrupt
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.equ INT_SOURCE_GPT0,62 // GPT0 timer interrupt
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// Atari register equates (provided by FPGA)
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.equ vbasehi, 0xffff8201
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/*
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* macros
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*/
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.altmacro
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.macro irq vector,int_mask,clr_int
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move.w #0x2700,sr // disable interrupt
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subq.l #8,sp
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movem.l d0/a5,(sp) // save registers
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lea MCF_EPORT_EPFR,a5
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move.b #\clr_int,(a5) // clear int pending
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movem.l (sp),d0/a5 // restore registers
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addq.l #8,sp
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move.l \vector,-(sp)
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move #0x2\int_mask\()00,sr
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rts
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.endm
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.text
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_vec_init:
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move.l a2,-(sp) // Backup registers
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mov3q.l #-1,_rt_mod // rt_mod auf super
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clr.l _rt_ssp
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clr.l _rt_usp
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clr.l _rt_vbr
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move.l #__RAMBAR0,d0 // exception vectors reside in rambar0
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movec d0,VBR
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move.l d0,a0
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move.l a0,a2
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/*
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* first, set standard vector for all exceptions
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*/
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init_vec:
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move.l #256,d0
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lea std_exc_vec(pc),a1 // standard vector
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init_vec_loop:
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move.l a1,(a2)+ // set standard vector for all exceptions
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subq.l #1,d0
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bne init_vec_loop
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move.l #__SUP_SP,(a0) // set initial stack pointer at start of exception vector table
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lea reset_vector(pc),a1 // set reset vector
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move.l a1,0x04(a0)
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lea access(pc),a1 // set illegal access exception handler
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move.l a1,0x08(a0)
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// trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS
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lea _get_bas_drivers(pc),a1
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move.l a1,0x80(a0) // trap #0 exception vector
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#ifdef MACHINE_FIREBEE
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// timer vectors (triggers when vbashi gets changed, used for video page copy)
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lea handler_gpt0(pc),a1
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// GPT0 interrupt source = 62
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move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
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#endif /* MACHINE_FIREBEE */
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// install lowlevel_isr_handler for the three GPT timers
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lea _lowlevel_isr_handler(pc),a1
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move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
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// install lowlevel_isr_handler for the FEC0 interrupt
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move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
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// install lowlevel_isr_handler for the PSC3 interrupt
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move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
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// install lowlevel_isr_handler for the XLBPCI interrupt
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move.l a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
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#ifndef MACHINE_FIREBEE
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// FEC1 not wired on the FireBee (used for FPGA as GPIO), but used on other machines
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move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
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#endif
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// install lowlevel_isr_handler for Coldfire DMA interrupts
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move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
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move.l (sp)+,a2 // Restore registers
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rts
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/*
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* exception vector routines
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*/
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vector_table_start:
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std_exc_vec:
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_std_exc_vec:
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//move.w #0x2700,sr // disable interrupt
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subq.l #8,sp
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movem.l d0/a5,(sp) // save registers
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move.w 8(sp),d0 // fetch vector
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and.l #0x3fc,d0 // mask out vector number
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#ifdef DBG_EXC
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// printout vector number of exception
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lea -4 * 4(sp),sp // reserve stack space
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movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers
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lsr.l #2,d0 // shift vector number in place
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cmp.l #33,d0
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beq noprint
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cmp.l #34,d0
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beq n oprint
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cmp.l #45,d0
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beq noprint
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cmp.l #46,d0
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beq noprint
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move.l 4 * 4 + 8 + 4(sp),-(sp) // pc at exception
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move.l d0,-(sp) // provide it to xprintf()
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pea exception_text
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jsr _xprintf // call xprintf()
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add.l #3*4,sp // adjust stack
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noprint:
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movem.l (sp),d0-d1/a0-a1 // restore registers
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lea 4 * 4(sp),sp
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#endif /* DBG_EXC */
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add.l _rt_vbr,d0 // + VBR
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move.l d0,a5
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move.l (a5),d0 // fetch exception routine address
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move.l 4(sp),a5 // restore a5
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move.l d0,4(sp) // store exception routine address
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// FIXME: not clear why we would need the following?
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//move.w 10(sp),d0 // restore original SR
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//bset #13,d0 // set supervisor bit
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//move.w d0,sr //
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move.l (sp)+,d0 // restore d0
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rts // jump to exception handler
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exception_text:
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.ascii "DEBUG: EXCEPTION %d caught at %p"
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.byte 13, 10, 0
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.align 4
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reset_vector:
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move.w #0x2700,sr // disable interrupt
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move.l #0x31415926,d0
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cmp.l 0x426,d0 // _resvalid: reset vector valid?
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beq std_exc_vec // yes->
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jmp _rom_entry // no, cold start machine
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access:
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move.w #0x2700,sr // disable interrupts
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link a6,#-4 * 4 // make room for gcc scratch registers
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movem.l d0-d1/a0-a1,(sp) // save them
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move.l 4(a6),-(sp) // push format_status
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move.l 8(a6),-(sp) // pc at exception
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move.l MCF_MMU_MMUAR,-(sp) // MMU fault address
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move.l MCF_MMU_MMUSR,-(sp) // MMU status regisrter
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move.w #0x2300,sr // can lower interrupt mask now that MMU status is safe
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jsr _mmutr_miss // call C routine
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lea 4 * 4(sp),sp // adjust stack
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tst.l d0 // exception handler signals bus error
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bne bus_error
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movem.l (sp),d0-d1/a0-a1 // restore registers
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unlk a6
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rte
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bus_error:
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movem.l (sp),d0-d1/a0-a1 // restore registers
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unlk a6
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bra std_exc_vec
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zero_divide:
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move.w #0x2700,sr // disable interrupt
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move.l a0,-(sp)
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move.l d0,-(sp)
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move.l 12(sp),a0 // pc
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move.w (a0)+,d0 // command word
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btst #7,d0 // long?
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beq zd_word // nein->
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addq.l #2,a0
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zd_word:
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and.l 0x3f,d0 // mask out ea field
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cmp.w #0x08,d0 // -(ax) or less?
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ble zd_end
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addq.l #2,a0
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cmp.w #0x39,d0 // xxx.L
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bne zd_nal
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addq.l #2,a0
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bra zd_end
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zd_nal: cmp.w #0x3c,d0 // immediate?
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bne zd_end // no->
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btst #7,d0 // long?
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beq zd_end // no
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addq.l #2,a0
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zd_end:
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move.l a0,12(sp)
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move.l (sp)+,d0
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move.l (sp)+,a0
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rte
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#ifdef _NOT_USED_
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linea:
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move.w #0x2700,sr // disable interrupt
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halt
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nop
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nop
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linef:
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move.w #0x2700,sr // disable interrupt
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halt
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nop
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nop
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format:
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move.w #0x2700,sr // disable interrupt
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halt
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nop
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nop
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//floating point
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flpoow:
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move.w #0x2700,sr // disable interrupt
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halt
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nop
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nop
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#endif /* _NOT_USED */
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#if MACHINE_M5484LITE // handlers for M5484LITE
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irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
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move.w #0x2700,sr // disable interrupts
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lea -4*4(sp),sp // save gcc scratch registers
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movem.l d0-d1/a0-a1,(sp)
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jsr _irq5_handler // call C handler routine
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movem.l (sp),d0-d1/a0-a1 // restore registers
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lea 4*4(sp),sp
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rte // return from exception
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irq5text:
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.ascii "IRQ5!"
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.dc.b 13,10,0
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irq6:
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irq 0x74,5,0x20
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irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
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move.w #0x2700,sr // disable interrupts
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lea -4*4(sp),sp // save gcc scratch registers
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movem.l d0-d1/a0-a1,(sp)
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jsr _irq7_handler // call C handler routine
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movem.l (sp),d0-d1/a0-a1 // restore registers
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lea 4*4(sp),sp
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rte // return from exception
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irq7text:
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.data
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.ascii "IRQ7!"
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.dc.b 13,10,0
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.text
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#elif MACHINE_FIREBEE /* these handlers are only meaningful for the Firebee */
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irq5: move.w #0x2700,sr // disable interrupts
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subq.l #4,sp // extra space
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link a6,#-4 * 4 // save gcc scratch registers
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movem.l d0-d1/a0-a1,(sp)
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jsr _irq5_handler // call C handler routine
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tst.l d0 // handled?
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bne irq5_forward
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movem.l (sp),d0-d1/a0-a1 // restore registers
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unlk a6
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addq.l #4,sp
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rte // return from exception
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irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector
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add.l _rt_vbr,a0 // add runtime vbr
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move.l a0,4(a6) // put on stack
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movem.l (sp),d0-d1/a0-a1 // restore registers
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unlk a6 //
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move.w #0x2500,sr // set interrupt level
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rts // jump through vector
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irq6: move.w #0x2700,sr // disable interrupt
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subq.l #4,sp // extra space
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link a6,#-4 * 4 // save gcc scratch registers
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movem.l d0-d1/a0-a1,(sp)
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move.l 4(a6),-(sp) // format status word
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move.l 8(a6),-(sp) // pc at exception
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jsr _irq6_handler // call C handler
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lea 8(sp),sp // fix stack
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tst.l d0 // interrupt handled?
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bne irq6_forward // no, forward to TOS
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movem.l (sp),d0-d1/a0-a1 // restore registers
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unlk a6
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addq.l #4,sp // "extra space" not needed in this case
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rte
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irq6_forward:
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move.l 0xf0020000,a0 // fetch "MFP interrupt vector from FPGA"
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add.l _rt_vbr,a0 // add runtime VBR
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move.l (a0),8(a6) // fetch handler address and put it on "extra space"
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movem.l (sp),d0-d1/a0-a1
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unlk a6
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move.w #0x2600,sr // set interrupt level
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rts // jump through vector
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/*
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* irq 7 = pseudo bus error
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*/
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irq7:
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lea -12(sp),sp
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movem.l d0/a0,(sp)
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move.l __RAMBAR0+0x008,a0 // real access error handler
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move.l a0,8(sp) // this will be the return address for rts
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move.w 12(sp),d0 // format/vector word
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andi.l #0xf000,d0 // keep only the format
|
|
ori.l #2*4,d0 // simulate vector #2, no fault
|
|
move.w d0,12(sp)
|
|
|
|
// TODO: Inside an interrupt handler, 16(sp) is the return address.
|
|
// For an Access Error, it should be the address of the fault instruction instead
|
|
|
|
lea MCF_EPORT_EPFR,a0
|
|
bset #7,(a0) // clear int 7
|
|
|
|
move.l (sp)+,d0 // restore registers
|
|
move.l (sp)+,a0
|
|
rts // Forward to the Access Error handler
|
|
|
|
|
|
/*
|
|
* general purpose timer 0 (GPT0): video change, later also others.
|
|
*
|
|
* GPT0 is used as input trigger. It is connected to the TIN0 signal of
|
|
* the FPGA and triggers everytime vbasehi is written to, i.e.
|
|
* when the video base address gets changed
|
|
*/
|
|
|
|
/*
|
|
* TODO: remove. This interrupt still fires, but doesn't do anything anymore.
|
|
* BaS_gcc handles FPGA RAM as STRAM, so there is no page copy necessary as
|
|
* it was with previous versions.
|
|
*/
|
|
handler_gpt0:
|
|
.extern _gpt0_interrupt_handler
|
|
|
|
move.w #0x2700,sr // disable interrupts
|
|
link a6,#-4 * 4 // make room for
|
|
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
|
|
// other registers will be handled by gcc itself
|
|
|
|
move.w 4(a6),d0 // fetch vector number from stack
|
|
move.l d0,-(sp) // push it
|
|
jsr _gpt0_interrupt_handler // call C handler
|
|
addq.l #4,sp // adjust stack
|
|
|
|
movem.l (sp),d0-d1/a0-a1 // restore registers
|
|
|
|
unlk a6
|
|
rte
|
|
#endif /* MACHINE_FIREBEE */
|
|
|
|
/*
|
|
* low-level interrupt service routine for routines registered with
|
|
* isr_register_handler()
|
|
*/
|
|
.global _lowlevel_isr_handler
|
|
.extern _isr_execute_handler
|
|
|
|
|
|
_lowlevel_isr_handler:
|
|
move.w #0x2700,sr // do not disturb
|
|
link a6,#-4 * 4 // make room for
|
|
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
|
|
// other registers will be handled by gcc itself
|
|
|
|
move.w 4(a6),d0 // fetch vector number from stack
|
|
lsr.l #2,d0 // move it in place
|
|
andi.l #0xff,d0 // mask it out
|
|
move.l d0,-(sp) // push it
|
|
jsr _isr_execute_handler // call the C handler
|
|
addq.l #4,sp // adjust stack
|
|
|
|
movem.l (sp),d0-d1/a0-a1 // restore registers
|
|
unlk a6
|
|
rte
|