1a718db4aa
-moved all includes into "include" directory -extracted "wait...()"-routines into separate files
662 lines
12 KiB
C
662 lines
12 KiB
C
/*****************************************************************************************/
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// opertionen
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/*****************************************************************************************/
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ii_lset_op:.macro
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//byt
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ii_lset_opea \1,0 // dx,ax
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ii_lset_opea \1,1 // (ax), (ax)+
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ii_lset_opea \1,2 // -(ax),d16(ax)
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ii_lset_opeag \1,3 // d8(ax,dy)
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lea table+0x\1\238*4,a0
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move.l #ii_0x\138,(a0)+ // xxx.w
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move.l #ii_0x\139,(a0)+ // xxx.l
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//word
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ii_lset_opea \1,4 // dx,ax
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ii_lset_opea \1,5 // (ax), (ax)+
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ii_lset_opea \1,6 // -(ax),d16(ax)
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ii_lset_opeag \1,7 // d8(ax,dy)
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lea table+0x\178*4,a0
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move.l #ii_0x\178,(a0)+ // xxx.w
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move.l #ii_0x\179,(a0)+ // xxx.l
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//long
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ii_lset_opea \1,8 // dx,ax
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ii_lset_opea \1,9 // (ax), (ax)+
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ii_lset_opea \1,a // -(ax),d16(ax)
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ii_lset_opeag \1,b // d8(ax,dy)
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lea table+0x\1b8*4,a0
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move.l #ii_0x\1b8,(a0)+ // xxx.w
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move.l #ii_0x\1b9,(a0)+ // xxx.l
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.endm
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ii_lset_opeag:.macro // 0x1120-0x1127
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lea table+0x\1\20*4,a0
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move.l #ii_0x\1\20,(a0)+
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move.l #ii_0x\1\21,(a0)+
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move.l #ii_0x\1\22,(a0)+
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move.l #ii_0x\1\23,(a0)+
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move.l #ii_0x\1\24,(a0)+
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move.l #ii_0x\1\25,(a0)+
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move.l #ii_0x\1\26,(a0)+
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move.l #ii_0x\1\27,(a0)+
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.endm;
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ii_lset_opeau:.macro // 0x1128-0x112f
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lea table+0x\1\28*4,a0
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move.l #ii_0x\1\28,(a0)+
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move.l #ii_0x\1\29,(a0)+
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move.l #ii_0x\1\2a,(a0)+
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move.l #ii_0x\1\2b,(a0)+
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move.l #ii_0x\1\2c,(a0)+
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move.l #ii_0x\1\2d,(a0)+
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move.l #ii_0x\1\2e,(a0)+
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move.l #ii_0x\1\2f,(a0)+
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.endm;
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ii_lset_opea:.macro
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ii_lset_opeag \1,\2
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ii_lset_opeau \1,\2
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.endm
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/******************************************************/
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ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick
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// byt
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opdx \1,\2,b,0,\3 // dx,ax
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opia \1,\2,b,1,\3 // (ax),(ax)+
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opdia \1,\2,b,2,\3 // -(ax),d16(ax)
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opd8a \1,\2,b,3,\3 // d8(ax),xxx
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// word
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opdx \1,\2,w,4,\3 // dx,ax
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opia \1,\2,w,5,\3 // (ax),(ax)+
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opdia \1,\2,w,6,\3 // -(ax),d16(ax)
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opd8a \1,\2,w,7,\3 // d8(ax),xxx
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// long
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opdx \1,\2,l,8,\3 // dx,ax
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opia \1,\2,l,9,\3 // (ax),(ax)+
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opdia \1,\2,l,a,\3 // -(ax),d16(ax)
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opd8a \1,\2,l,b,\3 // d8(ax),xxx
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.endm
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/******************************************************/
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// byt word long
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/******************************************************/
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opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
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ii_0x\1\40:
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.ifc \3,b
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op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
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.else
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.ifc \3,w
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op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
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.else
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op\5smd \2,d0_off(a7),d0_off(a7),\3
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.endif
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.endif
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ii_0x\1\41:
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.ifc \3,b
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op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
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.else
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.ifc \3,w
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op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
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.else
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op\5smd \2,d1_off(a7),d1_off(a7),\3
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.endif
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.endif
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ii_0x\1\42:
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op\5smd \2,d2,d2,\3
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ii_0x\1\43:
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op\5smd \2,d3,d3,\3
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ii_0x\1\44:
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op\5smd \2,d4,d4,\3
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ii_0x\1\45:
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op\5smd \2,d5,d5,\3
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ii_0x\1\46:
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op\5smd \2,d6,d6,\3
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ii_0x\1\47:
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op\5smd \2,d7,d7,\3
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//ax
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ii_0x\1\48:
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opa\5smd \2,a0_off(a7),a0_off(a7),\3
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ii_0x\1\49:
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opa\5smd \2,a1_off(a7),a1_off(a7),\3
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ii_0x\1\4a:
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opa\5smd \2,a2,a2,\3
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ii_0x\1\4b:
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opa\5smd \2,a3,a3,\3
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ii_0x\1\4c:
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opa\5smd \2,a4,a4,\3
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ii_0x\1\4d:
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opa\5smd \2,a5,a5,\3
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ii_0x\1\4e:
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opa\5smd \2,a6,a6,\3
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ii_0x\1\4f:
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opa\5smd \2,usp,usp,\3
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.endm;
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//-----------------------------------------------
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opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
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//(ax)
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ii_0x\1\40:
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op\5sia \2,a0_off(a7),(a1),(a1),\3
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ii_0x\1\41:
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op\5sia \2,a1_off(a7),(a1),(a1),\3
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ii_0x\1\42:
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op\5smd \2,(a2),(a2),\3
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ii_0x\1\43:
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op\5smd \2,(a3),(a3),\3
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ii_0x\1\44:
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op\5smd \2,(a4),(a4),\3
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ii_0x\1\45:
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op\5smd \2,(a5),(a5),\3
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ii_0x\1\46:
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op\5smd \2,(a6),(a6),\3
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ii_0x\1\47:
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op\5sia \2,usp,(a1),(a1),\3
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//(ax)+
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ii_0x\1\48:
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op\5sia \2,a0_off(a7),(a1),(a1)+,\3
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ii_0x\1\49:
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op\5sia \2,a1_off(a7),(a1),(a1)+,\3
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ii_0x\1\4a:
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op\5smd \2,(a2),(a2)+,\3
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ii_0x\1\4b:
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op\5smd \2,(a3),(a3)+,\3
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ii_0x\1\4c:
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op\5smd \2,(a4),(a4)+,\3
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ii_0x\1\4d:
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op\5smd \2,(a5),(a5)+,\3
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ii_0x\1\4e:
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op\5smd \2,(a6),(a6)+,\3
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ii_0x\1\4f:
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op\5sia \2,usp,(a1),(a1)+,\3
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.endm;
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//-----------------------------------------------
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opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
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ii_0x\1\40:
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op\5sia \2,a0_off(a7),-(a1),(a1),\3
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ii_0x\1\41:
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op\5sia \2,a1_off(a7),-(a1),(a1),\3
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ii_0x\1\42:
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op\5smd \2,-(a2),(a2),\3
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ii_0x\1\43:
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op\5smd \2,-(a3),(a3),\3
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ii_0x\1\44:
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op\5smd \2,-(a4),(a4),\3
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ii_0x\1\45:
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op\5smd \2,-(a5),(a5),\3
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ii_0x\1\46:
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op\5smd \2,-(a6),(a6),\3
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ii_0x\1\47:
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op\5sia \2,usp,-(a1),(a1),\3
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ii_0x\1\48:
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op\5sd16a \2,a0_off(a7),\3
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ii_0x\1\49:
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op\5sd16a \2,a1_off(a7),\3
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ii_0x\1\4a:
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op\5sd16a \2,a2,\3
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ii_0x\1\4b:
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op\5sd16a \2,a3,\3
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ii_0x\1\4c:
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op\5sd16a \2,a4,\3
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ii_0x\1\4d:
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op\5sd16a \2,a5,\3
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ii_0x\1\4e:
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op\5sd16a \2,a6,\3
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ii_0x\1\4f:
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op\5sd16a \2,usp,\3
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.endm;
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//-----------------------------------------------
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opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
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ii_0x\1\40:
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op\5sd8a \2,a0_off(a7),\3
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ii_0x\1\41:
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op\5sd8a \2,a1_off(a7),\3
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ii_0x\1\42:
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op\5sd8a \2,a2,\3
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ii_0x\1\43:
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op\5sd8a \2,a3,\3
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ii_0x\1\44:
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op\5sd8a \2,a4,\3
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ii_0x\1\45:
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op\5sd8a \2,a5,\3
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ii_0x\1\46:
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op\5sd8a \2,a6,\3
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ii_0x\1\47:
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op\5sd8a \2,usp,\3
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ii_0x\1\48:
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op\5sxx \2,\3,w
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ii_0x\1\49:
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op\5sxx \2,\3,l
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.endm;
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//-----------------------------------------------
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opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size
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#ifdef halten_op
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halt
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#endif
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.ifc \4,l
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move.l \2,d1
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.else
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mvs.\4 \2,d1
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.endif
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.ifc \1,negx
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move.b sr_off+1(a7),d1 //ccr holen
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move d1,ccr //setzen
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.endif
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\1 d1
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set_cc0
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move.\4 d1,\3
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ii_end
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.endm;
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opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size
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#ifdef halten_op
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halt
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#endif
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.ifc \2,usp
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move.l usp,a1
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move.l a1,d1
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.else
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move.l \2,d1
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.endif
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\1 d1
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.ifc \3,usp
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move.l d1,a1
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move.l a1,usp
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.else
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move.l d1,\3
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.endif
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ii_end
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.endm;
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opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size
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#ifdef halten_op
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halt
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#endif
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move.l \2,a1
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.ifc \5,l
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move.l \3,d1
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.else
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mvs.\5 \3,d1
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.endif
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.ifc \1,negx
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move.b sr_off+1(a7),d1 //ccr holen
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move d1,ccr //setzen
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.endif
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\1 d1
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set_cc0
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move.\5 d1,\4
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ii_end
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.endm;
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opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size
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#ifdef halten_op
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halt
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#endif
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move.l \2,a1
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mvs.w (a0)+,d1
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add.l d1,a1
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.ifc \3,l
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move.l (a1),d1
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.else
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mvs.\3 (a1),d1
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.endif
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.ifc \1,negx
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move.b sr_off+1(a7),d1 //ccr holen
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move d1,ccr //setzen
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.endif
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\1 d1
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set_cc0
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move.\3 d1,(a1)
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ii_end
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.endm;
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opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size
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#ifdef halten_op
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halt
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#endif
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move.l \2,a1
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jsr ewf
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.ifc \3,l
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move.l (a1),d1
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.else
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mvs.\3 (a1),d1
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.endif
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.ifc \1,negx
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move.b sr_off+1(a7),d1 //ccr holen
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move d1,ccr //setzen
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.endif
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\1 d1
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set_cc0
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move.\3 d1,(a1)
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ii_end
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.endm;
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opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse
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#ifdef halten_op
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halt
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#endif
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.ifc \2,l
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move.l (a1),d1
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.else
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mvs.\2 (a1),d1
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.endif
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move.\3 (a0)+,a1
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.ifc \1,negx
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move.b sr_off+1(a7),d1 //ccr holen
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move d1,ccr //setzen
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.endif
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\1 d1
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set_cc0
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move.\2 d1,(a1)
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ii_end
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.endm;
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//*******************************************************************************3
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opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size
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#ifdef halten_op
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halt
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#endif
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.ifc \4,l
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move.l (a0)+,d0
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.else
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.ifc \4,w
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mvs.w (a0)+,d0
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.else
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move.w (a0)+,d0
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extb.l d0
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.endif
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.endif
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.ifc \4,l
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move.l \2,d1
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.else
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mvs.\4 \2,d1
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.endif
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\1 d0,d1
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set_cc0
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.ifnc \1,cmp.l
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move.\4 d1,\3
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.endif
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ii_end
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.endm;
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opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size
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#ifdef halten_op
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halt
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#endif
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.ifc \4,l
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move.l (a0)+,d0
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.else
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.ifc \4,w
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mvs.w (a0)+,d0
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.else
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move.w (a0)+,d0
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extb.l d0
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.endif
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.endif
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.ifc \2,usp
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move.l usp,a1
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move.l a1,d1
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.else
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move.l \2,d1
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.endif
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\1 d0,d1
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.ifnc \1,cmp.l
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.ifc \3,usp
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move.l d1,a1
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move.l a1,usp
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.else
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move.l d1,\3
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.endif
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.endif
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ii_end
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.endm;
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opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
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#ifdef halten_op
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halt
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#endif
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.ifc \5,l
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move.l (a0)+,d0
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.else
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.ifc \5,w
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mvs.w (a0)+,d0
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.else
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move.w (a0)+,d0
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extb.l d0
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.endif
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.endif
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move.l \2,a1
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.ifc \5,l
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move.l \3,d1
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.else
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mvs.\5 \3,d1
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.endif
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\1 d0,d1
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set_cc0
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.ifnc \1,cmp.l
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move.\5 d1,\4
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.endif
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ii_end
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.endm;
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opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size
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#ifdef halten_op
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halt
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#endif
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.ifc \3,l
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move.l (a0)+,d0
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.else
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.ifc \3,w
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mvs.w (a0)+,d0
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.else
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move.w (a0)+,d0
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extb.l d0
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.endif
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.endif
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move.l \2,a1
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mvs.w (a0)+,d1
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add.l d1,a1
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.ifc \3,l
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move.l (a1),d1
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.else
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mvs.\3 (a1),d1
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.endif
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\1 d0,d1
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set_cc0
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.ifnc \1,cmp.l
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move.\3 d1,(a1)
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.endif
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ii_end
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.endm;
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opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size
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#ifdef halten_op
|
|
halt
|
|
#endif
|
|
|
|
.ifc \3,l
|
|
move.l (a0)+,d0
|
|
.else
|
|
.ifc \3,w
|
|
mvs.w (a0)+,d0
|
|
.else
|
|
move.w (a0)+,d0
|
|
extb.l d0
|
|
.endif
|
|
.endif
|
|
move.l d0,_d0_save
|
|
move.l \2,a1
|
|
jsr ewf
|
|
move.l _d0_save,d0
|
|
.ifc \3,l
|
|
move.l (a1),d1
|
|
.else
|
|
mvs.\3 (a1),d1
|
|
.endif
|
|
\1 d0,d1
|
|
set_cc0
|
|
.ifnc \1,cmp.l
|
|
move.\3 d1,(a1)
|
|
.endif
|
|
ii_end
|
|
.endm;
|
|
|
|
opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse
|
|
.ifc \2,l
|
|
move.l (a0)+,d0
|
|
.else
|
|
.ifc \2,w
|
|
mvs.w (a0)+,d0
|
|
.else
|
|
move.w (a0)+,d0
|
|
extb.l d0
|
|
.endif
|
|
.endif
|
|
move.\3 (a0)+,a1
|
|
.ifc \2,l
|
|
move.l (a1),d1
|
|
.else
|
|
mvs.\2 (a1),d1
|
|
.endif
|
|
\1 d0,d1
|
|
set_cc0
|
|
.ifnc \1,cmp.l
|
|
move.\2 d1,(a1)
|
|
.endif
|
|
ii_end
|
|
.endm;
|
|
//*******************************************************************************3
|
|
opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
|
|
.ifc \4,l
|
|
move.l \2,d1
|
|
.else
|
|
mvs.\4 \2,d1
|
|
.endif
|
|
.ifc \1,eor.l d0
|
|
move.l d0_off(a7),d0
|
|
.endif
|
|
.ifc \1,eor.l d1
|
|
move.l d1_off(a7),d1
|
|
.endif
|
|
\1 ,d1
|
|
set_cc0
|
|
move.\4 d1,\3
|
|
ii_end
|
|
.endm;
|
|
|
|
opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
|
|
.ifc \2,usp
|
|
move.l usp,a1
|
|
move.l a1,d1
|
|
.else
|
|
move.l \2,d1
|
|
.endif
|
|
\1 ,d1
|
|
.ifc \3,usp
|
|
move.l d1,a1
|
|
move.l a1,usp
|
|
.else
|
|
move.l d1,\3
|
|
.endif
|
|
ii_end
|
|
.endm;
|
|
|
|
opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
|
|
#ifdef halten_op
|
|
halt
|
|
#endif
|
|
|
|
move.l \2,a1
|
|
.ifc \5,l
|
|
move.l \3,d1
|
|
.else
|
|
mvs.\5 \3,d1
|
|
.endif
|
|
.ifc \1,eor.l d0
|
|
move.l d0_off(a7),d0
|
|
.endif
|
|
.ifc \1,eor.l d1
|
|
move.l d1_off(a7),d1
|
|
.endif
|
|
\1 ,d1
|
|
set_cc0
|
|
move.\5 d1,\4
|
|
ii_end
|
|
.endm;
|
|
|
|
opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size
|
|
#ifdef halten_op
|
|
halt
|
|
#endif
|
|
|
|
move.l \2,a1
|
|
mvs.w (a0)+,d1
|
|
add.l d1,a1
|
|
.ifc \3,l
|
|
move.l (a1),d1
|
|
.else
|
|
mvs.\3 (a1),d1
|
|
.endif
|
|
.ifc \1,eor.l d0
|
|
move.l d0_off(a7),d0
|
|
.endif
|
|
.ifc \1,eor.l d1
|
|
move.l d1_off(a7),d1
|
|
.endif
|
|
\1 ,d1
|
|
set_cc0
|
|
move.\3 d1,(a1)
|
|
ii_end
|
|
.endm;
|
|
|
|
opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
|
|
#ifdef halten_op
|
|
halt
|
|
#endif
|
|
|
|
move.l d0,_d0_save
|
|
move.l \2,a1
|
|
jsr ewf
|
|
move.l _d0_save,d0
|
|
.ifc \3,l
|
|
move.l (a1),d1
|
|
.else
|
|
mvs.\3 (a1),d1
|
|
.endif
|
|
.ifc \1,eor.l d0
|
|
move.l d0_off(a7),d0
|
|
.endif
|
|
.ifc \1,eor.l d1
|
|
move.l d1_off(a7),d1
|
|
.endif
|
|
\1 ,d1
|
|
set_cc0
|
|
move.\3 d1,(a1)
|
|
ii_end
|
|
.endm;
|
|
|
|
opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse
|
|
#ifdef halten_op
|
|
halt
|
|
#endif
|
|
|
|
move.\3 (a0)+,a1
|
|
.ifc \2,l
|
|
move.l (a1),d1
|
|
.else
|
|
mvs.\2 (a1),d1
|
|
.endif
|
|
.ifc \1,eor.l d0
|
|
move.l d0_off(a7),d0
|
|
.endif
|
|
.ifc \1,eor.l d1
|
|
move.l d1_off(a7),d1
|
|
.endif
|
|
\1 ,d1
|
|
set_cc0
|
|
move.\2 d1,(a1)
|
|
ii_end
|
|
.endm;
|