984 lines
31 KiB
C
984 lines
31 KiB
C
#include "mmu.h"
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#include "acia.h"
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#include "exceptions.h"
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#if defined(MACHINE_FIREBEE)
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#include "firebee.h"
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#elif defined(MACHINE_M5484LITE)
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#include "m5484l.h"
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#elif defined(MACHINE_M54455)
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#include "m54455.h"
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#else
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#error "unknown machine!"
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#endif
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/*
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* mmu.c
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* derived from original assembler sources:
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2013 M. Froeschle
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*/
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#define ACR_BA(x) ((x) & 0xffff0000)
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#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
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#define ACR_E(x) (((x) & 1) << 15)
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#define ACR_S(x) (((x) & 3) << 13)
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#define ACR_S_USERMODE 0
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#define ACR_S_SUPERVISOR_MODE 1
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#define ACR_S_ALL 2
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#define ACR_AMM(x) (((x) & 1) << 10)
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#define ACR_CM(x) (((x) & 3) << 5)
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#define ACR_CM_CACHEABLE_WT 0x0
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#define ACR_CM_CACHEABLE_CB 0x1
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#define ACR_CM_CACHE_INH_PRECISE 0x2
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#define ACR_CM_CACHE_INH_IMPRECISE 0x3
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#define ACR_SP(x) (((x) & 1) << 3)
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#define ACR_W(x) (((x) & 1) << 2)
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#include <stdint.h>
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#include "bas_printf.h"
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#include "bas_types.h"
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#include "MCF5475.h"
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#include "pci.h"
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#include "cache.h"
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#include "util.h"
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#if defined(MACHINE_FIREBEE)
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#include "firebee.h"
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#elif defined(MACHINE_M5484LITE)
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#include "m5484l.h"
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#elif defined(MACHINE_M54455)
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#include "m54455.h"
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#else
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#error "unknown machine!"x
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#endif /* MACHINE_FIREBEE */
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//#define DBG_MMU
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#ifdef DBG_MMU
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#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
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#else
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#define dbg(format, arg...) do {;} while (0)
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#endif /* DBG_MMU */
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#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0);
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/*
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* set ASID register
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* saves new value to rt_asid and returns former value
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*/
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inline uint32_t set_asid(uint32_t value)
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{
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extern long rt_asid;
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uint32_t ret = rt_asid;
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__asm__ __volatile__(
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"movec %[value],ASID\n\t"
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: /* no output */
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: [value] "r" (value)
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:
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);
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rt_asid = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr0(uint32_t value)
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{
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extern uint32_t rt_acr0;
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uint32_t ret = rt_acr0;
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__asm__ __volatile__(
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"movec %[value],ACR0\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr0 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr1(uint32_t value)
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{
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extern uint32_t rt_acr1;
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uint32_t ret = rt_acr1;
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__asm__ __volatile__(
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"movec %[value],ACR1\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr1 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr2(uint32_t value)
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{
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extern uint32_t rt_acr2;
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uint32_t ret = rt_acr2;
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__asm__ __volatile__(
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"movec %[value],ACR2\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr2 = value;
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return ret;
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}
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/*
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* set ACRx register
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* saves new value to rt_acrx and returns former value
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*/
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inline uint32_t set_acr3(uint32_t value)
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{
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extern uint32_t rt_acr3;
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uint32_t ret = rt_acr3;
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__asm__ __volatile__(
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"movec %[value],ACR3\n\t"
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: /* not output */
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: [value] "r" (value)
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:
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);
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rt_acr3 = value;
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return ret;
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}
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inline uint32_t set_mmubar(uint32_t value)
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{
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extern uint32_t rt_mmubar;
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uint32_t ret = rt_mmubar;
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__asm__ __volatile__(
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"movec %[value],MMUBAR\n\t"
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: /* no output */
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: [value] "r" (value)
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: /* no clobber */
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);
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rt_mmubar = value;
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NOP();
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return ret;
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}
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/*
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* translation table for virtual address ranges. Holds the physical_offset (which must be added to a virtual
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* address to get its physical counterpart) for memory ranges.
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*/
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struct virt_to_phys
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{
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uint32_t start_address;
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uint32_t length;
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uint32_t physical_offset;
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};
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#if defined(MACHINE_FIREBEE)
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static struct virt_to_phys translation[] =
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{
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/* virtual , length , offset */
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{ 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */
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{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
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{ 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */
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{ 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */
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};
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#elif defined(MACHINE_M5484LITE)
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static struct virt_to_phys translation[] =
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{
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/* virtual , length , offset */
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{ 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */
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{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
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{ 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */
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{ 0x60000000, 0x10000000, 0x00000000 }, /* map CPLD CF card I/O area */
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};
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#elif defined(MACHINE_M54455)
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/* FIXME: this is not determined yet! */
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static struct virt_to_phys translation[] =
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{
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/* virtual , length , offset */
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{ 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */
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{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
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{ 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */
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{ 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */
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};
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#else
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#error unknown machine!
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#endif
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static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);
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static inline int32_t lookup_phys(int32_t virt)
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{
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int i;
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for (i = 0; i < num_translations; i++)
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{
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if (virt >= translation[i].start_address && virt < translation[i].start_address + translation[i].length)
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{
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return virt + translation[i].physical_offset;
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}
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}
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err("virtual address 0x%lx not found in translation table!\r\n", virt);
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return -1;
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}
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struct mmu_page_descriptor
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{
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uint8_t cache_mode : 2;
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uint8_t supervisor_protect : 1;
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uint8_t read : 1;
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uint8_t write : 1;
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uint8_t execute : 1;
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uint8_t global : 1;
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uint8_t locked : 1;
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};
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/*
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* page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512
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* bytes size) or 8k pages (64k descriptor array size)
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*/
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static struct mmu_page_descriptor pages[SDRAM_SIZE / DEFAULT_PAGE_SIZE];
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int mmu_map_instruction_page(int32_t virt, uint8_t asid)
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{
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const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
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int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
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struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
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int ipl;
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int32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
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if (phys == -1)
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{
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/* no valid mapping found, caller will issue a bus error in return */
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return 0;
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}
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#ifdef DBG_MMU
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register int sp asm("sp");
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dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
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#endif /* DBG_MMU */
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/*
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* add page to TLB
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*/
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ipl = set_ipl(7); /* do not disturb */
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MCF_MMU_MMUAR = (virt & size_mask);
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MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
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MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
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(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
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MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
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MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
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(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
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(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
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(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
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(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
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(page->locked ? MCF_MMU_MMUDR_LK : 0);
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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set_ipl(ipl);
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dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
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dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
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return 1;
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}
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int mmu_map_data_page(int32_t virt, uint8_t asid)
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{
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uint16_t ipl;
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const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
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int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
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struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
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int32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
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if (phys == -1)
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{
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/* no valid mapping found, caller will issue a bus error in return */
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return 0;
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}
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#ifdef DBG_MMU
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register int sp asm("sp");
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dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
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#endif /* DBG_MMU */
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/*
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* add page to TLB
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*/
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ipl = set_ipl(7); /* do not disturb */
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MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
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MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
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(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
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MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
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MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
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(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
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(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
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(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
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(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
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(page->locked ? MCF_MMU_MMUDR_LK : 0);
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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set_ipl(ipl);
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dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
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dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
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return 1;
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}
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/*
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* map a page of memory using virt and phys as addresses with the Coldfire MMU.
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*
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* Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
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* instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
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* for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
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* TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
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* per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
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* LRU algorithm) should be used sparsingly.
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*/
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int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
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{
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int size_mask;
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int ipl;
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switch (sz)
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{
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case MMU_PAGE_SIZE_1M:
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size_mask = ~ (SIZE_1M - 1);
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break;
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case MMU_PAGE_SIZE_8K:
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size_mask = ~ (SIZE_8K - 1);
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break;
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case MMU_PAGE_SIZE_4K:
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size_mask = ~ (SIZE_4K - 1);
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break;
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case MMU_PAGE_SIZE_1K:
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size_mask = ~ (SIZE_1K - 1);
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break;
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default:
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dbg("illegal map size %d\r\n", sz);
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return 0;
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}
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/*
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* add page to TLB
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*/
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ipl = set_ipl(7); /* do not disturb */
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MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */
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MCF_MMU_MMUTR_ID(page_id) | /* address space id (ASID) */
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(flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
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MCF_MMU_MMUTR_V; /* valid */
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MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */
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MCF_MMU_MMUDR_SZ(sz) | /* page size */
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MCF_MMU_MMUDR_CM(flags->cache_mode) |
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(flags->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
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(flags->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
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(flags->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
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(flags->locked ? MCF_MMU_MMUDR_LK : 0);
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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NOP();
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
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MCF_MMU_MMUOR_ACC | /* access TLB */
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MCF_MMU_MMUOR_UAA; /* update allocation address field */
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set_ipl(ipl);
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dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
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return 1;
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}
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void mmu_init(void)
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{
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extern uint8_t _MMUBAR[];
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uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
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struct mmu_page_descriptor flags;
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int i;
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/*
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* clear all MMU TLB entries first
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*/
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MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA; /* clears _all_ TLBs (including locked ones) */
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NOP();
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/*
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* prelaminary initialization of page descriptor 0 (root) table
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*/
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for (i = 0; i < sizeof(pages) / sizeof(struct mmu_page_descriptor); i++)
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{
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uint32_t addr = i * DEFAULT_PAGE_SIZE;
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#if defined(MACHINE_FIREBEE)
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if (addr >= 0x00f00000UL && addr < 0x00ffffffUL) /* Falcon I/O area on the Firebee */
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{
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pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
|
|
pages[i].execute = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 0;
|
|
pages[i].global = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
}
|
|
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
|
|
{
|
|
pages[i].cache_mode = CACHE_WRITETHROUGH;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 0;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK;
|
|
pages[i].execute = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].global = 1;
|
|
}
|
|
pages[i].locked = 0; /* not locked */
|
|
pages[0].supervisor_protect = 0; /* protect system vectors */
|
|
|
|
#elif defined(MACHINE_M5484LITE)
|
|
if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */
|
|
{
|
|
pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
|
|
pages[i].execute = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 0;
|
|
pages[i].global = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
}
|
|
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
|
|
{
|
|
pages[i].cache_mode = CACHE_WRITETHROUGH;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 0;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */
|
|
pages[i].execute = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].global = 1;
|
|
}
|
|
pages[i].locked = 0; /* not locked */
|
|
pages[0].supervisor_protect = 0; /* protect system vectors */
|
|
|
|
#elif defined(MACHINE_M54455)
|
|
if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */
|
|
{
|
|
pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
|
|
pages[i].execute = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 0;
|
|
pages[i].global = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
}
|
|
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
|
|
{
|
|
pages[i].cache_mode = CACHE_WRITETHROUGH;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK;
|
|
pages[i].execute = 1;
|
|
pages[i].supervisor_protect = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 0;
|
|
pages[i].execute = 1;
|
|
pages[i].global = 1;
|
|
}
|
|
else
|
|
{
|
|
pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */
|
|
pages[i].execute = 1;
|
|
pages[i].read = 1;
|
|
pages[i].write = 1;
|
|
pages[i].supervisor_protect = 0;
|
|
pages[i].global = 1;
|
|
}
|
|
pages[i].locked = 0; /* not locked */
|
|
pages[0].supervisor_protect = 0; /* protect system vectors */
|
|
#else
|
|
#error Unknown machine!
|
|
#endif /* MACHINE_FIREBEE */
|
|
}
|
|
|
|
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
|
|
|
|
/* set data access attributes in ACR0 and ACR1 */
|
|
|
|
/* map PCI address space */
|
|
set_acr0(ACR_W(0) | /* read and write accesses permitted */
|
|
ACR_SP(1) | /* supervisor and user mode access permitted */
|
|
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
|
|
ACR_AMM(0) | /* control region > 16 MB */
|
|
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
|
|
ACR_E(1) | /* enable ACR */
|
|
#if defined(MACHINE_FIREBEE)
|
|
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
|
|
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
|
|
#elif defined(MACHINE_M5484LITE)
|
|
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
|
|
ACR_BA(0x80000000));
|
|
#elif defined(MACHINE_M54455)
|
|
ACR_ADMSK(0x7f) |
|
|
ACR_BA(0x80000000)); /* FIXME: not determined yet */
|
|
#else
|
|
#error unknown machine!
|
|
#endif /* MACHINE_FIREBEE */
|
|
|
|
// set_acr1(0x601fc000);
|
|
|
|
/* data access attributes for BaS in flash */
|
|
|
|
set_acr1(ACR_W(0) |
|
|
ACR_SP(0) |
|
|
ACR_CM(0) |
|
|
#if defined(MACHINE_FIREBEE)
|
|
ACR_CM(ACR_CM_CACHEABLE_WT) |
|
|
#elif defined(MACHINE_M5484LITE)
|
|
ACR_CM(ACR_CM_CACHEABLE_WT) |
|
|
#elif defined(MACHINE_M54455)
|
|
ACR_CM(ACR_CM_CACHEABLE_WT) |
|
|
#else
|
|
#error unknown machine!
|
|
#endif /* MACHINE_FIREBEE */
|
|
ACR_AMM(0) |
|
|
ACR_S(ACR_S_ALL) |
|
|
ACR_E(1) |
|
|
ACR_ADMSK(0x1f) |
|
|
ACR_BA(0xe0000000));
|
|
|
|
/* set instruction access attributes in ACR2 and ACR3 */
|
|
|
|
//set_acr2(0xe007c400);
|
|
|
|
/* instruction access attribute for BaS in flash */
|
|
|
|
set_acr2(ACR_W(0) |
|
|
ACR_SP(0) |
|
|
ACR_CM(0) |
|
|
ACR_CM(ACR_CM_CACHEABLE_WT) |
|
|
ACR_AMM(1) |
|
|
ACR_S(ACR_S_ALL) |
|
|
ACR_E(1) |
|
|
ACR_ADMSK(0x7) |
|
|
ACR_BA(0xe0000000));
|
|
|
|
/* disable ACR1 - 3, essentially disabling all of the above */
|
|
|
|
set_acr3(0x0);
|
|
|
|
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
|
|
|
|
/* create locked TLB entries */
|
|
|
|
flags.cache_mode = CACHE_COPYBACK;
|
|
flags.supervisor_protect = 0;
|
|
flags.read = 1;
|
|
flags.write = 1;
|
|
flags.execute = 1;
|
|
flags.locked = true;
|
|
|
|
/* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */
|
|
mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags);
|
|
|
|
#ifdef _NOT_USED_
|
|
#if defined(MACHINE_FIREBEE)
|
|
/*
|
|
* 0x00d00000 - 0x00e00000 (last megabyte of ST RAM = Falcon video memory) locked ID = 6
|
|
* mapped to physical address 0x60d0'0000 (FPGA video memory)
|
|
* video RAM: read write execute normal write true
|
|
*/
|
|
flags.cache_mode = CACHE_WRITETHROUGH;
|
|
flags.supervisor_protect = 0;
|
|
flags.read = 1;
|
|
flags.write = 1;
|
|
flags.execute = 1;
|
|
flags.locked = true;
|
|
mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, SCA_PAGE_ID, &flags);
|
|
#endif /* MACHINE_FIREBEE */
|
|
#endif
|
|
|
|
/*
|
|
* Make the TOS (in SDRAM) read-only
|
|
* This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
|
|
*/
|
|
flags.cache_mode = CACHE_COPYBACK;
|
|
flags.supervisor_protect = 0;
|
|
flags.read = 1;
|
|
flags.write = 0;
|
|
flags.execute = 1;
|
|
flags.locked = 1;
|
|
mmu_map_page(0xe00000, 0xe00000, MMU_PAGE_SIZE_1M, 0, &flags);
|
|
|
|
#if defined(MACHINE_FIREBEE)
|
|
/*
|
|
* Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
|
|
* area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
|
|
*/
|
|
flags.cache_mode = CACHE_NOCACHE_PRECISE;
|
|
flags.supervisor_protect = 1;
|
|
flags.read = 1;
|
|
flags.write = 1;
|
|
flags.execute = 0;
|
|
flags.locked = 1;
|
|
mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags);
|
|
#endif /* MACHINE_FIREBEE */
|
|
|
|
/*
|
|
* Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
|
|
* virtual address. This is also used (completely) when BaS is in RAM
|
|
*/
|
|
flags.cache_mode = CACHE_COPYBACK;
|
|
flags.supervisor_protect = 1;
|
|
flags.read = 1;
|
|
flags.write = 1;
|
|
flags.execute = 1;
|
|
flags.locked = 1;
|
|
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00200000, SDRAM_START + SDRAM_SIZE - 0x00200000, MMU_PAGE_SIZE_1M, 0, &flags);
|
|
|
|
/*
|
|
* Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
|
|
* virtual address. Used uncached for drivers.
|
|
*/
|
|
flags.cache_mode = CACHE_NOCACHE_PRECISE;
|
|
flags.supervisor_protect = 1;
|
|
flags.read = 1;
|
|
flags.write = 1;
|
|
flags.execute = 0;
|
|
flags.locked = 1;
|
|
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, 0, &flags);
|
|
}
|
|
|
|
|
|
uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,
|
|
uint32_t format_status)
|
|
{
|
|
uint32_t fault = format_status & 0xc030000;
|
|
|
|
dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc);
|
|
// flush_and_invalidate_caches();
|
|
|
|
switch (fault)
|
|
{
|
|
/* if we have a real TLB miss, map the offending page */
|
|
|
|
case 0x04010000: /* TLB miss on opword of instruction fetch */
|
|
case 0x04020000: /* TLB miss on extension word of instruction fetch */
|
|
dbg("MMU ITLB MISS accessing 0x%08x\r\n"
|
|
"FS = 0x%08x\r\n"
|
|
"MMUSR = 0x%08x\r\n"
|
|
"PC = 0x%08x\r\n",
|
|
fault_address, format_status, mmu_sr, pc);
|
|
dbg("fault = 0x%08x\r\n", fault);
|
|
|
|
if (!mmu_map_instruction_page(pc, 0))
|
|
{
|
|
dbg("bus error\r\n");
|
|
return 1; /* bus error */
|
|
}
|
|
|
|
/* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
|
|
if (pc + DEFAULT_PAGE_SIZE < TARGET_ADDRESS)
|
|
{
|
|
/*
|
|
* only do this if the next page is still valid RAM
|
|
*/
|
|
if (!mmu_map_instruction_page(pc + DEFAULT_PAGE_SIZE, 0))
|
|
{
|
|
dbg("bus error\r\n");
|
|
return 1; /* bus error */
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x08020000: /* TLB miss on data write */
|
|
case 0x0c020000: /* TLB miss on data read or read-modify-write */
|
|
dbg("MMU DTLB MISS accessing 0x%08x\r\n"
|
|
"FS = 0x%08x\r\n"
|
|
"MMUSR = 0x%08x\r\n"
|
|
"PC = 0x%08x\r\n",
|
|
fault_address, format_status, mmu_sr, pc);
|
|
dbg("fault = 0x%08x\r\n", fault);
|
|
|
|
if (!mmu_map_data_page(fault_address, 0))
|
|
{
|
|
dbg("bus error\r\n");
|
|
return 1; /* bus error */
|
|
}
|
|
break;
|
|
|
|
/* else issue a bus error */
|
|
default:
|
|
dbg("bus error\r\n");
|
|
return 1; /* signal bus error to caller */
|
|
}
|
|
#ifdef DBG_MMU
|
|
xprintf("\r\n");
|
|
#endif /* DBG_MMU */
|
|
|
|
return 0; /* signal TLB miss handled to caller */
|
|
}
|
|
|
|
|
|
/* TODO: implement */
|
|
|
|
/*
|
|
* API-exposed, externally callable MMU functions
|
|
*/
|
|
|
|
|
|
/*
|
|
* lock data page(s) with address space id asid from address virt to virt + size.
|
|
*
|
|
* ASID probably needs an explanation - this is the "address space id" managed by
|
|
* the MMU.
|
|
* If its value range would be large enough, this could directly map to a PID
|
|
* in MiNT. Unfortunately, the Coldfire MMU only allows an 8 bit value for ASID
|
|
* (with 0 already occupied for the super user/root process and the Firebee video
|
|
* subsystem occupying another one), so we are left with 253 distinct values.
|
|
* MMU software needs to implement some kind of mapping and LRU scheme which will
|
|
* lead to a throwaway of all mappings for processes not seen for a while (and thus
|
|
* to undeterministic response/task switching times when such processes are activated
|
|
* again).
|
|
*
|
|
* FIXME: There is no check for "too many locked pages", currently.
|
|
*
|
|
* return: 0 if failed (page not in translation table), 1 otherwise
|
|
*/
|
|
int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
|
|
{
|
|
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
|
|
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
|
|
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
|
|
int i = 0;
|
|
|
|
while (page_index * DEFAULT_PAGE_SIZE < virt + size)
|
|
{
|
|
if (page->locked)
|
|
{
|
|
dbg("page at %p is already locked. Nothing to do\r\n", virt);
|
|
}
|
|
else
|
|
{
|
|
page->locked = 1;
|
|
mmu_map_data_page(virt, 0);
|
|
i++;
|
|
}
|
|
virt += DEFAULT_PAGE_SIZE;
|
|
}
|
|
|
|
dbg("%d pages locked\r\n", i);
|
|
|
|
return 1; /* success */
|
|
}
|
|
|
|
/*
|
|
* the opposite: unlock data page(s) with address space id asid from address virt to virt + size_t
|
|
*
|
|
* return: 0 if failed (page not found), 1 otherwise
|
|
*/
|
|
int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
|
|
{
|
|
int curr_asid;
|
|
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);
|
|
int page_index = (address & size_mask) / DEFAULT_PAGE_SIZE; /* index into page descriptor array */
|
|
struct mmu_page_descriptor *page = &pages[page_index];
|
|
|
|
curr_asid = set_asid(asid); /* set asid to the one to search for */
|
|
|
|
/* TODO: check for pages[] array bounds */
|
|
|
|
while (page_index * DEFAULT_PAGE_SIZE < address + size)
|
|
{
|
|
MCF_MMU_MMUAR = address + page->supervisor_protect;
|
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB | /* search TLB */
|
|
MCF_MMU_MMUOR_ADR |
|
|
MCF_MMU_MMUOR_RW;
|
|
if (MCF_MMU_MMUSR & MCF_MMU_MMUSR_HIT) /* found */
|
|
{
|
|
#ifdef DBG_MMU
|
|
uint32_t tlb_aa = MCF_MMU_MMUOR >> 16; /* MMU internal allocation address for TLB */
|
|
#endif /* DBG_MMU */
|
|
|
|
MCF_MMU_MMUDR &= ~MCF_MMU_MMUDR_LK; /* clear lock bit */
|
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_UAA |
|
|
MCF_MMU_MMUOR_ACC; /* update TLB */
|
|
|
|
dbg("DTLB %d unlocked\r\n", tlb_aa);
|
|
}
|
|
else
|
|
{
|
|
dbg("%p doesn't seem to be locked??\r\n");
|
|
}
|
|
page_index++;
|
|
}
|
|
set_asid(curr_asid);
|
|
|
|
return 1; /* success */
|
|
}
|
|
|
|
int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
|
|
{
|
|
int i;
|
|
int li = 0;
|
|
int ld = 0;
|
|
|
|
/* Coldfire V4e allocation addresses run from 0 to 63 */
|
|
|
|
for (i = 0; i < 31; i++) /* 0-31 = ITLB AA */
|
|
{
|
|
MCF_MMU_MMUAR = i;
|
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |
|
|
MCF_MMU_MMUOR_ITLB |
|
|
MCF_MMU_MMUOR_RW; /* search ITLB */
|
|
|
|
if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V)
|
|
{
|
|
/* entry is valid */
|
|
if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK)
|
|
{
|
|
li++;
|
|
}
|
|
}
|
|
|
|
}
|
|
for (i = 32; i < 64; i++) /* 32-63 = DTLB AA */
|
|
{
|
|
MCF_MMU_MMUAR = i;
|
|
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |
|
|
MCF_MMU_MMUOR_RW; /* search ITLB */
|
|
|
|
if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V)
|
|
{
|
|
/* entry is valid */
|
|
if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK)
|
|
{
|
|
ld++;
|
|
}
|
|
}
|
|
}
|
|
|
|
*num_itlb = li;
|
|
*num_dtlb = ld;
|
|
|
|
return 1; /* success */
|
|
}
|
|
|
|
uint32_t mmu_report_pagesize(void)
|
|
{
|
|
return DEFAULT_PAGE_SIZE;
|
|
}
|