569 lines
22 KiB
C
569 lines
22 KiB
C
/*
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* File: sysinit.c
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* Purpose: Power-on Reset configuration of the Firebee board.
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#include <stdbool.h>
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#include "MCF5475.h"
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#include "startcf.h"
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#include "cache.h"
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#include "sysinit.h"
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#include "bas_printf.h"
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#include "bas_string.h"
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#include "bas_types.h"
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#include "wait.h"
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#include "util.h"
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#if defined(MACHINE_FIREBEE)
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#include "firebee.h"
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#elif defined(MACHINE_M5484LITE)
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#include "m5484l.h"
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#elif defined(MACHINE_M5475EVB)
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#include "m5475e.h"
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#elif defined(MACHINE_M54455)
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#include "m54455.h"
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#else
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#error "unknown machine"
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#endif /* MACHINE_FIREBEE */
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// #define DEBUG
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#include "debug.h"
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/*
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* init SLICE TIMER 0
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* all = 32.538 sec = 30.736mHz
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* BYT0 = 127.1ms/tick = 7.876Hz offset 0
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* BYT1 = 496.5us/tick = 2.014kHz offset 1
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* BYT2 = 1.939us/tick = 515.6kHz offset 2
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* BYT3 = 7.576ns/tick = 132.00MHz offset 3/
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* count down!!! 132MHz!!!
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*/
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static void init_slt(void)
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{
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MCF_SLT0_STCNT = 0xffffffff;
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MCF_SLT0_SCR = MCF_SLT_SCR_TEN | MCF_SLT_SCR_RUN; /* enable and run continuously */
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}
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/*
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* init GPIO general purpose I/O module
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*/
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static void init_gpio(void)
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{
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/*
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* pad register P.S.:FBCTL and FBCS set correctly at reset
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*/
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/*
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* configure all four 547x GPIO module DMA pins:
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*
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* /DACK1 - DMA acknowledge 1
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* /DACK0 - DMA acknowledge 0
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* /DREQ1 - DMA request 1
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* /DREQ0 - DMA request 0
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*
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* for DMA operation
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*/
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MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0x3) |
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MCF_PAD_PAR_DMA_PAR_DACK1(0x3) |
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MCF_PAD_PAR_DMA_PAR_DREQ1(0x3) |
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MCF_PAD_PAR_DMA_PAR_DREQ0(0x3);
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/*
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* configure FEC0 pin assignment on GPIO module as FEC0
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* configure FEC1 pin assignment (PAR_E17, PAR_E1MII) as GPIO,
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* /IRQ5 and /IRQ6 from GPIO (needs to be disabled on EPORT module, which also can
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* use those INTs).
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*/
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MCF_PAD_PAR_FECI2CIRQ = MCF_PAD_PAR_FECI2CIRQ_PAR_E07 |
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MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII |
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MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO |
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MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC |
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MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO |
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MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC |
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MCF_PAD_PAR_FECI2CIRQ_PAR_SDA |
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MCF_PAD_PAR_FECI2CIRQ_PAR_SCL |
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MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 |
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MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5;
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/*
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* configure PCI Grant pin assignment on GPIO module:
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*
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* /PCIBG4 used as FlexBus /TBST
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* /PCIBG3 used as general purpose I/O
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* /PCIBG2 used as /PCIBG2
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* /PCIBG1 used as /PCIBG1
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* /PCIBG0 used as /PCIBG0
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*/
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#if defined(MACHINE_FIREBEE)
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MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0;
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#elif defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
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MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 |
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MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0;
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#endif /* MACHINE_FIREBEE */
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/*
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* configure PCI request pin assignment on GPIO module:
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* /PCIBR4 as /IRQ4
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* /PCIBR3 as GPIO (PIC)
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* /PCIBR2 as /PCIBR2
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* /PCIBR1 as /PCIBR1
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* /PCIBR0 as /PCIBR0
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*/
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#if defined(MACHINE_FIREBEE)
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MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0;
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#elif defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
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MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 |
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MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0;
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#endif /* MACHINE_FIREBEE */
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/*
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* configure PSC3 pin assignment on GPIO module:
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* /PSC3CTS as /PSC3PTS
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* /PSC3RTS as /PSC3RTS
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* PSC3RXD as PSC3RXD
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* PSC3TXD as PSC3TXD
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*/
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MCF_PAD_PAR_PSC3 = MCF_PAD_PAR_PSC3_PAR_TXD3 | MCF_PAD_PAR_PSC3_PAR_RXD3;
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/*
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* Configure PSC1 pin assignment on GPIO module:
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* - all pins configured for serial interface operation
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*/
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MCF_PAD_PAR_PSC1 = MCF_PAD_PAR_PSC1_PAR_CTS1_CTS |
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MCF_PAD_PAR_PSC1_PAR_RTS1_RTS |
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MCF_PAD_PAR_PSC1_PAR_RXD1 |
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MCF_PAD_PAR_PSC1_PAR_TXD1;
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/*
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* Configure PSC0 Pin Assignment on GPIO module:
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* - all pins configured for serial interface operation
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*/
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MCF_PAD_PAR_PSC0 = MCF_PAD_PAR_PSC0_PAR_CTS0_CTS |
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MCF_PAD_PAR_PSC0_PAR_RTS0_RTS |
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MCF_PAD_PAR_PSC0_PAR_RXD0 |
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MCF_PAD_PAR_PSC0_PAR_TXD0;
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/*
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* Configure all DSPI pins on the GPIO module for there primary function
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*/
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MCF_PAD_PAR_DSPI = MCF_PAD_PAR_DSPI_PAR_SOUT(MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT) |
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MCF_PAD_PAR_DSPI_PAR_SIN(MCF_PAD_PAR_DSPI_PAR_SIN_SIN) |
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MCF_PAD_PAR_DSPI_PAR_SCK(MCF_PAD_PAR_DSPI_PAR_SCK_SCK) |
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MCF_PAD_PAR_DSPI_PAR_CS0(MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0) |
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MCF_PAD_PAR_DSPI_PAR_CS2(MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2) |
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MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3) |
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MCF_PAD_PAR_DSPI_PAR_CS5;
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MCF_PAD_PAR_TIMER = MCF_PAD_PAR_TIMER_PAR_TIN3(MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3) |
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MCF_PAD_PAR_TIMER_PAR_TOUT3 |
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MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) |
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MCF_PAD_PAR_TIMER_PAR_TOUT2;
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}
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/*
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* init serial
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*/
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static void init_serial(void)
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{
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/* PSC0: SER1 */
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MCF_PSC0_PSCSICR = 0; /* PSC control register: select UART mode */
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MCF_PSC0_PSCCSR = 0xDD; /* use TX and RX baud rate from PSC timer */
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MCF_PSC0_PSCCTUR = 0x00; /* =\ */
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#if defined(MACHINE_FIREBEE) || defined(MACHINE_M5475EVB)
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MCF_PSC0_PSCCTLR = 36; /* divide sys_clk by 36 => BAUD RATE = 115200 bps */
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#endif
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#if defined(MACHINE_M5484LITE)
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MCF_PSC0_PSCCTLR = 27; /* LITE board has 100 MHz sys_clk only */
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#endif
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MCF_PSC0_PSCCR = 0x20; /* reset receiver and RxFIFO */
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MCF_PSC0_PSCCR = 0x30; /* reset transmitter and TxFIFO */
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MCF_PSC0_PSCCR = 0x40; /* reset all error status */
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MCF_PSC0_PSCCR = 0x50; /* reset break change interrupt */
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MCF_PSC0_PSCCR = 0x10; /* reset MR pointer */
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MCF_PSC0_PSCIMR = 0x8700; /* enable input port change interrupt, enable delta break interrupt, */
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/* enable receiver interrupt/request, enable transceiver interrupt/request */
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MCF_PSC0_PSCACR = 0x03; /* enable state change of CTS */
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MCF_PSC0_PSCMR1 = 0xb3; /* 8 bit, no parity */
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MCF_PSC0_PSCMR2 = 0x07; /* 1 stop bit */
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MCF_PSC0_PSCRFCR = 0x0F;
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MCF_PSC0_PSCTFCR = 0x0F;
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MCF_PSC0_PSCRFAR = 0x00F0;
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MCF_PSC0_PSCTFAR = 0x00F0;
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MCF_PSC0_PSCOPSET = 0x01;
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MCF_PSC0_PSCCR = 0x05;
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#if defined(MACHINE_FIREBEE) /* PSC3 is not connected to anything on the LITE board */
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/* PSC3: PIC */
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MCF_PSC3_PSCSICR = 0; // UART
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MCF_PSC3_PSCCSR = 0xDD;
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MCF_PSC3_PSCCTUR = 0x00;
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MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200
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MCF_PSC3_PSCCR = 0x20;
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MCF_PSC3_PSCCR = 0x30;
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MCF_PSC3_PSCCR = 0x40;
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MCF_PSC3_PSCCR = 0x50;
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MCF_PSC3_PSCCR = 0x10;
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MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable
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MCF_PSC3_PSCACR = 0x03;
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MCF_PSC3_PSCMR1 = 0xb3;
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MCF_PSC3_PSCMR2 = 0x07;
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MCF_PSC3_PSCRFCR = 0x0F;
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MCF_PSC3_PSCTFCR = 0x0F;
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MCF_PSC3_PSCRFAR = 0x00F0;
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MCF_PSC3_PSCTFAR = 0x00F0;
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MCF_PSC3_PSCOPSET = 0x01;
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MCF_PSC3_PSCCR = 0x05;
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#endif /* MACHINE_FIREBEE */
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}
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/********************************************************************/
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/* Initialize DDR DIMMs on the EVB board */
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/********************************************************************/
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static bool init_ddram(void)
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{
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
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/* Basic configuration and initialization */
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/*
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* SB_E (Bits 9-8): 10 <=> 7.6 mA (SDCKE)
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* SB_C (Bits 7-6): 10 <=> 7.6 mA (SDRAM Clocks)
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* SB_A (Bits 5-4): 10 <=> 7.6 mA (RAS, CAS, SDWE, SDADDR[12:0], and SDBA)
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* SB_S (Bits 3-2): 10 <=> 7.6 mA (SDRDQS)
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* SB_D (Bits 1-0): 10 <=> 7.6 mA (SDRDQS)
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*
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* -> lowest setting the Coldfire SDRAM controller allows
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*/
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MCF_SDRAMC_SDRAMDS = 0x000002AA;/* SDRAMDS configuration */
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#if defined(MACHINE_FIREBEE)
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MCF_SDRAMC_CS0CFG = 0x0000001A; /* SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) */
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MCF_SDRAMC_CS1CFG = 0x0800001A; /* SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) */
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MCF_SDRAMC_CS2CFG = 0x1000001A; /* SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) */
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MCF_SDRAMC_CS3CFG = 0x1800001A; /* SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) */
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/*
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*
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*/
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MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_WTLAT(3) /* Write latency */
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| MCF_SDRAMC_SDCFG1_REF2ACT(8) /* Refresh to Active Delay */
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| MCF_SDRAMC_SDCFG1_PRE2ACT(2) /* Precharge to Active Delay */
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| MCF_SDRAMC_SDCFG1_ACT2RW(2) /* Active to Read/Write Delay */
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| MCF_SDRAMC_SDCFG1_RDLAT(6) /* Read CAS latency */
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| MCF_SDRAMC_SDCFG1_SWT2RD(3) /* Single Write to Read/Write/Precharge delay */
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| MCF_SDRAMC_SDCFG1_SRD2RW(7); /* Single Read to Read/Write/Precharge delay */
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MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BL(7) /* Burst Length */
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| MCF_SDRAMC_SDCFG2_BRD2WT(7) /* Burst Read to Write delay */
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| MCF_SDRAMC_SDCFG2_BWT2RW(6) /* Burst Write to Read/Write/Precharge delay */
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| MCF_SDRAMC_SDCFG2_BRD2PRE(4); /* Burst Read to Read/Precharge delay */
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MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_IPALL /* initiate Precharge All command */
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| MCF_SDRAMC_SDCR_RCNT(13) /* Refresh Count (= (x + 1) * 64 */
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| MCF_SDRAMC_SDCR_MUX(1) /* Muxing control */
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| MCF_SDRAMC_SDCR_DDR
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| MCF_SDRAMC_SDCR_CKE
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| MCF_SDRAMC_SDCR_MODE_EN;
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0) /* Address */
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| MCF_SDRAMC_SDMR_BNKAD(1); /* LEMR */
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0x123)
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| MCF_SDRAMC_SDMR_BNKAD(0); /* LMR */
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */
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MCF_SDRAMC_SDMR = 0x008D0000; /* SDMR (write to LMR) */
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MCF_SDRAMC_SDCR = 0x710D0F00; /* SDCR (lock SDMR and enable refresh) */
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#elif defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
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MCF_SDRAMC_CS0CFG = 0x00000019; /* SDRAM CS0 configuration (64 Mbytes 0000_0000 - 03FF_FFFF) */
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MCF_SDRAMC_CS1CFG = 0x00000000; /* SDRAM CS1 configuration - off */
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MCF_SDRAMC_CS2CFG = 0x00000000; /* SDRAM CS2 configuration - off */
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MCF_SDRAMC_CS3CFG = 0x00000000; /* SDRAM CS3 configuration - off */
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/*
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*
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*/
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MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_WTLAT(3) /* Write latency */
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| MCF_SDRAMC_SDCFG1_REF2ACT(8) /* Refresh to Active Delay */
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| MCF_SDRAMC_SDCFG1_PRE2ACT(2) /* Precharge to Active Delay */
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| MCF_SDRAMC_SDCFG1_ACT2RW(2) /* Active to Read/Write Delay */
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| MCF_SDRAMC_SDCFG1_RDLAT(6) /* Read CAS latency */
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| MCF_SDRAMC_SDCFG1_SWT2RD(3) /* Single Write to Read/Write/Precharge delay */
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| MCF_SDRAMC_SDCFG1_SRD2RW(7); /* Single Read to Read/Write/Precharge delay */
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MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BL(7) /* Burst Length */
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| MCF_SDRAMC_SDCFG2_BRD2WT(7) /* Burst Read to Write delay */
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| MCF_SDRAMC_SDCFG2_BWT2RW(6) /* Burst Write to Read/Write/Precharge delay */
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| MCF_SDRAMC_SDCFG2_BRD2PRE(4); /* Burst Read to Read/Precharge delay */
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MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_IPALL /* initiate Precharge All command */
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| MCF_SDRAMC_SDCR_RCNT(13) /* Refresh Count (= (x + 1) * 64 */
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| MCF_SDRAMC_SDCR_MUX(1) /* Muxing control */
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| MCF_SDRAMC_SDCR_DDR
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| MCF_SDRAMC_SDCR_CKE
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| MCF_SDRAMC_SDCR_MODE_EN;
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0) /* Address */
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| MCF_SDRAMC_SDMR_BNKAD(1); /* LEMR */
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0x123)
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| MCF_SDRAMC_SDMR_BNKAD(0); /* LMR */
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */
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MCF_SDRAMC_SDMR = 0x008D0000; /* SDMR (write to LMR) */
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MCF_SDRAMC_SDCR = 0x710D0F00; /* SDCR (lock SDMR and enable refresh) */
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#endif /* MACHINE_FIREBEE */
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return true;
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}
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return false;
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}
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/*
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* initialize FlexBus chip select registers
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*/
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static void init_fbcs()
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{
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/* Flash */
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MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOTFLASH_BASE_ADDRESS); /* flash base address */
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MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | /* 16 bit word access */
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MCF_FBCS_CSCR_WS(8)| /* 6 wait states */
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MCF_FBCS_CSCR_AA | /* auto /TA acknowledge */
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MCF_FBCS_CSCR_ASET(1) | /* assert chip select on second rising edge after address assertion */
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MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */
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MCF_FBCS0_CSMR = BOOTFLASH_BAM |
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MCF_FBCS_CSMR_V; /* enable */
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#if defined(MACHINE_FIREBEE) /* FBC setup for FireBee */
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MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF80000); /* ATARI I/O address range */
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MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
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| MCF_FBCS_CSCR_WS(32) /* 32 wait states */
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// | MCF_FBCS_CSCR_BSTR /* burst read enable */
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// | MCF_FBCS_CSCR_BSTW /* burst write enable */
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| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
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MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V;
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MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */
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MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
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| MCF_FBCS_CSCR_WS(32) /* 4 wait states */
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| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
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MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */
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| MCF_FBCS_CSMR_V);
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MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000); /* IDE I/O address BURST! */
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MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
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| MCF_FBCS_CSCR_WS(16) /* 16 wait states */
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| MCF_FBCS_CSCR_BSTR /* Burst read enable */
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| MCF_FBCS_CSCR_BSTW /* Burst write enable */
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| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
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MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_512K /* FFF0'0000-FFF7'FFFF */
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| MCF_FBCS_CSMR_V);
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/*
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* Note: burst read/write settings of the following FBCS are purely "cosmetical".
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* The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit,
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* i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port.
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* Enabling burst on a 32 bit port has no effect (unfortunately).
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*/
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MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000); /* video ram area, FB_CS4 not used, decoded on FPGA */
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MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32 bit port */
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| MCF_FBCS_CSCR_WS(32) /* 0 wait states */
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| MCF_FBCS_CSCR_AA /* /TA auto acknowledge */
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| MCF_FBCS_CSCR_BSTR /* burst read enable */
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| MCF_FBCS_CSCR_BSTW; /* burst write enable */
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MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G /* 4000'0000-7FFF'FFFF */
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| MCF_FBCS_CSMR_V;
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/* disable FBCS5 on Firebee */
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MCF_FBCS5_CSAR = 0x0;
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MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_8
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| MCF_FBCS_CSCR_BSTR
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| MCF_FBCS_CSCR_BSTW
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| MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */
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MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_1G;
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//| MCF_FBCS_CSMR_V;
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#elif defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
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/* disable other FBCS for now */
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MCF_FBCS1_CSMR = 0;
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MCF_FBCS2_CSMR = 0;
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MCF_FBCS3_CSMR = 0;
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MCF_FBCS4_CSMR = 0;
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/*
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* the FireEngine needs AA for its CPLD accessed registers
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*/
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MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000);
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MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access 16 bit wide */
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MCF_FBCS_CSCR_WS(32) | /* 32 wait states */
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MCF_FBCS_CSCR_ASET(1) | /* chip select on second rising clock edge */
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MCF_FBCS_CSCR_AA; /* auto acknowledge */
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MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M | /* maps 0x60000000 to 0x68000000 */
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MCF_FBCS_CSMR_V;
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#endif /* MACHINE_FIREBEE */
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}
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/* Symbols from the linker script */
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extern uint8_t _STRAM_END[];
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#define STRAM_END ((uint32_t)_STRAM_END)
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extern uint8_t _FIRETOS[];
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#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */
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extern uint8_t _BAS_LMA[];
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#define BAS_LMA (&_BAS_LMA[0]) /* where the BaS is stored in flash */
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extern uint8_t _BAS_IN_RAM[];
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#define BAS_IN_RAM (&_BAS_IN_RAM[0]) /* where the BaS is run in RAM */
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extern uint8_t _BAS_SIZE[];
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#define BAS_SIZE ((uint32_t)_BAS_SIZE) /* size of the BaS, in bytes */
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extern uint8_t _FASTRAM_END[];
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#define FASTRAM_END ((uint32_t)_FASTRAM_END)
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extern uint8_t _BAS_RESIDENT_TEXT[];
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#define BAS_RESIDENT_TEXT ((uint32_t) _BAS_RESIDENT_TEXT)
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extern uint8_t _BAS_RESIDENT_TEXT_SIZE[];
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#define BAS_RESIDENT_TEXT_SIZE ((uint32_t) _BAS_RESIDENT_TEXT_SIZE)
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static void clear_bss_segment(void)
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{
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extern uint8_t _BAS_BSS_START[];
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uint8_t * BAS_BSS_START = &_BAS_BSS_START[0];
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extern uint8_t _BAS_BSS_END[];
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uint8_t *BAS_BSS_END = &_BAS_BSS_END[0];
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int i;
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for (i = 0; i < BAS_BSS_END - BAS_BSS_START + 1; i++)
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BAS_BSS_START[i] = 0;
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}
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void initialize_hardware(void)
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{
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init_gpio();
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init_serial();
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/*
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* Clear the Reset Status Register
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*/
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MCF_SIU_RSR = (MCF_SIU_RSR_RST
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| MCF_SIU_RSR_RSTWD
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| MCF_SIU_RSR_RSTJTG);
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/* make sure MMU is disabled */
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MCF_MMU_MMUCR = 0; /* MMU off */
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NOP(); /* force pipeline sync */
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init_slt();
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init_fbcs();
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init_ddram();
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#if defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
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* (uint8_t *) 0x61000000 = 1 << 7;
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#endif /* MACHINE_M5484LITE */
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|
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/*
|
|
* save the planet (and reduce case heat): disable clocks of unused SOC modules
|
|
*/
|
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MCF_CLOCK_SPCR = 0xffffffff & ~(
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0 | /* leave memory clock enabled */
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0 | /* leave PCI clock enabled */
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0 | /* leave FlexBus clock enabled */
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MCF_CLOCK_SPCR_CAN0EN | /* disable CAN0 */
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0 | /* leave DMA clock enabled */
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0 | /* leave FEC0 clock enabled */
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MCF_CLOCK_SPCR_FEC1EN | /* disable FEC1 */
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MCF_CLOCK_SPCR_USBEN | /* disable USB slave */
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0 | /* leave PSC clock enabled */
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MCF_CLOCK_SPCR_CAN1EN | /* disable CAN1 */
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MCF_CLOCK_SPCR_CRYENA | /* disable crypto clock A */
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MCF_CLOCK_SPCR_CRYENB | /* disable crypto clock B */
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0 /* leave core clock enabled */
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);
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/* the following only makes sense _after_ DDRAM has been initialized */
|
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clear_bss_segment();
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if (BAS_LMA != BAS_IN_RAM)
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{
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int i;
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|
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/* although tempting, do not use memcpy() here */
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for (i = 0; i < BAS_SIZE; i++)
|
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{
|
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BAS_IN_RAM[i] = BAS_LMA[i];
|
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}
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|
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/* we have copied a code area, so flush the caches */
|
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flush_and_invalidate_caches();
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}
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|
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/* jump into the BaS */
|
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extern void BaS(void);
|
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BaS();
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}
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