#ifndef _RADEON_H #define _RADEON_H /* to fix: multiple definition from Linux defines and Xfree defines added for VIDX and RENDER */ #define RADEON_REGSIZE 0x4000 #define MM_INDEX 0x0000 #define MM_DATA 0x0004 #define RADEON_BIOS_0_SCRATCH 0x0010 #define RADEON_BIOS_1_SCRATCH 0x0014 #define RADEON_BIOS_2_SCRATCH 0x0018 #define RADEON_BIOS_3_SCRATCH 0x001c #define RADEON_BIOS_4_SCRATCH 0x0020 #define RADEON_BIOS_5_SCRATCH 0x0024 #define RADEON_BIOS_6_SCRATCH 0x0028 #define RADEON_BIOS_7_SCRATCH 0x002c #define BUS_CNTL 0x0030 #define BUS_CNTL1 0x0034 #define MEM_VGA_WP_SEL 0x0038 #define MEM_VGA_RP_SEL 0x003C #define GEN_INT_CNTL 0x0040 #define GEN_INT_STATUS 0x0044 #define HI_STAT 0x004C #define CRTC_GEN_CNTL 0x0050 #define CRTC_EXT_CNTL 0x0054 #define DAC_CNTL 0x0058 #define CRTC_STATUS 0x005C #define GPIO_VGA_DDC 0x0060 #define GPIO_DVI_DDC 0x0064 #define GPIO_MONID 0x0068 #define GPIO_CRT2_DDC 0x006c #define I2C_CNTL_1 0x0094 #define CONFIG_CNTL 0x00E0 #define CONFIG_MEMSIZE 0x00F8 #define CONFIG_APER_0_BASE 0x0100 #define CONFIG_APER_1_BASE 0x0104 #define CONFIG_APER_SIZE 0x0108 #define CONFIG_REG_1_BASE 0x010C #define CONFIG_REG_APER_SIZE 0x0110 #define PAD_AGPINPUT_DELAY 0x0164 #define PAD_CTLR_STRENGTH 0x0168 #define PAD_CTLR_UPDATE 0x016C #define PAD_CTLR_MISC 0x0aa0 #define AGP_CNTL 0x0174 #define BM_STATUS 0x0160 #define CAP0_TRIG_CNTL 0x0950 #define CAP1_TRIG_CNTL 0x09c0 #define VENDOR_ID 0x0F00 #define DEVICE_ID 0x0F02 #define COMMAND 0x0F04 #define STATUS 0x0F06 #define REVISION_ID 0x0F08 #define REGPROG_INF 0x0F09 #define SUB_CLASS 0x0F0A #define BASE_CODE 0x0F0B #define CACHE_LINE 0x0F0C #define LATENCY 0x0F0D #define HEADER 0x0F0E #define BIST 0x0F0F #define REG_MEM_BASE 0x0F10 #define REG_IO_BASE 0x0F14 #define REG_REG_BASE 0x0F18 #define ADAPTER_ID 0x0F2C #define BIOS_ROM 0x0F30 #define CAPABILITIES_PTR 0x0F34 #define INTERRUPT_LINE 0x0F3C #define INTERRUPT_PIN 0x0F3D #define MIN_GRANT 0x0F3E #define MAX_LATENCY 0x0F3F #define ADAPTER_ID_W 0x0F4C #define PMI_CAP_ID 0x0F50 #define PMI_NXT_CAP_PTR 0x0F51 #define PMI_PMC_REG 0x0F52 #define PM_STATUS 0x0F54 #define PMI_DATA 0x0F57 #define AGP_CAP_ID 0x0F58 #define AGP_STATUS 0x0F5C #define AGP_COMMAND 0x0F60 #define AIC_CTRL 0x01D0 #define AIC_STAT 0x01D4 #define AIC_PT_BASE 0x01D8 #define AIC_LO_ADDR 0x01DC #define AIC_HI_ADDR 0x01E0 #define AIC_TLB_ADDR 0x01E4 #define AIC_TLB_DATA 0x01E8 #define DAC_CNTL2 0x007c #define MEM_CNTL 0x0140 #define MC_CNTL 0x0140 #define EXT_MEM_CNTL 0x0144 #define MC_TIMING_CNTL 0x0144 #define MC_AGP_LOCATION 0x014C #define MEM_IO_CNTL_A0 0x0178 #define MEM_REFRESH_CNTL 0x0178 #define MEM_INIT_LATENCY_TIMER 0x0154 #define MC_INIT_GFX_LAT_TIMER 0x0154 #define MEM_SDRAM_MODE_REG 0x0158 #define AGP_BASE 0x0170 #define MEM_IO_CNTL_A1 0x017C #define MC_READ_CNTL_AB 0x017C #define MEM_IO_CNTL_B0 0x0180 #define MC_INIT_MISC_LAT_TIMER 0x0180 #define MEM_IO_CNTL_B1 0x0184 #define MC_IOPAD_CNTL 0x0184 #define MC_DEBUG 0x0188 #define MC_STATUS 0x0150 #define MEM_IO_OE_CNTL 0x018C #define MC_CHIP_IO_OE_CNTL_AB 0x018C #define MC_FB_LOCATION 0x0148 #define HOST_PATH_CNTL 0x0130 #define HDP_DEBUG 0x0138 #define SW_SEMAPHORE 0x013C #define TEST_DEBUG_CNTL 0x0120 #define TEST_DEBUG_MUX 0x0124 #define TEST_DEBUG_OUT 0x012c #define CRTC2_GEN_CNTL 0x03f8 #define CRTC2_DISPLAY_BASE_ADDR 0x033c #define SURFACE_CNTL 0x0B00 #define SURFACE0_LOWER_BOUND 0x0B04 #define SURFACE1_LOWER_BOUND 0x0B14 #define SURFACE2_LOWER_BOUND 0x0B24 #define SURFACE3_LOWER_BOUND 0x0B34 #define SURFACE4_LOWER_BOUND 0x0B44 #define SURFACE5_LOWER_BOUND 0x0B54 #define SURFACE6_LOWER_BOUND 0x0B64 #define SURFACE7_LOWER_BOUND 0x0B74 #define SURFACE0_UPPER_BOUND 0x0B08 #define SURFACE1_UPPER_BOUND 0x0B18 #define SURFACE2_UPPER_BOUND 0x0B28 #define SURFACE3_UPPER_BOUND 0x0B38 #define SURFACE4_UPPER_BOUND 0x0B48 #define SURFACE5_UPPER_BOUND 0x0B58 #define SURFACE6_UPPER_BOUND 0x0B68 #define SURFACE7_UPPER_BOUND 0x0B78 #define SURFACE0_INFO 0x0B0C #define SURFACE1_INFO 0x0B1C #define SURFACE2_INFO 0x0B2C #define SURFACE3_INFO 0x0B3C #define SURFACE4_INFO 0x0B4C #define SURFACE5_INFO 0x0B5C #define SURFACE6_INFO 0x0B6C #define SURFACE7_INFO 0x0B7C #define SURFACE_ACCESS_FLAGS 0x0BF8 #define SURFACE_ACCESS_CLR 0x0BFC #define BRUSH_DATA0 0x1480 #define BRUSH_DATA1 0x1484 #define BRUSH_DATA2 0x1488 #define BRUSH_DATA3 0x148c #define BRUSH_DATA4 0x1490 #define BRUSH_DATA5 0x1494 #define BRUSH_DATA7 0x149c #define BRUSH_DATA8 0x14a0 #define BRUSH_DATA9 0x14a4 #define BRUSH_DATA10 0x14a8 #define BRUSH_DATA11 0x14ac #define BRUSH_DATA12 0x14b0 #define BRUSH_DATA13 0x14b4 #define BRUSH_DATA14 0x14b8 #define BRUSH_DATA15 0x14bc #define BRUSH_DATA16 0x14c0 #define BRUSH_DATA17 0x14c4 #define BRUSH_DATA18 0x14c8 #define BRUSH_DATA19 0x14cc #define BRUSH_DATA20 0x14d0 #define BRUSH_DATA21 0x14d4 #define BRUSH_DATA22 0x14d8 #define BRUSH_DATA23 0x14dc #define BRUSH_DATA24 0x14e0 #define BRUSH_DATA25 0x14e4 #define BRUSH_DATA26 0x14e8 #define BRUSH_DATA27 0x14ec #define BRUSH_DATA28 0x14f0 #define BRUSH_DATA29 0x14f4 #define BRUSH_DATA30 0x14f8 #define BRUSH_DATA31 0x14fc #define BRUSH_DATA32 0x1500 #define BRUSH_DATA33 0x1504 #define BRUSH_DATA34 0x1508 #define BRUSH_DATA35 0x150c #define BRUSH_DATA36 0x1510 #define BRUSH_DATA37 0x1514 #define BRUSH_DATA38 0x1518 #define BRUSH_DATA39 0x151c #define BRUSH_DATA40 0x1520 #define BRUSH_DATA41 0x1524 #define BRUSH_DATA42 0x1528 #define BRUSH_DATA43 0x152c #define BRUSH_DATA44 0x1530 #define BRUSH_DATA45 0x1534 #define BRUSH_DATA46 0x1538 #define BRUSH_DATA47 0x153c #define BRUSH_DATA48 0x1540 #define BRUSH_DATA49 0x1544 #define BRUSH_DATA50 0x1548 #define BRUSH_DATA51 0x154c #define BRUSH_DATA52 0x1550 #define BRUSH_DATA53 0x1554 #define BRUSH_DATA54 0x1558 #define BRUSH_DATA55 0x155c #define BRUSH_DATA56 0x1560 #define BRUSH_DATA57 0x1564 #define BRUSH_DATA58 0x1568 #define BRUSH_DATA59 0x156c #define BRUSH_DATA6 0x1498 #define BRUSH_DATA60 0x1570 #define BRUSH_DATA61 0x1574 #define BRUSH_DATA62 0x1578 #define BRUSH_DATA63 0x157c #define BRUSH_SCALE 0x1470 #define BRUSH_Y_X 0x1474 #define RB3D_CNTL 0x1C3C #define WAIT_UNTIL 0x1720 #define ISYNC_CNTL 0x1724 #define RBBM_GUICNTL 0x172C #define RBBM_STATUS 0x0E40 #define RBBM_STATUS_alt_1 0x1740 #define RBBM_CNTL 0x00EC #define RBBM_CNTL_alt_1 0x0E44 #define RBBM_SOFT_RESET 0x00F0 #define RBBM_SOFT_RESET_alt_1 0x0E48 #define NQWAIT_UNTIL 0x0E50 #define RBBM_DEBUG 0x0E6C #define RBBM_CMDFIFO_ADDR 0x0E70 #define RBBM_CMDFIFO_DATAL 0x0E74 #define RBBM_CMDFIFO_DATAH 0x0E78 #define RBBM_CMDFIFO_STAT 0x0E7C #define PALETTE_INDEX 0x00B0 #define PALETTE_DATA 0x00B4 #define PALETTE_30_DATA 0x00B8 #define CRTC_H_TOTAL_DISP 0x0200 #define CRTC_H_SYNC_STRT_WID 0x0204 #define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_SYNC_STRT_WID 0x020C #define CRTC_VLINE_CRNT_VLINE 0x0210 #define CRTC_CRNT_FRAME 0x0214 #define CRTC_GUI_TRIG_VLINE 0x0218 #define CRTC_DEBUG 0x021C #define CRTC_OFFSET_RIGHT 0x0220 #define CRTC_OFFSET 0x0224 #define CRTC_OFFSET_CNTL 0x0228 #define CRTC_PITCH 0x022C #define OVR_CLR 0x0230 #define OVR_WID_LEFT_RIGHT 0x0234 #define OVR_WID_TOP_BOTTOM 0x0238 #define DISPLAY_BASE_ADDR 0x023C #define SNAPSHOT_VH_COUNTS 0x0240 #define SNAPSHOT_F_COUNT 0x0244 #define N_VIF_COUNT 0x0248 #define SNAPSHOT_VIF_COUNT 0x024C #define FP_CRTC_H_TOTAL_DISP 0x0250 #define FP_CRTC_V_TOTAL_DISP 0x0254 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C #define CUR_OFFSET 0x0260 #define CUR_HORZ_VERT_POSN 0x0264 #define CUR_HORZ_VERT_OFF 0x0268 #define CUR_CLR0 0x026C #define CUR_CLR1 0x0270 #define FP_HORZ_VERT_ACTIVE 0x0278 #define CRTC_MORE_CNTL 0x027C #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define DAC_EXT_CNTL 0x0280 #define FP_GEN_CNTL 0x0284 #define FP_HORZ_STRETCH 0x028C #define FP_VERT_STRETCH 0x0290 #define FP_H_SYNC_STRT_WID 0x02C4 #define FP_V_SYNC_STRT_WID 0x02C8 #define AUX_WINDOW_HORZ_CNTL 0x02D8 #define AUX_WINDOW_VERT_CNTL 0x02DC //#define DDA_CONFIG 0x02e0 //#define DDA_ON_OFF 0x02e4 #define DVI_I2C_CNTL_1 0x02e4 #define GRPH_BUFFER_CNTL 0x02F0 #define GRPH2_BUFFER_CNTL 0x03F0 #define VGA_BUFFER_CNTL 0x02F4 #define OV0_Y_X_START 0x0400 #define OV0_Y_X_END 0x0404 #define OV0_PIPELINE_CNTL 0x0408 #define OV0_REG_LOAD_CNTL 0x0410 #define OV0_SCALE_CNTL 0x0420 #define OV0_V_INC 0x0424 #define OV0_P1_V_ACCUM_INIT 0x0428 #define OV0_P23_V_ACCUM_INIT 0x042C #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 #define OV0_BASE_ADDR 0x043C #define OV0_VID_BUF0_BASE_ADRS 0x0440 #define OV0_VID_BUF1_BASE_ADRS 0x0444 #define OV0_VID_BUF2_BASE_ADRS 0x0448 #define OV0_VID_BUF3_BASE_ADRS 0x044C #define OV0_VID_BUF4_BASE_ADRS 0x0450 #define OV0_VID_BUF5_BASE_ADRS 0x0454 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 #define OV0_AUTO_FLIP_CNTRL 0x0470 #define OV0_DEINTERLACE_PATTERN 0x0474 #define OV0_SUBMIT_HISTORY 0x0478 #define OV0_H_INC 0x0480 #define OV0_STEP_BY 0x0484 #define OV0_P1_H_ACCUM_INIT 0x0488 #define OV0_P23_H_ACCUM_INIT 0x048C #define OV0_P1_X_START_END 0x0494 #define OV0_P2_X_START_END 0x0498 #define OV0_P3_X_START_END 0x049C #define OV0_FILTER_CNTL 0x04A0 #define OV0_FOUR_TAP_COEF_0 0x04B0 #define OV0_FOUR_TAP_COEF_1 0x04B4 #define OV0_FOUR_TAP_COEF_2 0x04B8 #define OV0_FOUR_TAP_COEF_3 0x04BC #define OV0_FOUR_TAP_COEF_4 0x04C0 #define OV0_FLAG_CNTRL 0x04DC #define OV0_SLICE_CNTL 0x04E0 #define OV0_VID_KEY_CLR_LOW 0x04E4 #define OV0_VID_KEY_CLR_HIGH 0x04E8 #define OV0_GRPH_KEY_CLR_LOW 0x04EC #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 #define OV0_KEY_CNTL 0x04F4 #define OV0_TEST 0x04F8 #define SUBPIC_CNTL 0x0540 #define SUBPIC_DEFCOLCON 0x0544 #define SUBPIC_Y_X_START 0x054C #define SUBPIC_Y_X_END 0x0550 #define SUBPIC_V_INC 0x0554 #define SUBPIC_H_INC 0x0558 #define SUBPIC_BUF0_OFFSET 0x055C #define SUBPIC_BUF1_OFFSET 0x0560 #define SUBPIC_LC0_OFFSET 0x0564 #define SUBPIC_LC1_OFFSET 0x0568 #define SUBPIC_PITCH 0x056C #define SUBPIC_BTN_HLI_COLCON 0x0570 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 #define SUBPIC_PALETTE_INDEX 0x057C #define SUBPIC_PALETTE_DATA 0x0580 #define SUBPIC_H_ACCUM_INIT 0x0584 #define SUBPIC_V_ACCUM_INIT 0x0588 #define DISP_MISC_CNTL 0x0D00 #define DAC_MACRO_CNTL 0x0D04 #define DISP_PWR_MAN 0x0D08 #define DISP_TEST_DEBUG_CNTL 0x0D10 #define DISP_HW_DEBUG 0x0D14 #define DAC_CRC_SIG1 0x0D18 #define DAC_CRC_SIG2 0x0D1C #define OV0_LIN_TRANS_A 0x0D20 #define OV0_LIN_TRANS_B 0x0D24 #define OV0_LIN_TRANS_C 0x0D28 #define OV0_LIN_TRANS_D 0x0D2C #define OV0_LIN_TRANS_E 0x0D30 #define OV0_LIN_TRANS_F 0x0D34 #define OV0_GAMMA_0_F 0x0D40 #define OV0_GAMMA_10_1F 0x0D44 #define OV0_GAMMA_20_3F 0x0D48 #define OV0_GAMMA_40_7F 0x0D4C #define OV0_GAMMA_380_3BF 0x0D50 #define OV0_GAMMA_3C0_3FF 0x0D54 #define DISP_MERGE_CNTL 0x0D60 #define DISP_OUTPUT_CNTL 0x0D64 #define DISP_LIN_TRANS_GRPH_A 0x0D80 #define DISP_LIN_TRANS_GRPH_B 0x0D84 #define DISP_LIN_TRANS_GRPH_C 0x0D88 #define DISP_LIN_TRANS_GRPH_D 0x0D8C #define DISP_LIN_TRANS_GRPH_E 0x0D90 #define DISP_LIN_TRANS_GRPH_F 0x0D94 #define DISP_LIN_TRANS_VID_A 0x0D98 #define DISP_LIN_TRANS_VID_B 0x0D9C #define DISP_LIN_TRANS_VID_C 0x0DA0 #define DISP_LIN_TRANS_VID_D 0x0DA4 #define DISP_LIN_TRANS_VID_E 0x0DA8 #define DISP_LIN_TRANS_VID_F 0x0DAC #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 #define RMX_HORZ_PHASE 0x0DBC #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 #define DAC_BROAD_PULSE 0x0DC4 #define DAC_SKEW_CLKS 0x0DC8 #define DAC_INCR 0x0DCC #define DAC_NEG_SYNC_LEVEL 0x0DD0 #define DAC_POS_SYNC_LEVEL 0x0DD4 #define DAC_BLANK_LEVEL 0x0DD8 #define CLOCK_CNTL_INDEX 0x0008 #define CLOCK_CNTL_DATA 0x000C #define CP_RB_CNTL 0x0704 #define CP_RB_BASE 0x0700 #define CP_RB_RPTR_ADDR 0x070C #define CP_RB_RPTR 0x0710 #define CP_RB_WPTR 0x0714 #define CP_RB_WPTR_DELAY 0x0718 #define CP_IB_BASE 0x0738 #define CP_IB_BUFSZ 0x073C #define SCRATCH_REG0 0x15E0 #define GUI_SCRATCH_REG0 0x15E0 #define SCRATCH_REG1 0x15E4 #define GUI_SCRATCH_REG1 0x15E4 #define SCRATCH_REG2 0x15E8 #define GUI_SCRATCH_REG2 0x15E8 #define SCRATCH_REG3 0x15EC #define GUI_SCRATCH_REG3 0x15EC #define SCRATCH_REG4 0x15F0 #define GUI_SCRATCH_REG4 0x15F0 #define SCRATCH_REG5 0x15F4 #define GUI_SCRATCH_REG5 0x15F4 #define SCRATCH_UMSK 0x0770 #define SCRATCH_ADDR 0x0774 #define DP_BRUSH_FRGD_CLR 0x147C #define DP_BRUSH_BKGD_CLR 0x1478 #define DST_LINE_START 0x1600 #define DST_LINE_END 0x1604 #define DST_LINE_PATCOUNT 0x1608 #define SRC_OFFSET 0x15AC #define SRC_PITCH 0x15B0 #define SRC_TILE 0x1704 #define SRC_PITCH_OFFSET 0x1428 #define SRC_X 0x1414 #define SRC_Y 0x1418 #define SRC_X_Y 0x1590 #define SRC_Y_X 0x1434 #define DST_Y_X 0x1438 #define DST_WIDTH_HEIGHT 0x1598 #define DST_HEIGHT_WIDTH 0x143c #define DST_OFFSET 0x1404 #define SRC_CLUT_ADDRESS 0x1780 #define SRC_CLUT_DATA 0x1784 #define SRC_CLUT_DATA_RD 0x1788 #define HOST_DATA0 0x17C0 #define HOST_DATA1 0x17C4 #define HOST_DATA2 0x17C8 #define HOST_DATA3 0x17CC #define HOST_DATA4 0x17D0 #define HOST_DATA5 0x17D4 #define HOST_DATA6 0x17D8 #define HOST_DATA7 0x17DC #define HOST_DATA_LAST 0x17E0 #define DP_SRC_ENDIAN 0x15D4 #define DP_SRC_FRGD_CLR 0x15D8 #define DP_SRC_BKGD_CLR 0x15DC #define SC_LEFT 0x1640 #define SC_RIGHT 0x1644 #define SC_TOP 0x1648 #define SC_BOTTOM 0x164C #define SRC_SC_RIGHT 0x1654 #define SRC_SC_BOTTOM 0x165C #define DP_CNTL 0x16C0 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 #define DP_DATATYPE 0x16C4 #define DP_MIX 0x16C8 #define DP_WRITE_MSK 0x16CC #define DP_XOP 0x17F8 #define CLR_CMP_CLR_SRC 0x15C4 #define CLR_CMP_CLR_DST 0x15C8 #define CLR_CMP_CNTL 0x15C0 #define CLR_CMP_MSK 0x15CC #define DSTCACHE_MODE 0x1710 #define DSTCACHE_CTLSTAT 0x1714 #define DEFAULT_PITCH_OFFSET 0x16E0 #define DEFAULT_OFFSET 0x16e0 #define DEFAULT_PITCH 0x16e4 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 #define DEFAULT_SC_TOP_LEFT 0x16EC #define SRC_PITCH_OFFSET 0x1428 #define DST_PITCH_OFFSET 0x142C #define DP_GUI_MASTER_CNTL 0x146C #define SC_TOP_LEFT 0x16EC #define SC_BOTTOM_RIGHT 0x16F0 #define SRC_SC_BOTTOM_RIGHT 0x16F4 #define RB2D_DSTCACHE_MODE 0x3428 #define RB2D_DSTCACHE_CTLSTAT 0x342C #define LVDS_GEN_CNTL 0x02d0 #define LVDS_PLL_CNTL 0x02d4 #define FP2_GEN_CNTL 0x0288 #define TMDS_CNTL 0x0294 #define TMDS_CRC 0x02a0 #define TMDS_TRANSMITTER_CNTL 0x02a4 #define MPP_TB_CONFIG 0x01c0 #define PAMAC0_DLY_CNTL 0x0a94 #define PAMAC1_DLY_CNTL 0x0a98 #define PAMAC2_DLY_CNTL 0x0a9c #define FW_CNTL 0x0118 #define FCP_CNTL 0x0910 #define VGA_DDA_ON_OFF 0x02ec #define TV_MASTER_CNTL 0x0800 #define BIOS_0_SCRATCH 0x0010 #define BIOS_1_SCRATCH 0x0014 #define BIOS_2_SCRATCH 0x0018 #define BIOS_3_SCRATCH 0x001c #define BIOS_4_SCRATCH 0x0020 #define BIOS_5_SCRATCH 0x0024 #define BIOS_6_SCRATCH 0x0028 #define BIOS_7_SCRATCH 0x002c #define HDP_SOFT_RESET (1 << 26) #define TV_DAC_CNTL 0x088c #define GPIOPAD_MASK 0x0198 #define GPIOPAD_A 0x019c #define GPIOPAD_EN 0x01a0 #define GPIOPAD_Y 0x01a4 #define ZV_LCDPAD_MASK 0x01a8 #define ZV_LCDPAD_A 0x01ac #define ZV_LCDPAD_EN 0x01b0 #define ZV_LCDPAD_Y 0x01b4 /* PLL Registers */ #define CLK_PIN_CNTL 0x0001 #define PPLL_CNTL 0x0002 #define PPLL_REF_DIV 0x0003 #define PPLL_DIV_0 0x0004 #define PPLL_DIV_1 0x0005 #define PPLL_DIV_2 0x0006 #define PPLL_DIV_3 0x0007 #define VCLK_ECP_CNTL 0x0008 #define HTOTAL_CNTL 0x0009 #define M_SPLL_REF_FB_DIV 0x000a #define AGP_PLL_CNTL 0x000b #define SPLL_CNTL 0x000c #define SCLK_CNTL 0x000d #define MPLL_CNTL 0x000e #define MDLL_CKO 0x000f #define MDLL_RDCKA 0x0010 #define MCLK_CNTL 0x0012 #define AGP_PLL_CNTL 0x000b #define PLL_TEST_CNTL 0x0013 #define CLK_PWRMGT_CNTL 0x0014 #define PLL_PWRMGT_CNTL 0x0015 #define MCLK_MISC 0x001f #define P2PLL_CNTL 0x002a #define P2PLL_REF_DIV 0x002b #define PIXCLKS_CNTL 0x002d #define SCLK_MORE_CNTL 0x0035 /* MCLK_CNTL bit constants */ #define FORCEON_MCLKA (1 << 16) #define FORCEON_MCLKB (1 << 17) #define FORCEON_YCLKA (1 << 18) #define FORCEON_YCLKB (1 << 19) #define FORCEON_MC (1 << 20) #define FORCEON_AIC (1 << 21) /* SCLK_CNTL bit constants */ #define DYN_STOP_LAT_MASK 0x00007ff8 #define CP_MAX_DYN_STOP_LAT 0x0008 #define SCLK_FORCEON_MASK 0xffff8000 /* SCLK_MORE_CNTL bit constants */ #define SCLK_MORE_FORCEON 0x0700 /* BUS_CNTL bit constants */ #define BUS_DBL_RESYNC 0x00000001 #define BUS_MSTR_RESET 0x00000002 #define BUS_FLUSH_BUF 0x00000004 #define BUS_STOP_REQ_DIS 0x00000008 #define BUS_ROTATION_DIS 0x00000010 #define BUS_MASTER_DIS 0x00000040 #define BUS_ROM_WRT_EN 0x00000080 #define BUS_DIS_ROM 0x00001000 #define BUS_PCI_READ_RETRY_EN 0x00002000 #define BUS_AGP_AD_STEPPING_EN 0x00004000 #define BUS_PCI_WRT_RETRY_EN 0x00008000 #define BUS_MSTR_RD_MULT 0x00100000 #define BUS_MSTR_RD_LINE 0x00200000 #define BUS_SUSPEND 0x00400000 #define LAT_16X 0x00800000 #define BUS_RD_DISCARD_EN 0x01000000 #define BUS_RD_ABORT_EN 0x02000000 #define BUS_MSTR_WS 0x04000000 #define BUS_PARKING_DIS 0x08000000 #define BUS_MSTR_DISCONNECT_EN 0x10000000 #define BUS_WRT_BURST 0x20000000 #define BUS_READ_BURST 0x40000000 #define BUS_RDY_READ_DLY 0x80000000 /* PIXCLKS_CNTL */ #define PIX2CLK_SRC_SEL_MASK 0x03 #define PIX2CLK_SRC_SEL_CPUCLK 0x00 #define PIX2CLK_SRC_SEL_PSCANCLK 0x01 #define PIX2CLK_SRC_SEL_BYTECLK 0x02 #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 #define PIX2CLK_ALWAYS_ONb (1<<6) #define PIX2CLK_DAC_ALWAYS_ONb (1<<7) #define PIXCLK_TV_SRC_SEL (1 << 8) #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) /* CLOCK_CNTL_INDEX bit constants */ #define PLL_WR_EN 0x00000080 /* CONFIG_CNTL bit constants */ #define CFG_VGA_RAM_EN 0x00000100 #define CFG_ATI_REV_ID_MASK (0xf << 16) #define CFG_ATI_REV_A11 (0 << 16) #define CFG_ATI_REV_A12 (1 << 16) #define CFG_ATI_REV_A13 (2 << 16) /* CRTC_EXT_CNTL bit constants */ #define VGA_ATI_LINEAR 0x00000008 #define VGA_128KAP_PAGING 0x00000010 #define XCRT_CNT_EN (1 << 6) #define CRTC_HSYNC_DIS (1 << 8) #define CRTC_VSYNC_DIS (1 << 9) #define CRTC_DISPLAY_DIS (1 << 10) #define CRTC_CRT_ON (1 << 15) /* DSTCACHE_CTLSTAT bit constants */ #define RB2D_DC_FLUSH (3 << 0) #define RB2D_DC_FREE (3 << 2) #define RB2D_DC_FLUSH_ALL 0xf #define RB2D_DC_BUSY (1 << 31) /* CRTC_GEN_CNTL bit constants */ #define CRTC_DBL_SCAN_EN (1 << 0) #define CRTC_INTERLACE_EN (1 << 1) #define CRTC_CSYNC_EN (1 << 4) #define CRTC_BYPASS_LUT_EN (1 << 14) #define CRTC_CUR_EN (1 << 16) #define CRTC_CUR_MODE_MASK (7 << 17) #define CRTC_ICON_EN (1 << 20) #define CRTC_EXT_DISP_EN (1 << 24) #define CRTC_EN (1 << 25) #define CRTC_DISP_REQ_EN_B (1 << 26) /* CRTC2_GEN_CTRL bit constants */ #define CRTC2_DBL_SCAN_EN (1 << 0) #define CRTC2_INTERLACE_EN (1 << 1) #define CRTC2_SYNC_TRISTAT (1 << 4) #define CRTC2_HSYNC_TRISTAT (1 << 5) #define CRTC2_VSYNC_TRISTAT (1 << 6) #define CRTC2_CRT2_ON (1 << 7) #define CRTC2_ICON_EN (1 << 15) #define CRTC2_CUR_EN (1 << 16) #define CRTC2_CUR_MODE_MASK (7 << 20) #define CRTC2_DISP_DIS (1 << 23) #define CRTC2_EN (1 << 25) #define CRTC2_DISP_REQ_EN_B (1 << 26) #define CRTC2_CSYNC_EN (1 << 27) #define CRTC2_HSYNC_DIS (1 << 28) #define CRTC2_VSYNC_DIS (1 << 29) /* CRTC_STATUS bit constants */ #define CRTC_VBLANK 0x00000001 /* CRTC2_GEN_CNTL bit constants */ #define CRT2_ON (1 << 7) #define CRTC2_DISPLAY_DIS (1 << 23) #define CRTC2_EN (1 << 25) #define CRTC2_DISP_REQ_EN_B (1 << 26) /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ #define CUR_LOCK 0x80000000 /* GPIO bit constants */ #define GPIO_A_0 (1 << 0) #define GPIO_A_1 (1 << 1) #define GPIO_Y_0 (1 << 8) #define GPIO_Y_1 (1 << 9) #define GPIO_EN_0 (1 << 16) #define GPIO_EN_1 (1 << 17) #define GPIO_MASK_0 (1 << 24) #define GPIO_MASK_1 (1 << 25) #define VGA_DDC_DATA_OUTPUT GPIO_A_0 #define VGA_DDC_CLK_OUTPUT GPIO_A_1 #define VGA_DDC_DATA_INPUT GPIO_Y_0 #define VGA_DDC_CLK_INPUT GPIO_Y_1 #define VGA_DDC_DATA_OUT_EN GPIO_EN_0 #define VGA_DDC_CLK_OUT_EN GPIO_EN_1 /* FP bit constants */ #define FP_CRTC_H_TOTAL_MASK 0x000003ff #define FP_CRTC_H_DISP_MASK 0x01ff0000 #define FP_CRTC_V_TOTAL_MASK 0x00000fff #define FP_CRTC_V_DISP_MASK 0x0fff0000 #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 #define FP_H_SYNC_WID_MASK 0x003f0000 #define FP_V_SYNC_STRT_MASK 0x00000fff #define FP_V_SYNC_WID_MASK 0x001f0000 #define FP_CRTC_H_TOTAL_SHIFT 0x00000000 #define FP_CRTC_H_DISP_SHIFT 0x00000010 #define FP_CRTC_V_TOTAL_SHIFT 0x00000000 #define FP_CRTC_V_DISP_SHIFT 0x00000010 #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 #define FP_H_SYNC_WID_SHIFT 0x00000010 #define FP_V_SYNC_STRT_SHIFT 0x00000000 #define FP_V_SYNC_WID_SHIFT 0x00000010 /* FP_GEN_CNTL bit constants */ #define FP_FPON (1 << 0) #define FP_TMDS_EN (1 << 2) #define FP_PANEL_FORMAT (1 << 3) #define FP_EN_TMDS (1 << 7) #define FP_DETECT_SENSE (1 << 8) #define R200_FP_SOURCE_SEL_MASK (3 << 10) #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) #define R200_FP_SOURCE_SEL_RMX (2 << 10) #define R200_FP_SOURCE_SEL_TRANS (3 << 10) #define FP_SEL_CRTC1 (0 << 13) #define FP_SEL_CRTC2 (1 << 13) #define FP_USE_VGA_HSYNC (1 << 14) #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) #define FP_CRTC_DONT_SHADOW_HEND (1 << 17) #define FP_CRTC_USE_SHADOW_VEND (1 << 18) #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) #define FP_DFP_SYNC_SEL (1 << 21) #define FP_CRTC_LOCK_8DOT (1 << 22) #define FP_CRT_SYNC_SEL (1 << 23) #define FP_USE_SHADOW_EN (1 << 24) #define FP_CRT_SYNC_ALT (1 << 26) /* FP2_GEN_CNTL bit constants */ #define FP2_BLANK_EN (1 << 1) #define FP2_ON (1 << 2) #define FP2_PANEL_FORMAT (1 << 3) #define FP2_SOURCE_SEL_MASK (3 << 10) #define FP2_SOURCE_SEL_CRTC2 (1 << 10) #define FP2_SRC_SEL_MASK (3 << 13) #define FP2_SRC_SEL_CRTC2 (1 << 13) #define FP2_FP_POL (1 << 16) #define FP2_LP_POL (1 << 17) #define FP2_SCK_POL (1 << 18) #define FP2_LCD_CNTL_MASK (7 << 19) #define FP2_PAD_FLOP_EN (1 << 22) #define FP2_CRC_EN (1 << 23) #define FP2_CRC_READ_EN (1 << 24) #define FP2_DV0_EN (1 << 25) #define FP2_DV0_RATE_SEL_SDR (1 << 26) /* LVDS_GEN_CNTL bit constants */ #define LVDS_ON (1 << 0) #define LVDS_DISPLAY_DIS (1 << 1) #define LVDS_PANEL_TYPE (1 << 2) #define LVDS_PANEL_FORMAT (1 << 3) #define LVDS_EN (1 << 7) #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 #define LVDS_BL_MOD_LEVEL_SHIFT 8 #define LVDS_BL_MOD_EN (1 << 16) #define LVDS_DIGON (1 << 18) #define LVDS_BLON (1 << 19) #define LVDS_SEL_CRTC2 (1 << 23) #define LVDS_STATE_MASK \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) /* LVDS_PLL_CNTL bit constatns */ #define HSYNC_DELAY_SHIFT 0x1c #define HSYNC_DELAY_MASK (0xf << 0x1c) /* TMDS_TRANSMITTER_CNTL bit constants */ #define TMDS_PLL_EN (1 << 0) #define TMDS_PLLRST (1 << 1) #define TMDS_RAN_PAT_RST (1 << 7) #define TMDS_ICHCSEL (1 << 28) /* FP_HORZ_STRETCH bit constants */ #define HORZ_STRETCH_RATIO_MASK 0xffff #define HORZ_STRETCH_RATIO_MAX 4096 #define HORZ_PANEL_SIZE (0x1ff << 16) #define HORZ_PANEL_SHIFT 16 #define HORZ_STRETCH_PIXREP (0 << 25) #define HORZ_STRETCH_BLEND (1 << 26) #define HORZ_STRETCH_ENABLE (1 << 25) #define HORZ_AUTO_RATIO (1 << 27) #define HORZ_FP_LOOP_STRETCH (0x7 << 28) #define HORZ_AUTO_RATIO_INC (1 << 31) /* FP_VERT_STRETCH bit constants */ #define VERT_STRETCH_RATIO_MASK 0xfff #define VERT_STRETCH_RATIO_MAX 4096 #define VERT_PANEL_SIZE (0xfff << 12) #define VERT_PANEL_SHIFT 12 #define VERT_STRETCH_LINREP (0 << 26) #define VERT_STRETCH_BLEND (1 << 26) #define VERT_STRETCH_ENABLE (1 << 25) #define VERT_AUTO_RATIO_EN (1 << 27) #define VERT_FP_LOOP_STRETCH (0x7 << 28) #define VERT_STRETCH_RESERVED 0xf1000000 /* DAC_CNTL bit constants */ #define DAC_8BIT_EN 0x00000100 #define DAC_4BPP_PIX_ORDER 0x00000200 #define DAC_CRC_EN 0x00080000 #define DAC_MASK_ALL (0xff << 24) #define DAC_PDWN (1 << 15) #define DAC_EXPAND_MODE (1 << 14) #define DAC_VGA_ADR_EN (1 << 13) #define DAC_RANGE_CNTL (3 << 0) #define DAC_RANGE_CNTL_MASK 0x03 #define DAC_BLANKING (1 << 2) #define DAC_CMP_EN (1 << 3) #define DAC_CMP_OUTPUT (1 << 7) /* DAC_CNTL2 bit constants */ #define DAC2_EXPAND_MODE (1 << 14) #define DAC2_CMP_EN (1 << 7) #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) /* DAC_EXT_CNTL bit constants */ #define DAC_FORCE_BLANK_OFF_EN (1 << 4) #define DAC_FORCE_DATA_EN (1 << 5) #define DAC_FORCE_DATA_SEL_MASK (3 << 6) #define DAC_FORCE_DATA_MASK 0x0003ff00 #define DAC_FORCE_DATA_SHIFT 8 /* GEN_RESET_CNTL bit constants */ #define SOFT_RESET_GUI 0x00000001 #define SOFT_RESET_VCLK 0x00000100 #define SOFT_RESET_PCLK 0x00000200 #define SOFT_RESET_ECP 0x00000400 #define SOFT_RESET_DISPENG_XCLK 0x00000800 /* MEM_CNTL bit constants */ #define MEM_CTLR_STATUS_IDLE 0x00000000 #define MEM_CTLR_STATUS_BUSY 0x00100000 #define MEM_SEQNCR_STATUS_IDLE 0x00000000 #define MEM_SEQNCR_STATUS_BUSY 0x00200000 #define MEM_ARBITER_STATUS_IDLE 0x00000000 #define MEM_ARBITER_STATUS_BUSY 0x00400000 #define MEM_REQ_UNLOCK 0x00000000 #define MEM_REQ_LOCK 0x00800000 #define MEM_NUM_CHANNELS_MASK 0x00000001 #define MEM_USE_B_CH_ONLY 0x00000002 #define RV100_MEM_HALF_MODE 0x00000008 #define R300_MEM_NUM_CHANNELS_MASK 0x00000003 #define R300_MEM_USE_CD_CH_ONLY 0x00000004 /* RBBM_GUICNTL bit connstants */ #define HOST_DATA_SWAP_NONE (0 << 0) #define HOST_DATA_SWAP_16BIT (1 << 0) #define HOST_DATA_SWAP_32BIT (2 << 0) #define HOST_DATA_SWAP_HDW (3 << 0) /* RBBM_SOFT_RESET bit constants */ #define SOFT_RESET_CP (1 << 0) #define SOFT_RESET_HI (1 << 1) #define SOFT_RESET_SE (1 << 2) #define SOFT_RESET_RE (1 << 3) #define SOFT_RESET_PP (1 << 4) #define SOFT_RESET_E2 (1 << 5) #define SOFT_RESET_RB (1 << 6) #define SOFT_RESET_HDP (1 << 7) /* RBBM_STATUS bit constants */ #define RBBM_FIFOCNT_MASK 0x007f #define RBBM_ACTIVE (1 << 31) /* SURFACE_CNTL bit constants */ #define SURF_TRANSLATION_DIS (1 << 8) #define NONSURF_AP0_SWP_16BPP (1 << 20) #define NONSURF_AP0_SWP_32BPP (1 << 21) #define NONSURF_AP1_SWP_16BPP (1 << 22) #define NONSURF_AP1_SWP_32BPP (1 << 23) /* SURFACE_INFO bit constants */ #define SURF_TILE_COLOR_MACRO (0 << 16) #define SURF_TILE_COLOR_BOTH (1 << 16) #define SURF_TILE_DEPTH_32BPP (2 << 16) #define SURF_TILE_DEPTH_16BPP (3 << 16) #define R200_SURF_TILE_NONE (0 << 16) #define R200_SURF_TILE_COLOR_MACRO (1 << 16) #define R200_SURF_TILE_COLOR_MICRO (2 << 16) #define R200_SURF_TILE_COLOR_BOTH (3 << 16) #define R200_SURF_TILE_DEPTH_32BPP (4 << 16) #define R200_SURF_TILE_DEPTH_16BPP (5 << 16) #define R300_SURF_TILE_NONE (0 << 16) #define R300_SURF_TILE_COLOR_MACRO (1 << 16) #define R300_SURF_TILE_DEPTH_32BPP (2 << 16) #define SURF_AP0_SWP_16BPP (1 << 20) #define SURF_AP0_SWP_32BPP (1 << 21) #define SURF_AP1_SWP_16BPP (1 << 22) #define SURF_AP1_SWP_32BPP (1 << 23) /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) /* MM_INDEX bit constants */ #define MM_APER 0x80000000 /* CLR_CMP_CNTL bit constants */ #define COMPARE_SRC_FALSE 0x00000000 #define COMPARE_SRC_TRUE 0x00000001 #define COMPARE_SRC_NOT_EQUAL 0x00000004 #define COMPARE_SRC_EQUAL 0x00000005 #define COMPARE_SRC_EQUAL_FLIP 0x00000007 #define COMPARE_DST_FALSE 0x00000000 #define COMPARE_DST_TRUE 0x00000100 #define COMPARE_DST_NOT_EQUAL 0x00000400 #define COMPARE_DST_EQUAL 0x00000500 #define COMPARE_DESTINATION 0x00000000 #define COMPARE_SOURCE 0x01000000 #define COMPARE_SRC_AND_DST 0x02000000 /* CMP_CNTL bit constants */ #define SRC_CMP_EQ_COLOR (4 << 0) #define SRC_CMP_NEQ_COLOR (5 << 0) #define CLR_CMP_SRC_SOURCE (1 << 24) /* DP_CNTL bit constants */ #define DST_X_RIGHT_TO_LEFT 0x00000000 #define DST_X_LEFT_TO_RIGHT 0x00000001 #define DST_Y_BOTTOM_TO_TOP 0x00000000 #define DST_Y_TOP_TO_BOTTOM 0x00000002 #define DST_X_MAJOR 0x00000000 #define DST_Y_MAJOR 0x00000004 #define DST_X_TILE 0x00000008 #define DST_Y_TILE 0x00000010 #define DST_LAST_PEL 0x00000020 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 #define DST_BRES_SIGN 0x00000100 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 #define DST_POLYLINE_NONLAST 0x00008000 #define DST_RASTER_STALL 0x00010000 #define DST_POLY_EDGE 0x00040000 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ #define DST_X_MAJOR_S 0x00000000 #define DST_Y_MAJOR_S 0x00000001 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 #define DST_X_RIGHT_TO_LEFT_S 0x00000000 #define DST_X_LEFT_TO_RIGHT_S 0x80000000 /* SC_TOP_LEFT_C bit contsants */ #define SC_SIGN_MASK_LO 0x8000 #define SC_SIGN_MASK_HI 0x80000000 /* DST_LINE_PATCOUNT bit constants */ #define BRES_CNTL_SHIFT 8 /* DP_DATATYPE bit constants */ #define DST_8BPP 0x00000002 #define DST_15BPP 0x00000003 #define DST_16BPP 0x00000004 #define DST_24BPP 0x00000005 #define DST_32BPP 0x00000006 #define DST_8BPP_RGB332 0x00000007 #define DST_8BPP_Y8 0x00000008 #define DST_8BPP_RGB8 0x00000009 #define DST_16BPP_VYUY422 0x0000000b #define DST_16BPP_YVYU422 0x0000000c #define DST_32BPP_AYUV444 0x0000000e #define DST_16BPP_ARGB4444 0x0000000f #define BRUSH_SOLIDCOLOR 0x00000d00 #define SRC_MONO 0x00000000 #define SRC_MONO_LBKGD 0x00010000 #define SRC_DSTCOLOR 0x00030000 #define BYTE_ORDER_MSB_TO_LSB 0x00000000 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 #define DP_CONVERSION_TEMP 0x80000000 #define HOST_BIG_ENDIAN_EN (1 << 29) /* DP_GUI_MASTER_CNTL bit constants */ #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_SRC_CLIP_LEAVE 0x00000004 #define GMC_DST_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_LEAVE 0x00000008 #define GMC_BRUSH_8x8MONO 0x00000000 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 #define GMC_BRUSH_8x1MONO 0x00000020 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 #define GMC_BRUSH_1x8MONO 0x00000040 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 #define GMC_BRUSH_32x1MONO 0x00000060 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 #define GMC_BRUSH_32x32MONO 0x00000080 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 #define GMC_BRUSH_8x8COLOR 0x000000a0 #define GMC_BRUSH_8x1COLOR 0x000000b0 #define GMC_BRUSH_1x8COLOR 0x000000c0 #define GMC_DST_8BPP 0x00000200 #define GMC_DST_8BPP_RGB332 0x00000700 #define GMC_DST_8BPP_Y8 0x00000800 #define GMC_DST_8BPP_RGB8 0x00000900 #define GMC_DST_16BPP_VYUY422 0x00000b00 #define GMC_DST_16BPP_YVYU422 0x00000c00 #define GMC_DST_32BPP_AYUV444 0x00000e00 #define GMC_DST_16BPP_ARGB4444 0x00000f00 #define GMC_SRC_MONO 0x00000000 #define GMC_SRC_MONO_LBKGD 0x00001000 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 #define GMC_DP_SRC_RECT 0x02000000 #define GMC_DP_SRC_HOST 0x03000000 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 #define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_3D_FCN_EN_SET 0x08000000 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 #define GMC_AUX_CLIP_LEAVE 0x00000000 #define GMC_AUX_CLIP_CLEAR 0x20000000 #define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define DP_SRC_SOURCE_MASK (7 << 24) #define GMC_BRUSH_NONE (15 << 4) #define DP_SRC_SOURCE_MEMORY (2 << 24) #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) #define GMC_DST_PITCH_OFFSET_CNTL (1 << 1) #define GMC_SRC_CLIPPING (1 << 2) #define GMC_DST_CLIPPING (1 << 3) #define GMC_BRUSH_DATATYPE_MASK (0x0f << 4) #define GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) #define GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) #define GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) #define GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) #define GMC_BRUSH_32X1_MONO_FG_BG (6 << 4) #define GMC_BRUSH_32X1_MONO_FG_LA (7 << 4) #define GMC_BRUSH_32X32_MONO_FG_BG (8 << 4) #define GMC_BRUSH_32X32_MONO_FG_LA (9 << 4) #define GMC_BRUSH_8X8_COLOR (10 << 4) #define GMC_BRUSH_1X8_COLOR (12 << 4) #define GMC_BRUSH_SOLID_COLOR (13 << 4) #define GMC_BRUSH_NONE (15 << 4) #define GMC_DST_8BPP_CI (2 << 8) #define GMC_DST_15BPP (3 << 8) #define GMC_DST_16BPP (4 << 8) #define GMC_DST_24BPP (5 << 8) #define GMC_DST_32BPP (6 << 8) #define GMC_DST_8BPP_RGB (7 << 8) #define GMC_DST_Y8 (8 << 8) #define GMC_DST_RGB8 (9 << 8) #define GMC_DST_VYUY (11 << 8) #define GMC_DST_YVYU (12 << 8) #define GMC_DST_AYUV444 (14 << 8) #define GMC_DST_ARGB4444 (15 << 8) #define GMC_DST_DATATYPE_MASK (0x0f << 8) #define GMC_DST_DATATYPE_SHIFT 8 #define GMC_SRC_DATATYPE_MASK (3 << 12) #define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) #define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define GMC_BYTE_PIX_ORDER (1 << 14) #define GMC_BYTE_MSB_TO_LSB (0 << 14) #define GMC_BYTE_LSB_TO_MSB (1 << 14) #define GMC_CONVERSION_TEMP (1 << 15) #define GMC_CONVERSION_TEMP_6500 (0 << 15) #define GMC_CONVERSION_TEMP_9300 (1 << 15) #define GMC_ROP3_MASK (0xff << 16) #define DP_SRC_SOURCE_MASK (7 << 24) #define DP_SRC_SOURCE_MEMORY (2 << 24) #define DP_SRC_SOURCE_HOST_DATA (3 << 24) #define GMC_3D_FCN_EN (1 << 27) #define GMC_CLR_CMP_CNTL_DIS (1 << 28) #define GMC_AUX_CLIP_DIS (1 << 29) #define GMC_WR_MSK_DIS (1 << 30) #define GMC_LD_BRUSH_Y_X (1 << 31) #define ROP3_ZERO 0x00000000 #define ROP3_DSa 0x00880000 #define ROP3_SDna 0x00440000 #define ROP3_S 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000 #define ROP3_DSna 0x00220000 #define ROP3_D 0x00aa0000 #define ROP3_DSx 0x00660000 #define ROP3_DSo 0x00ee0000 #define ROP3_DSon 0x00110000 #define ROP3_DSxn 0x00990000 #define ROP3_Dn 0x00550000 #define ROP3_SDno 0x00dd0000 #define ROP3_Sn 0x00330000 #define ROP3_DSno 0x00bb0000 #define ROP3_DSan 0x00770000 #define ROP3_ONE 0x00ff0000 #define ROP3_DPa 0x00a00000 #define ROP3_PDna 0x00500000 #define ROP3_P 0x00f00000 #define ROP3_PATCOPY 0x00f00000 #define ROP3_DPna 0x000a0000 #define ROP3_D 0x00aa0000 #define ROP3_DPx 0x005a0000 #define ROP3_DPo 0x00fa0000 #define ROP3_DPon 0x00050000 #define ROP3_PDxn 0x00a50000 #define ROP3_PDno 0x00f50000 #define ROP3_Pn 0x000f0000 #define ROP3_DPno 0x00af0000 #define ROP3_DPan 0x005f0000 /* DP_MIX bit constants */ #define DP_SRC_RECT 0x00000200 #define DP_SRC_HOST 0x00000300 #define DP_SRC_HOST_BYTEALIGN 0x00000400 /* MPLL_CNTL bit constants */ #define MPLL_RESET 0x00000001 /* MDLL_CKO bit constants */ #define MCKOA_SLEEP 0x00000001 #define MCKOA_RESET 0x00000002 #define MCKOA_REF_SKEW_MASK 0x00000700 #define MCKOA_FB_SKEW_MASK 0x00007000 /* MDLL_RDCKA bit constants */ #define MRDCKA0_SLEEP 0x00000001 #define MRDCKA0_RESET 0x00000002 #define MRDCKA1_SLEEP 0x00010000 #define MRDCKA1_RESET 0x00020000 /* VCLK_ECP_CNTL constants */ #define VCLK_SRC_SEL_MASK 0x03 #define VCLK_SRC_SEL_CPUCLK 0x00 #define VCLK_SRC_SEL_PSCANCLK 0x01 #define VCLK_SRC_SEL_BYTECLK 0x02 #define VCLK_SRC_SEL_PPLLCLK 0x03 #define PIXCLK_ALWAYS_ONb 0x00000040 #define PIXCLK_DAC_ALWAYS_ONb 0x00000080 /* BUS_CNTL1 constants */ #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 #define BUS_CNTL1_AGPCLK_VALID 0x80000000 /* PLL_PWRMGT_CNTL constants */ #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 /* TV_DAC_CNTL constants */ #define TV_DAC_CNTL_BGSLEEP 0x00000040 #define TV_DAC_CNTL_DETECT 0x00000010 #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 #define TV_DAC_CNTL_BGADJ__SHIFT 16 #define TV_DAC_CNTL_DACADJ__SHIFT 20 #define TV_DAC_CNTL_RDACPD 0x01000000 #define TV_DAC_CNTL_GDACPD 0x02000000 #define TV_DAC_CNTL_BDACPD 0x04000000 /* DISP_MISC_CNTL constants */ #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) /* DISP_PWR_MAN constants */ #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) #define DISP_PWR_MAN_DISP_D3_RST (1 << 16) #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) /* DST_PITCH_OFFSET bit constants */ #define PITCH_SHIFT 21 #define DST_TILE_LINEAR (0 << 30) #define DST_TILE_MACRO (1 << 30) #define DST_TILE_MICRO (2 << 30) #define DST_TILE_BOTH (3 << 30) /* masks */ #define CONFIG_MEMSIZE_MASK 0x1f000000 #define MEM_CFG_TYPE 0x40000000 #define DST_OFFSET_MASK 0x003fffff #define DST_PITCH_MASK 0x3fc00000 #define DEFAULT_TILE_MASK 0xc0000000 #define PPLL_DIV_SEL_MASK 0x00000300 #define PPLL_RESET 0x00000001 #define PPLL_SLEEP 0x00000002 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 #define PPLL_REF_DIV_MASK 0x000003ff #define PPLL_FB3_DIV_MASK 0x000007ff #define PPLL_POST3_DIV_MASK 0x00070000 #define PPLL_ATOMIC_UPDATE_R 0x00008000 #define PPLL_ATOMIC_UPDATE_W 0x00008000 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) #define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define GUI_ACTIVE 0x80000000 #define MC_IND_INDEX 0x01F8 #define MC_IND_DATA 0x01FC /* PAD_CTLR_STRENGTH */ #define PAD_MANUAL_OVERRIDE 0x80000000 /* pllCLK_PIN_CNTL */ #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L #define CLK_PIN_CNTL__OSC_EN 0x00000001L #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L #define CLK_PIN_CNTL__CG_SPARE 0x00004000L #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L /* pllCLK_PWRMGT_CNTL */ #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f /* pllP2PLL_CNTL */ #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L #define P2PLL_CNTL__P2PLL_RESET 0x00000001L #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L /* pllPIXCLKS_CNTL */ #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f /* pllPIXCLKS_CNTL */ #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) /* pllP2PLL_DIV_0 */ #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L /* pllSCLK_CNTL */ #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 #define SCLK_CNTL__FORCE_DISP2 0x00008000L #define SCLK_CNTL__FORCE_CP 0x00010000L #define SCLK_CNTL__FORCE_HDP 0x00020000L #define SCLK_CNTL__FORCE_DISP1 0x00040000L #define SCLK_CNTL__FORCE_TOP 0x00080000L #define SCLK_CNTL__FORCE_E2 0x00100000L #define SCLK_CNTL__FORCE_SE 0x00200000L #define SCLK_CNTL__FORCE_IDCT 0x00400000L #define SCLK_CNTL__FORCE_VIP 0x00800000L #define SCLK_CNTL__FORCE_RE 0x01000000L #define SCLK_CNTL__FORCE_PB 0x02000000L #define SCLK_CNTL__FORCE_TAM 0x04000000L #define SCLK_CNTL__FORCE_TDM 0x08000000L #define SCLK_CNTL__FORCE_RB 0x10000000L #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L #define SCLK_CNTL__FORCE_OV0 0x80000000L #define SCLK_CNTL__R300_FORCE_VAP (1<<21) #define SCLK_CNTL__R300_FORCE_SR (1<<25) #define SCLK_CNTL__R300_FORCE_PX (1<<26) #define SCLK_CNTL__R300_FORCE_TX (1<<27) #define SCLK_CNTL__R300_FORCE_US (1<<28) #define SCLK_CNTL__R300_FORCE_SU (1<<30) #define SCLK_CNTL__FORCEON_MASK 0xffff8000L /* pllSCLK_CNTL2 */ #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) #define SCLK_CNTL2__R300_FORCE_TCL (1<<13) #define SCLK_CNTL2__R300_FORCE_CBA (1<<14) #define SCLK_CNTL2__R300_FORCE_GA (1<<15) /* SCLK_MORE_CNTL */ #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L #define SCLK_MORE_CNTL__FORCEON 0x00000700L /* MCLK_CNTL */ #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L #define MCLK_CNTL__FORCE_MCLKA 0x00010000L #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L #define MCLK_CNTL__FORCE_MCLKB 0x00020000L #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L #define MCLK_CNTL__FORCE_YCLKA 0x00040000L #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L #define MCLK_CNTL__FORCE_YCLKB 0x00080000L #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L #define MCLK_CNTL__FORCE_MC 0x00100000L #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L #define MCLK_CNTL__FORCE_AIC 0x00200000L #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) /* MCLK_MISC */ #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L #define MCLK_MISC__DLL_READY_LAT 0x00000100L #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L /* VCLK_ECP_CNTL */ #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) /* PLL_PWRMGT_CNTL */ #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L /* CLK_PWRMGT_CNTL */ #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L /* BUS_CNTL1 */ #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L #define BUS_CNTL1__AGPCLK_VALID 0x80000000L /* BUS_CNTL1 */ #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f /* CRTC_OFFSET_CNTL */ #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L #define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) #define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) #define R300_CRTC_X_Y_MODE_EN (1 << 9) #define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) #define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) #define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) #define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) #define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) #define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) #define R300_CRTC_MICRO_TILE_EN (1 << 13) #define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) #define R300_CRTC_MACRO_TILE_EN (1 << 15) /* CRTC_GEN_CNTL */ #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L /* CRTC2_GEN_CNTL */ #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L /* AGP_CNTL */ #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L #define AGP_CNTL__EN_2X_STBB 0x00000400L #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L #define AGP_CNTL__SBA_DIS_MASK 0x00001000L #define AGP_CNTL__SBA_DIS 0x00001000L #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L #define AGP_CNTL__AGP_REV_ID 0x00002000L #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L #define AGP_CNTL__FORCE_INT_VREF 0x00010000L #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L #define AGP_CNTL__EN_RBFCALM 0x00800000L #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L #define AGP_CNTL__DIS_RBF_MASK 0x02000000L #define AGP_CNTL__DIS_RBF 0x02000000L #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L /* AGP_CNTL */ #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e /* DISP_MISC_CNTL */ #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L /* DISP_PWR_MAN */ #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L /* MC_IND_INDEX */ #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L /* MC_IND_DATA */ #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL /* MC_CHP_IO_CNTL_A1 */ #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f /* MC_CHP_IO_CNTL_B1 */ #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f /* MC_CHP_IO_CNTL_A1 */ #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L /* MC_CHP_IO_CNTL_B1 */ #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L /* MEM_SDRAM_MODE_REG */ #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L /* MEM_SDRAM_MODE_REG */ #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f /* MEM_REFRESH_CNTL */ #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L /* MC_STATUS */ #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L #define MC_STATUS__MC_IDLE_MASK 0x00000004L #define MC_STATUS__MC_IDLE 0x00000004L #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L /* MDLL_CKO */ #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L #define MDLL_CKO__MCKOA_SLEEP 0x00000001L #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L #define MDLL_CKO__MCKOA_RESET 0x00000002L #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L #define MDLL_CKO__MCKOB_SLEEP 0x00010000L #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L #define MDLL_CKO__MCKOB_RESET 0x00020000L #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L /* MDLL_RDCKA */ #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L /* MDLL_RDCKB */ #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L #define pllCLK_PIN_CNTL 0x0001 #define pllPPLL_CNTL 0x0002 #define pllPPLL_REF_DIV 0x0003 #define pllPPLL_DIV_0 0x0004 #define pllPPLL_DIV_1 0x0005 #define pllPPLL_DIV_2 0x0006 #define pllPPLL_DIV_3 0x0007 #define pllVCLK_ECP_CNTL 0x0008 #define pllHTOTAL_CNTL 0x0009 #define pllM_SPLL_REF_FB_DIV 0x000A #define pllAGP_PLL_CNTL 0x000B #define pllSPLL_CNTL 0x000C #define pllSCLK_CNTL 0x000D #define pllMPLL_CNTL 0x000E #define pllMDLL_CKO 0x000F #define pllMDLL_RDCKA 0x0010 #define pllMDLL_RDCKB 0x0011 #define pllMCLK_CNTL 0x0012 #define pllPLL_TEST_CNTL 0x0013 #define pllCLK_PWRMGT_CNTL 0x0014 #define pllPLL_PWRMGT_CNTL 0x0015 #define pllCG_TEST_MACRO_RW_WRITE 0x0016 #define pllCG_TEST_MACRO_RW_READ 0x0017 #define pllCG_TEST_MACRO_RW_DATA 0x0018 #define pllCG_TEST_MACRO_RW_CNTL 0x0019 #define pllDISP_TEST_MACRO_RW_WRITE 0x001A #define pllDISP_TEST_MACRO_RW_READ 0x001B #define pllDISP_TEST_MACRO_RW_DATA 0x001C #define pllDISP_TEST_MACRO_RW_CNTL 0x001D #define pllSCLK_CNTL2 0x001E #define pllMCLK_MISC 0x001F #define pllTV_PLL_FINE_CNTL 0x0020 #define pllTV_PLL_CNTL 0x0021 #define pllTV_PLL_CNTL1 0x0022 #define pllTV_DTO_INCREMENTS 0x0023 #define pllSPLL_AUX_CNTL 0x0024 #define pllMPLL_AUX_CNTL 0x0025 #define pllP2PLL_CNTL 0x002A #define pllP2PLL_REF_DIV 0x002B #define pllP2PLL_DIV_0 0x002C #define pllPIXCLKS_CNTL 0x002D #define pllHTOTAL2_CNTL 0x002E #define pllSSPLL_CNTL 0x0030 #define pllSSPLL_REF_DIV 0x0031 #define pllSSPLL_DIV_0 0x0032 #define pllSS_INT_CNTL 0x0033 #define pllSS_TST_CNTL 0x0034 #define pllSCLK_MORE_CNTL 0x0035 #define ixMC_PERF_CNTL 0x0000 #define ixMC_PERF_SEL 0x0001 #define ixMC_PERF_REGION_0 0x0002 #define ixMC_PERF_REGION_1 0x0003 #define ixMC_PERF_COUNT_0 0x0004 #define ixMC_PERF_COUNT_1 0x0005 #define ixMC_PERF_COUNT_2 0x0006 #define ixMC_PERF_COUNT_3 0x0007 #define ixMC_PERF_COUNT_MEMCH_A 0x0008 #define ixMC_PERF_COUNT_MEMCH_B 0x0009 #define ixMC_IMP_CNTL 0x000A #define ixMC_CHP_IO_CNTL_A0 0x000B #define ixMC_CHP_IO_CNTL_A1 0x000C #define ixMC_CHP_IO_CNTL_B0 0x000D #define ixMC_CHP_IO_CNTL_B1 0x000E #define ixMC_IMP_CNTL_0 0x000F #define ixTC_MISMATCH_1 0x0010 #define ixTC_MISMATCH_2 0x0011 #define ixMC_BIST_CTRL 0x0012 #define ixREG_COLLAR_WRITE 0x0013 #define ixREG_COLLAR_READ 0x0014 #define ixR300_MC_IMP_CNTL 0x0018 #define ixR300_MC_CHP_IO_CNTL_A0 0x0019 #define ixR300_MC_CHP_IO_CNTL_A1 0x001a #define ixR300_MC_CHP_IO_CNTL_B0 0x001b #define ixR300_MC_CHP_IO_CNTL_B1 0x001c #define ixR300_MC_CHP_IO_CNTL_C0 0x001d #define ixR300_MC_CHP_IO_CNTL_C1 0x001e #define ixR300_MC_CHP_IO_CNTL_D0 0x001f #define ixR300_MC_CHP_IO_CNTL_D1 0x0020 #define ixR300_MC_IMP_CNTL_0 0x0021 #define ixR300_MC_ELPIDA_CNTL 0x0022 #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 #define ixR300_MC_READ_CNTL_CD 0x0024 #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 #define ixR300_MC_DEBUG_CNTL 0x0026 #define ixR300_MC_BIST_CNTL_0 0x0028 #define ixR300_MC_BIST_CNTL_1 0x0029 #define ixR300_MC_BIST_CNTL_2 0x002a #define ixR300_MC_BIST_CNTL_3 0x002b #define ixR300_MC_BIST_CNTL_4 0x002c #define ixR300_MC_BIST_CNTL_5 0x002d #define ixR300_MC_IMP_STATUS 0x002e #define ixR300_MC_DLL_CNTL 0x002f #define NB_TOM 0x15C /****************** for VIDIX **************************/ /* BUS_CNTL bit constants */ #define BUS_DBL_RESYNC 0x00000001 #define BUS_MSTR_RESET 0x00000002 #define BUS_FLUSH_BUF 0x00000004 #define BUS_STOP_REQ_DIS 0x00000008 #define BUS_ROTATION_DIS 0x00000010 #define BUS_MASTER_DIS 0x00000040 #define BUS_ROM_WRT_EN 0x00000080 #define BUS_DIS_ROM 0x00001000 #define BUS_PCI_READ_RETRY_EN 0x00002000 #define BUS_AGP_AD_STEPPING_EN 0x00004000 #define BUS_PCI_WRT_RETRY_EN 0x00008000 #define BUS_MSTR_RD_MULT 0x00100000 #define BUS_MSTR_RD_LINE 0x00200000 #define BUS_SUSPEND 0x00400000 #define LAT_16X 0x00800000 #define BUS_RD_DISCARD_EN 0x01000000 #define BUS_RD_ABORT_EN 0x02000000 #define BUS_MSTR_WS 0x04000000 #define BUS_PARKING_DIS 0x08000000 #define BUS_MSTR_DISCONNECT_EN 0x10000000 #define BUS_WRT_BURST 0x20000000 #define BUS_READ_BURST 0x40000000 #define BUS_RDY_READ_DLY 0x80000000 #define HI_STAT 0x004C #define BUS_CNTL1 0x0034 #define BUS_WAIT_ON_LOCK_EN (1 << 4) #define I2C_CNTL_0 0x0090 #define I2C_DONE (1<<0) #define I2C_NACK (1<<1) #define I2C_HALT (1<<2) #define I2C_SOFT_RST (1<<5) #define I2C_DRIVE_EN (1<<6) #define I2C_DRIVE_SEL (1<<7) #define I2C_START (1<<8) #define I2C_STOP (1<<9) #define I2C_RECEIVE (1<<10) #define I2C_ABORT (1<<11) #define I2C_GO (1<<12) #define I2C_SEL (1<<16) #define I2C_EN (1<<17) #define I2C_CNTL_1 0x0094 #define I2C_DATA 0x0098 #define CONFIG_CNTL 0x00E0 /* CONFIG_CNTL bit constants */ #define CFG_VGA_RAM_EN 0x00000100 #define CONFIG_MEMSIZE 0x00F8 #define CONFIG_APER_0_BASE 0x0100 #define CONFIG_APER_1_BASE 0x0104 #define CONFIG_APER_SIZE 0x0108 #define CONFIG_REG_1_BASE 0x010C #define CONFIG_REG_APER_SIZE 0x0110 #define PAD_AGPINPUT_DELAY 0x0164 #define PAD_CTLR_STRENGTH 0x0168 #define PAD_CTLR_UPDATE 0x016C #define AGP_CNTL 0x0174 #define AGP_APER_SIZE_256MB (0x00 << 0) #define AGP_APER_SIZE_128MB (0x20 << 0) #define AGP_APER_SIZE_64MB (0x30 << 0) #define AGP_APER_SIZE_32MB (0x38 << 0) #define AGP_APER_SIZE_16MB (0x3c << 0) #define AGP_APER_SIZE_8MB (0x3e << 0) #define AGP_APER_SIZE_4MB (0x3f << 0) #define AGP_APER_SIZE_MASK (0x3f << 0) #define AMCGPIO_A_REG 0x01a0 #define AMCGPIO_EN_REG 0x01a8 #define AMCGPIO_MASK 0x0194 #define AMCGPIO_Y_REG 0x01a4 #define MPP_TB_CONFIG 0x01c0 /* ? */ #define MPP_GP_CONFIG 0x01c8 /* ? */ #define VENDOR_ID 0x0F00 #define DEVICE_ID 0x0F02 #define COMMAND 0x0F04 #define STATUS 0x0F06 #define REVISION_ID 0x0F08 #define REGPROG_INF 0x0F09 #define SUB_CLASS 0x0F0A #define CACHE_LINE 0x0F0C #define LATENCY 0x0F0D #define HEADER 0x0F0E #define BIST 0x0F0F #define REG_MEM_BASE 0x0F10 #define REG_IO_BASE 0x0F14 #define REG_REG_BASE 0x0F18 #define ADAPTER_ID 0x0F2C #define BIOS_ROM 0x0F30 #define CAPABILITIES_PTR 0x0F34 #define INTERRUPT_LINE 0x0F3C #define INTERRUPT_PIN 0x0F3D #define MIN_GRANT 0x0F3E #define MAX_LATENCY 0x0F3F #define ADAPTER_ID_W 0x0F4C #define PMI_CAP_ID 0x0F50 #define PMI_NXT_CAP_PTR 0x0F51 #define PMI_PMC_REG 0x0F52 #define PM_STATUS 0x0F54 #define PMI_DATA 0x0F57 #define AGP_CAP_ID 0x0F58 #define AGP_STATUS 0x0F5C #define AGP_1X_MODE 0x01 #define AGP_2X_MODE 0x02 #define AGP_4X_MODE 0x04 #define AGP_MODE_MASK 0x07 #define AGP_COMMAND 0x0F60 /* Video muxer unit */ #define VIDEOMUX_CNTL 0x0190 #define VIPPAD_MASK 0x0198 #define VIPPAD1_A 0x01AC #define VIPPAD1_EN 0x01B0 #define VIPPAD1_Y 0x01B4 #define AIC_CTRL 0x01D0 #define AIC_STAT 0x01D4 #define AIC_PT_BASE 0x01D8 #define AIC_LO_ADDR 0x01DC #define AIC_HI_ADDR 0x01E0 #define AIC_TLB_ADDR 0x01E4 #define AIC_TLB_DATA 0x01E8 #define DAC_CNTL 0x0058 /* DAC_CNTL bit constants */ #define DAC_8BIT_EN 0x00000100 #define DAC_4BPP_PIX_ORDER 0x00000200 #define DAC_CRC_EN 0x00080000 #define DAC_MASK_ALL (0xff << 24) #define DAC_VGA_ADR_EN (1 << 13) #define DAC_RANGE_CNTL (3 << 0) #define DAC_BLANKING (1 << 2) #define DAC_CNTL2 0x007c /* DAC_CNTL2 bit constants */ #define DAC2_DAC_CLK_SEL (1 << 0) #define DAC2_DAC2_CLK_SEL (1 << 1) #define DAC2_PALETTE_ACC_CTL (1 << 5) #define TV_DAC_CNTL 0x088c /* TV_DAC_CNTL bit constants */ #define TV_DAC_STD_MASK 0x0300 #define TV_DAC_RDACPD (1 << 24) #define TV_DAC_GDACPD (1 << 25) #define TV_DAC_BDACPD (1 << 26) #define CRTC_GEN_CNTL 0x0050 /* CRTC_GEN_CNTL bit constants */ //#define CRTC_DBL_SCAN_EN 0x00000001 #define CRTC_INTERLACE_EN (1 << 1) #define CRTC_CSYNC_EN (1 << 4) //#define CRTC_CUR_EN 0x00010000 #define CRTC_CUR_MODE_MASK (7 << 17) #define CRTC_ICON_EN (1 << 20) #define CRTC_EXT_DISP_EN (1 << 24) #define CRTC_EN (1 << 25) #define CRTC_DISP_REQ_EN_B (1 << 26) #define CRTC2_GEN_CNTL 0x03f8 /* CRTC2_GEN_CNTL bit constants */ #define CRTC2_DBL_SCAN_EN (1 << 0) #define CRTC2_INTERLACE_EN (1 << 1) #define CRTC2_SYNC_TRISTAT (1 << 4) #define CRTC2_HSYNC_TRISTAT (1 << 5) #define CRTC2_VSYNC_TRISTAT (1 << 6) #define CRTC2_CRT2_ON (1 << 7) #define CRTC2_ICON_EN (1 << 15) #define CRTC2_CUR_EN (1 << 16) #define CRTC2_CUR_MODE_MASK (7 << 20) #define CRTC2_DISP_DIS (1 << 23) #define CRTC2_EN (1 << 25) #define CRTC2_DISP_REQ_EN_B (1 << 26) #define CRTC2_HSYNC_DIS (1 << 28) #define CRTC2_VSYNC_DIS (1 << 29) #define MEM_CNTL 0x0140 /* MEM_CNTL bit constants */ #define MEM_CTLR_STATUS_IDLE 0x00000000 #define MEM_CTLR_STATUS_BUSY 0x00100000 #define MEM_SEQNCR_STATUS_IDLE 0x00000000 #define MEM_SEQNCR_STATUS_BUSY 0x00200000 #define MEM_ARBITER_STATUS_IDLE 0x00000000 #define MEM_ARBITER_STATUS_BUSY 0x00400000 #define MEM_REQ_UNLOCK 0x00000000 #define MEM_REQ_LOCK 0x00800000 #define EXT_MEM_CNTL 0x0144 #define MC_AGP_LOCATION 0x014C #define MEM_IO_CNTL_A0 0x0178 #define MEM_INIT_LATENCY_TIMER 0x0154 #define MEM_SDRAM_MODE_REG 0x0158 #define AGP_BASE 0x0170 #define MEM_IO_CNTL_A1 0x017C #define MEM_IO_CNTL_B0 0x0180 #define MEM_IO_CNTL_B1 0x0184 #define MC_DEBUG 0x0188 #define MC_STATUS 0x0150 #define MEM_IO_OE_CNTL 0x018C #define MC_FB_LOCATION 0x0148 #define HOST_PATH_CNTL 0x0130 #define MEM_VGA_WP_SEL 0x0038 #define MEM_VGA_RP_SEL 0x003C #define HDP_DEBUG 0x0138 #define SW_SEMAPHORE 0x013C #define SURFACE_CNTL 0x0B00 /* SURFACE_CNTL bit constants */ # define SURF_TRANSLATION_DIS (1 << 8) #define SURFACE0_LOWER_BOUND 0x0B04 #define SURFACE1_LOWER_BOUND 0x0B14 #define SURFACE2_LOWER_BOUND 0x0B24 #define SURFACE3_LOWER_BOUND 0x0B34 #define SURFACE4_LOWER_BOUND 0x0B44 #define SURFACE5_LOWER_BOUND 0x0B54 #define SURFACE6_LOWER_BOUND 0x0B64 #define SURFACE7_LOWER_BOUND 0x0B74 #define SURFACE0_UPPER_BOUND 0x0B08 #define SURFACE1_UPPER_BOUND 0x0B18 #define SURFACE2_UPPER_BOUND 0x0B28 #define SURFACE3_UPPER_BOUND 0x0B38 #define SURFACE4_UPPER_BOUND 0x0B48 #define SURFACE5_UPPER_BOUND 0x0B58 #define SURFACE6_UPPER_BOUND 0x0B68 #define SURFACE7_UPPER_BOUND 0x0B78 #define SURFACE0_INFO 0x0B0C #define SURFACE1_INFO 0x0B1C #define SURFACE2_INFO 0x0B2C #define SURFACE3_INFO 0x0B3C #define SURFACE4_INFO 0x0B4C #define SURFACE5_INFO 0x0B5C #define SURFACE6_INFO 0x0B6C #define SURFACE7_INFO 0x0B7C #define SURFACE_ACCESS_FLAGS 0x0BF8 #define SURFACE_ACCESS_CLR 0x0BFC #define GEN_INT_CNTL 0x0040 #define GEN_INT_STATUS 0x0044 #define VSYNC_INT_AK (1 << 2) #define VSYNC_INT (1 << 2) #define CRTC_EXT_CNTL 0x0054 /* CRTC_EXT_CNTL bit constants */ #define CRTC_VGA_XOVERSCAN (1 << 0) #define VGA_ATI_LINEAR 0x00000008 #define VGA_128KAP_PAGING 0x00000010 #define XCRT_CNT_EN (1 << 6) #define CRTC_HSYNC_DIS (1 << 8) #define CRTC_VSYNC_DIS (1 << 9) #define CRTC_DISPLAY_DIS (1 << 10) #define CRTC_SYNC_TRISTAT (1 << 11) #define CRTC_CRT_ON (1 << 15) #define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 #define CRTC_HSYNC_DIS_BYTE (1 << 0) #define CRTC_VSYNC_DIS_BYTE (1 << 1) #define CRTC_DISPLAY_DIS_BYTE (1 << 2) #define WAIT_UNTIL 0x1720 #define WAIT_CRTC_PFLIP (1 << 0) #define WAIT_2D_IDLECLEAN (1 << 16) #define WAIT_3D_IDLECLEAN (1 << 17) #define WAIT_HOST_IDLECLEAN (1 << 18) #define ISYNC_CNTL 0x1724 #define RBBM_GUICNTL 0x172C #define RBBM_STATUS 0x0E40 #define RBBM_FIFOCNT_MASK 0x007f #define RBBM_ACTIVE (1 << 31) #define RBBM_STATUS_alt_1 0x1740 #define RBBM_CNTL 0x00EC #define RBBM_CNTL_alt_1 0x0E44 #define RBBM_SOFT_RESET 0x00F0 /* RBBM_SOFT_RESET bit constants */ #define SOFT_RESET_CP (1 << 0) #define SOFT_RESET_HI (1 << 1) #define SOFT_RESET_SE (1 << 2) #define SOFT_RESET_RE (1 << 3) #define SOFT_RESET_PP (1 << 4) #define SOFT_RESET_E2 (1 << 5) #define SOFT_RESET_RB (1 << 6) #define SOFT_RESET_HDP (1 << 7) #define RBBM_SOFT_RESET_alt_1 0x0E48 #define NQWAIT_UNTIL 0x0E50 #define RBBM_DEBUG 0x0E6C #define RBBM_CMDFIFO_ADDR 0x0E70 #define RBBM_CMDFIFO_DATAL 0x0E74 #define RBBM_CMDFIFO_DATAH 0x0E78 #define RBBM_CMDFIFO_STAT 0x0E7C #define CRTC_STATUS 0x005C /* CRTC_STATUS bit constants */ #define CRTC_VBLANK 0x00000001 #define CRTC_VBLANK_SAVE ( 1 << 1) #define GPIO_VGA_DDC 0x0060 #define GPIO_DVI_DDC 0x0064 #define GPIO_MONID 0x0068 #define PALETTE_INDEX 0x00B0 #define PALETTE_DATA 0x00B4 #define PALETTE_30_DATA 0x00B8 #define CRTC_H_TOTAL_DISP 0x0200 #define CRTC_H_TOTAL (0x03ff << 0) #define CRTC_H_TOTAL_SHIFT 0 #define CRTC_H_DISP (0x01ff << 16) #define CRTC_H_DISP_SHIFT 16 #define CRTC2_H_TOTAL_DISP 0x0300 #define CRTC2_H_TOTAL (0x03ff << 0) #define CRTC2_H_TOTAL_SHIFT 0 #define CRTC2_H_DISP (0x01ff << 16) #define CRTC2_H_DISP_SHIFT 16 #define CRTC_H_SYNC_STRT_WID 0x0204 #define CRTC_H_SYNC_STRT_PIX (0x07 << 0) #define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) #define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 #define CRTC_H_SYNC_WID (0x3f << 16) #define CRTC_H_SYNC_WID_SHIFT 16 #define CRTC_H_SYNC_POL (1 << 23) #define CRTC2_H_SYNC_STRT_WID 0x0304 #define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) #define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) #define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 #define CRTC2_H_SYNC_WID (0x3f << 16) #define CRTC2_H_SYNC_WID_SHIFT 16 #define CRTC2_H_SYNC_POL (1 << 23) #define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_TOTAL (0x07ff << 0) #define CRTC_V_TOTAL_SHIFT 0 #define CRTC_V_DISP (0x07ff << 16) #define CRTC_V_DISP_SHIFT 16 #define CRTC2_V_TOTAL_DISP 0x0308 #define CRTC2_V_TOTAL (0x07ff << 0) #define CRTC2_V_TOTAL_SHIFT 0 #define CRTC2_V_DISP (0x07ff << 16) #define CRTC2_V_DISP_SHIFT 16 #define CRTC_V_SYNC_STRT_WID 0x020C #define CRTC_V_SYNC_STRT (0x7ff << 0) #define CRTC_V_SYNC_STRT_SHIFT 0 #define CRTC_V_SYNC_WID (0x1f << 16) #define CRTC_V_SYNC_WID_SHIFT 16 #define CRTC_V_SYNC_POL (1 << 23) #define CRTC2_V_SYNC_STRT_WID 0x030C #define CRTC2_V_SYNC_STRT (0x7ff << 0) #define CRTC2_V_SYNC_STRT_SHIFT 0 #define CRTC2_V_SYNC_WID (0x1f << 16) #define CRTC2_V_SYNC_WID_SHIFT 16 #define CRTC2_V_SYNC_POL (1 << 23) #define CRTC_VLINE_CRNT_VLINE 0x0210 #define CRTC_CRNT_VLINE_MASK (0x7ff << 16) #define CRTC2_VLINE_CRNT_VLINE 0x0310 #define CRTC_CRNT_FRAME 0x0214 #define CRTC2_CRNT_FRAME 0x0314 #define CRTC_GUI_TRIG_VLINE 0x0218 #define CRTC2_GUI_TRIG_VLINE 0x0318 #define CRTC_DEBUG 0x021C #define CRTC2_DEBUG 0x031C #define CRTC_OFFSET_RIGHT 0x0220 #define CRTC_OFFSET 0x0224 #define CRTC2_OFFSET 0x0324 #define CRTC_OFFSET_CNTL 0x0228 #define CRTC_TILE_EN (1 << 15) #define CRTC2_OFFSET_CNTL 0x0328 #define CRTC2_TILE_EN (1 << 15) #define CRTC_PITCH 0x022C #define CRTC2_PITCH 0x032C #define TMDS_CRC 0x02a0 #define OVR_CLR 0x0230 #define OVR_WID_LEFT_RIGHT 0x0234 #define OVR_WID_TOP_BOTTOM 0x0238 #define DISPLAY_BASE_ADDR 0x023C #define SNAPSHOT_VH_COUNTS 0x0240 #define SNAPSHOT_F_COUNT 0x0244 #define N_VIF_COUNT 0x0248 #define SNAPSHOT_VIF_COUNT 0x024C #define FP_CRTC_H_TOTAL_DISP 0x0250 #define FP_CRTC2_H_TOTAL_DISP 0x0350 #define FP_CRTC_V_TOTAL_DISP 0x0254 #define FP_CRTC2_V_TOTAL_DISP 0x0354 #define FP_CRTC_H_TOTAL_MASK 0x000003ff #define FP_CRTC_H_DISP_MASK 0x01ff0000 #define FP_CRTC_V_TOTAL_MASK 0x00000fff #define FP_CRTC_V_DISP_MASK 0x0fff0000 #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 #define FP_H_SYNC_WID_MASK 0x003f0000 #define FP_V_SYNC_STRT_MASK 0x00000fff #define FP_V_SYNC_WID_MASK 0x001f0000 #define FP_CRTC_H_TOTAL_SHIFT 0x00000000 #define FP_CRTC_H_DISP_SHIFT 0x00000010 #define FP_CRTC_V_TOTAL_SHIFT 0x00000000 #define FP_CRTC_V_DISP_SHIFT 0x00000010 #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 #define FP_H_SYNC_WID_SHIFT 0x00000010 #define FP_V_SYNC_STRT_SHIFT 0x00000000 #define FP_V_SYNC_WID_SHIFT 0x00000010 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C #define CUR_OFFSET 0x0260 #define CUR_HORZ_VERT_POSN 0x0264 #define CUR_HORZ_VERT_OFF 0x0268 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ #define CUR_LOCK 0x80000000 #define CUR_CLR0 0x026C #define CUR_CLR1 0x0270 #define CUR2_OFFSET 0x0360 #define CUR2_HORZ_VERT_POSN 0x0364 #define CUR2_HORZ_VERT_OFF 0x0368 #define CUR2_LOCK (1 << 31) #define CUR2_CLR0 0x036c #define CUR2_CLR1 0x0370 #define FP_HORZ_VERT_ACTIVE 0x0278 #define CRTC_MORE_CNTL 0x027C #define DAC_EXT_CNTL 0x0280 #define FP_GEN_CNTL 0x0284 /* FP_GEN_CNTL bit constants */ #define FP_FPON (1 << 0) #define FP_TMDS_EN (1 << 2) #define FP_EN_TMDS (1 << 7) #define FP_DETECT_SENSE (1 << 8) #define FP_SEL_CRTC2 (1 << 13) #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) #define FP_CRTC_DONT_SHADOW_HEND (1 << 17) #define FP_CRTC_USE_SHADOW_VEND (1 << 18) #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) #define FP_DFP_SYNC_SEL (1 << 21) #define FP_CRTC_LOCK_8DOT (1 << 22) #define FP_CRT_SYNC_SEL (1 << 23) #define FP_USE_SHADOW_EN (1 << 24) #define FP_CRT_SYNC_ALT (1 << 26) #define FP2_GEN_CNTL 0x0288 /* FP2_GEN_CNTL bit constants */ #define FP2_FPON (1 << 0) #define FP2_TMDS_EN (1 << 2) #define FP2_EN_TMDS (1 << 7) #define FP2_DETECT_SENSE (1 << 8) #define FP2_SEL_CRTC2 (1 << 13) #define FP2_FP_POL (1 << 16) #define FP2_LP_POL (1 << 17) #define FP2_SCK_POL (1 << 18) #define FP2_LCD_CNTL_MASK (7 << 19) #define FP2_PAD_FLOP_EN (1 << 22) #define FP2_CRC_EN (1 << 23) #define FP2_CRC_READ_EN (1 << 24) #define FP_HORZ_STRETCH 0x028C #define FP_HORZ2_STRETCH 0x038C #define HORZ_STRETCH_RATIO_MASK 0xffff #define HORZ_STRETCH_RATIO_MAX 4096 #define HORZ_PANEL_SIZE (0x1ff << 16) #define HORZ_PANEL_SHIFT 16 #define HORZ_STRETCH_PIXREP (0 << 25) #define HORZ_STRETCH_BLEND (1 << 26) #define HORZ_STRETCH_ENABLE (1 << 25) #define HORZ_AUTO_RATIO (1 << 27) #define HORZ_FP_LOOP_STRETCH (0x7 << 28) #define HORZ_AUTO_RATIO_INC (1 << 31) #define FP_VERT_STRETCH 0x0290 #define FP_VERT2_STRETCH 0x0390 #define VERT_PANEL_SIZE (0xfff << 12) #define VERT_PANEL_SHIFT 12 #define VERT_STRETCH_RATIO_MASK 0xfff #define VERT_STRETCH_RATIO_SHIFT 0 #define VERT_STRETCH_RATIO_MAX 4096 #define VERT_STRETCH_ENABLE (1 << 25) #define VERT_STRETCH_LINEREP (0 << 26) #define VERT_STRETCH_BLEND (1 << 26) #define VERT_AUTO_RATIO_EN (1 << 27) #define VERT_STRETCH_RESERVED 0xf1000000 #define FP_H_SYNC_STRT_WID 0x02C4 #define FP_H2_SYNC_STRT_WID 0x03C4 #define FP_V_SYNC_STRT_WID 0x02C8 #define FP_V2_SYNC_STRT_WID 0x03C8 #define LVDS_GEN_CNTL 0x02d0 #define LVDS_ON (1 << 0) #define LVDS_DISPLAY_DIS (1 << 1) #define LVDS_PANEL_TYPE (1 << 2) #define LVDS_PANEL_FORMAT (1 << 3) #define LVDS_EN (1 << 7) #define LVDS_DIGON (1 << 18) #define LVDS_BLON (1 << 19) #define LVDS_SEL_CRTC2 (1 << 23) #define LVDS_PLL_CNTL 0x02d4 #define AUX_WINDOW_HORZ_CNTL 0x02D8 #define AUX_WINDOW_VERT_CNTL 0x02DC #define DDA_CONFIG 0x02e0 #define DDA_ON_OFF 0x02e4 #define GRPH_BUFFER_CNTL 0x02F0 #define VGA_BUFFER_CNTL 0x02F4 /* first overlay unit (there is only one) */ #define OV0_Y_X_START 0x0400 #define OV0_Y_X_END 0x0404 #define OV0_PIPELINE_CNTL 0x0408 #define OV0_EXCLUSIVE_HORZ 0x0408 #define EXCL_HORZ_START_MASK 0x000000ff #define EXCL_HORZ_END_MASK 0x0000ff00 #define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 #define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 #define OV0_EXCLUSIVE_VERT 0x040C #define EXCL_VERT_START_MASK 0x000003ff #define EXCL_VERT_END_MASK 0x03ff0000 #define OV0_REG_LOAD_CNTL 0x0410 #define REG_LD_CTL_LOCK 0x00000001L #define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L #define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L #define REG_LD_CTL_LOCK_READBACK 0x00000008L #define OV0_SCALE_CNTL 0x0420 #define SCALER_PIX_EXPAND 0x00000001L #define SCALER_Y2R_TEMP 0x00000002L #define SCALER_HORZ_PICK_NEAREST 0x00000004L #define SCALER_VERT_PICK_NEAREST 0x00000008L #define SCALER_SIGNED_UV 0x00000010L #define SCALER_GAMMA_SEL_MASK 0x00000060L #define SCALER_GAMMA_SEL_BRIGHT 0x00000000L #define SCALER_GAMMA_SEL_G22 0x00000020L #define SCALER_GAMMA_SEL_G18 0x00000040L #define SCALER_GAMMA_SEL_G14 0x00000060L #define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L #define SCALER_SURFAC_FORMAT 0x00000f00L #define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ #define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ #define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ #define SCALER_SOURCE_15BPP 0x00000300L #define SCALER_SOURCE_16BPP 0x00000400L /*# define SCALER_SOURCE_24BPP 0x00000500L*/ #define SCALER_SOURCE_32BPP 0x00000600L #define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ #define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ #define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ #define SCALER_SOURCE_YUV12 0x00000A00L #define SCALER_SOURCE_VYUY422 0x00000B00L #define SCALER_SOURCE_YVYU422 0x00000C00L #define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ #define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ #define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ #define SCALER_ADAPTIVE_DEINT 0x00001000L #define R200_SCALER_TEMPORAL_DEINT 0x00002000L #define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ #define SCALER_SMART_SWITCH 0x00008000L #define SCALER_BURST_PER_PLANE 0x007f0000L #define SCALER_DOUBLE_BUFFER 0x01000000L #define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ #define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ #define SCALER_DIS_LIMIT 0x08000000L #define SCALER_PRG_LOAD_START 0x10000000L #define SCALER_INT_EMU 0x20000000L #define SCALER_ENABLE 0x40000000L #define SCALER_SOFT_RESET 0x80000000L #define OV0_V_INC 0x0424 #define OV0_P1_V_ACCUM_INIT 0x0428 #define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L #define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L #define OV0_P23_V_ACCUM_INIT 0x042C #define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L #define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 #define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL #define P1_ACTIVE_LINES_M1 0x0fff0000L #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 #define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL #define P23_ACTIVE_LINES_M1 0x07ff0000L #define OV0_BASE_ADDR 0x043C #define OV0_VID_BUF0_BASE_ADRS 0x0440 #define VIF_BUF0_PITCH_SEL 0x00000001L #define VIF_BUF0_TILE_ADRS 0x00000002L #define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF1_BASE_ADRS 0x0444 #define VIF_BUF1_PITCH_SEL 0x00000001L #define VIF_BUF1_TILE_ADRS 0x00000002L #define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF2_BASE_ADRS 0x0448 #define VIF_BUF2_PITCH_SEL 0x00000001L #define VIF_BUF2_TILE_ADRS 0x00000002L #define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF3_BASE_ADRS 0x044C #define VIF_BUF3_PITCH_SEL 0x00000001L #define VIF_BUF3_TILE_ADRS 0x00000002L #define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF4_BASE_ADRS 0x0450 #define VIF_BUF4_PITCH_SEL 0x00000001L #define VIF_BUF4_TILE_ADRS 0x00000002L #define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF5_BASE_ADRS 0x0454 #define VIF_BUF5_PITCH_SEL 0x00000001L #define VIF_BUF5_TILE_ADRS 0x00000002L #define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0L #define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF_PITCH0_VALUE 0x0460 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 #define OV0_AUTO_FLIP_CNTL 0x0470 #define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 #define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 #define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 #define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 #define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 #define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 #define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 #define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 #define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 #define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 #define OV0_DEINTERLACE_PATTERN 0x0474 #define OV0_SUBMIT_HISTORY 0x0478 #define OV0_H_INC 0x0480 #define OV0_STEP_BY 0x0484 #define OV0_P1_H_ACCUM_INIT 0x0488 #define OV0_P23_H_ACCUM_INIT 0x048C #define OV0_P1_X_START_END 0x0494 #define OV0_P2_X_START_END 0x0498 #define OV0_P3_X_START_END 0x049C #define OV0_FILTER_CNTL 0x04A0 #define FILTER_PROGRAMMABLE_COEF 0x00000000 #define FILTER_HARD_SCALE_HORZ_Y 0x00000001 #define FILTER_HARD_SCALE_HORZ_UV 0x00000002 #define FILTER_HARD_SCALE_VERT_Y 0x00000004 #define FILTER_HARD_SCALE_VERT_UV 0x00000008 #define FILTER_HARDCODED_COEF 0x0000000F #define FILTER_COEF_MASK 0x0000000F /* When bit is set hard coded coefficients are used. */ /* Top quality 4x4-tap filtered vertical and horizontal scaler. It allows up to 64:1 upscaling and downscaling without performance or quality degradation. */ #define OV0_FOUR_TAP_COEF_0 0x04B0 #define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F #define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 #define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 #define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 #define OV0_FOUR_TAP_COEF_1 0x04B4 #define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F #define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 #define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 #define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 #define OV0_FOUR_TAP_COEF_2 0x04B8 #define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F #define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 #define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 #define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 #define OV0_FOUR_TAP_COEF_3 0x04BC #define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F #define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 #define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 #define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 #define OV0_FOUR_TAP_COEF_4 0x04C0 #define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F #define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 #define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 #define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 /* 0th_tap means that the left most of top most pixel in a set of four will be multiplied by this coefficient. */ #define OV0_FLAG_CNTL 0x04DC #define OV0_SLICE_CNTL 0x04E0 #define SLICE_CNTL_DISABLE 0x40000000 /* Video and graphics keys allow alpha blending, color correction and many other video effects */ #define OV0_VID_KEY_CLR 0x04E4 #define OV0_VID_KEY_MSK 0x04E8 #define OV0_GRAPHICS_KEY_CLR 0x04EC #define OV0_GRAPHICS_KEY_MSK 0x04F0 #define OV0_KEY_CNTL 0x04F4 #define VIDEO_KEY_FN_MASK 0x00000003L #define VIDEO_KEY_FN_FALSE 0x00000000L #define VIDEO_KEY_FN_TRUE 0x00000001L #define VIDEO_KEY_FN_EQ 0x00000002L #define VIDEO_KEY_FN_NE 0x00000003L #define GRAPHIC_KEY_FN_MASK 0x00000030L #define GRAPHIC_KEY_FN_FALSE 0x00000000L #define GRAPHIC_KEY_FN_TRUE 0x00000010L #define GRAPHIC_KEY_FN_EQ 0x00000020L #define GRAPHIC_KEY_FN_NE 0x00000030L #define CMP_MIX_MASK 0x00000100L #define CMP_MIX_OR 0x00000000L #define CMP_MIX_AND 0x00000100L #define OV0_TEST 0x04F8 #define OV0_SCALER_Y2R_DISABLE 0x00000001L #define OV0_SUBPIC_ONLY 0x00000008L #define OV0_EXTENSE 0x00000010L #define OV0_SWAP_UV 0x00000020L #define OV0_LIN_TRANS_A 0x0D20 #define OV0_LIN_TRANS_B 0x0D24 #define OV0_LIN_TRANS_C 0x0D28 #define OV0_LIN_TRANS_D 0x0D2C #define OV0_LIN_TRANS_E 0x0D30 #define OV0_LIN_TRANS_F 0x0D34 #define OV0_GAMMA_0_F 0x0D40 #define OV0_GAMMA_10_1F 0x0D44 #define OV0_GAMMA_20_3F 0x0D48 #define OV0_GAMMA_40_7F 0x0D4C /* These registers exist on R200 only */ #define OV0_GAMMA_80_BF 0x0E00 #define OV0_GAMMA_C0_FF 0x0E04 #define OV0_GAMMA_100_13F 0x0E08 #define OV0_GAMMA_140_17F 0x0E0C #define OV0_GAMMA_180_1BF 0x0E10 #define OV0_GAMMA_1C0_1FF 0x0E14 #define OV0_GAMMA_200_23F 0x0E18 #define OV0_GAMMA_240_27F 0x0E1C #define OV0_GAMMA_280_2BF 0x0E20 #define OV0_GAMMA_2C0_2FF 0x0E24 #define OV0_GAMMA_300_33F 0x0E28 #define OV0_GAMMA_340_37F 0x0E2C /* End of R200 specific definitions */ #define OV0_GAMMA_380_3BF 0x0D50 #define OV0_GAMMA_3C0_3FF 0x0D54 /* IDCT ENGINE: It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag and IDCT into an IDCT engine to complement the motion compensation engine. */ #define IDCT_RUNS 0x1F80 #define IDCT_LEVELS 0x1F84 #define IDCT_AUTH_CONTROL 0x1F88 #define IDCT_AUTH 0x1F8C #define IDCT_CONTROL 0x1FBC #define SE_MC_SRC2_CNTL 0x19D4 #define SE_MC_SRC1_CNTL 0x19D8 #define SE_MC_DST_CNTL 0x19DC #define SE_MC_CNTL_START 0x19E0 #define SE_MC_BUF_BASE 0x19E4 #define PP_MC_CONTEXT 0x19E8 /* SUBPICTURE UNIT: Decompressing, scaling and alpha blending the compressed bitmap on the fly. Provide optimal DVD subpicture qualtity. */ #define SUBPIC_CNTL 0x0540 #define SUBPIC_DEFCOLCON 0x0544 #define SUBPIC_Y_X_START 0x054C #define SUBPIC_Y_X_END 0x0550 #define SUBPIC_V_INC 0x0554 #define SUBPIC_H_INC 0x0558 #define SUBPIC_BUF0_OFFSET 0x055C #define SUBPIC_BUF1_OFFSET 0x0560 #define SUBPIC_LC0_OFFSET 0x0564 #define SUBPIC_LC1_OFFSET 0x0568 #define SUBPIC_PITCH 0x056C #define SUBPIC_BTN_HLI_COLCON 0x0570 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 #define SUBPIC_PALETTE_INDEX 0x057C #define SUBPIC_PALETTE_DATA 0x0580 #define SUBPIC_H_ACCUM_INIT 0x0584 #define SUBPIC_V_ACCUM_INIT 0x0588 #define CP_RB_BASE 0x0700 #define CP_RB_CNTL 0x0704 #define CP_RB_RPTR_ADDR 0x070C #define CP_RB_RPTR 0x0710 #define CP_RB_WPTR 0x0714 #define CP_RB_WPTR_DELAY 0x0718 #define CP_IB_BASE 0x0738 #define CP_IB_BUFSZ 0x073C #define CP_CSQ_CNTL 0x0740 #define SCRATCH_UMSK 0x0770 #define SCRATCH_ADDR 0x0774 #define DMA_GUI_TABLE_ADDR 0x0780 #define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff #define DMA_GUI_COMMAND__INTDIS 0x40000000 #define DMA_GUI_COMMAND__EOL 0x80000000 #define DMA_GUI_SRC_ADDR 0x0784 #define DMA_GUI_DST_ADDR 0x0788 #define DMA_GUI_COMMAND 0x078C #define DMA_GUI_STATUS 0x0790 #define DMA_GUI_ACT_DSCRPTR 0x0794 #define DMA_VID_TABLE_ADDR 0x07A0 #define DMA_VID_SRC_ADDR 0x07A4 #define DMA_VID_DST_ADDR 0x07A8 #define DMA_VID_COMMAND 0x07AC #define DMA_VID_STATUS 0x07B0 #define DMA_VID_ACT_DSCRPTR 0x07B4 #define CP_ME_CNTL 0x07D0 #define CP_ME_RAM_ADDR 0x07D4 #define CP_ME_RAM_RADDR 0x07D8 #define CP_ME_RAM_DATAH 0x07DC #define CP_ME_RAM_DATAL 0x07E0 #define CP_CSQ_ADDR 0x07F0 #define CP_CSQ_DATA 0x07F4 #define CP_CSQ_STAT 0x07F8 #define DISP_MISC_CNTL 0x0D00 #define SOFT_RESET_GRPH_PP (1 << 0) #define DAC_MACRO_CNTL 0x0D04 #define DISP_PWR_MAN 0x0D08 #define DISP_TEST_DEBUG_CNTL 0x0D10 #define DISP_HW_DEBUG 0x0D14 #define DAC_CRC_SIG1 0x0D18 #define DAC_CRC_SIG2 0x0D1C /* first capture unit */ #define VID_BUFFER_CONTROL 0x0900 #define CAP_INT_CNTL 0x0908 #define CAP_INT_STATUS 0x090C #define FCP_CNTL 0x0910 #define FCP0_SRC_PCICLK 0 #define FCP0_SRC_PCLK 1 #define FCP0_SRC_PCLKb 2 #define FCP0_SRC_HREF 3 #define FCP0_SRC_GND 4 #define FCP0_SRC_HREFb 5 #define CAP0_BUF0_OFFSET 0x0920 #define CAP0_BUF1_OFFSET 0x0924 #define CAP0_BUF0_EVEN_OFFSET 0x0928 #define CAP0_BUF1_EVEN_OFFSET 0x092C #define CAP0_BUF_PITCH 0x0930 #define CAP0_V_WINDOW 0x0934 #define CAP0_H_WINDOW 0x0938 #define CAP0_VBI0_OFFSET 0x093C #define CAP0_VBI1_OFFSET 0x0940 #define CAP0_VBI_V_WINDOW 0x0944 #define CAP0_VBI_H_WINDOW 0x0948 #define CAP0_PORT_MODE_CNTL 0x094C #define CAP0_TRIG_CNTL 0x0950 #define CAP0_DEBUG 0x0954 #define CAP0_CONFIG 0x0958 #define CAP0_CONFIG_CONTINUOS 0x00000001 #define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 #define CAP0_CONFIG_START_BUF_GET 0x00000004 #define CAP0_CONFIG_START_BUF_SET 0x00000008 #define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 #define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 #define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 #define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 #define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 #define CAP0_CONFIG_MIRROR_EN 0x00000200 #define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 #define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 #define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 #define CAP0_CONFIG_VBI_EN 0x00002000 #define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 #define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 #define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 #define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 #define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 #define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 #define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 #define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 #define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 #define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 #define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 #define CAP0_CONFIG_FORMAT_ZV 0x01000000 #define CAP0_CONFIG_FORMAT_VIP 0x01800000 #define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 #define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 #define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 #define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 #define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 #define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 #define CAP0_ANC_ODD_OFFSET 0x095C #define CAP0_ANC_EVEN_OFFSET 0x0960 #define CAP0_ANC_H_WINDOW 0x0964 #define CAP0_VIDEO_SYNC_TEST 0x0968 #define CAP0_ONESHOT_BUF_OFFSET 0x096C #define CAP0_BUF_STATUS 0x0970 /* #define CAP0_DWNSC_XRATIO 0x0978 */ /* #define CAP0_XSHARPNESS 0x097C */ #define CAP0_VBI2_OFFSET 0x0980 #define CAP0_VBI3_OFFSET 0x0984 #define CAP0_ANC2_OFFSET 0x0988 #define CAP0_ANC3_OFFSET 0x098C /* second capture unit */ #define CAP1_BUF0_OFFSET 0x0990 #define CAP1_BUF1_OFFSET 0x0994 #define CAP1_BUF0_EVEN_OFFSET 0x0998 #define CAP1_BUF1_EVEN_OFFSET 0x099C #define CAP1_BUF_PITCH 0x09A0 #define CAP1_V_WINDOW 0x09A4 #define CAP1_H_WINDOW 0x09A8 #define CAP1_VBI_ODD_OFFSET 0x09AC #define CAP1_VBI_EVEN_OFFSET 0x09B0 #define CAP1_VBI_V_WINDOW 0x09B4 #define CAP1_VBI_H_WINDOW 0x09B8 #define CAP1_PORT_MODE_CNTL 0x09BC #define CAP1_DEBUG 0x09C4 #define CAP1_CONFIG 0x09C8 #define CAP1_ANC_ODD_OFFSET 0x09CC #define CAP1_ANC_EVEN_OFFSET 0x09D0 #define CAP1_ANC_H_WINDOW 0x09D4 #define CAP1_VIDEO_SYNC_TEST 0x09D8 #define CAP1_ONESHOT_BUF_OFFSET 0x09DC #define CAP1_BUF_STATUS 0x09E0 #define CAP1_DWNSC_XRATIO 0x09E8 #define CAP1_XSHARPNESS 0x09EC #define DISP_MERGE_CNTL 0x0D60 #define DISP_OUTPUT_CNTL 0x0D64 #define DISP_DAC_SOURCE_MASK 0x03 #define DISP_DAC_SOURCE_CRTC2 0x01 #define DISP_LIN_TRANS_GRPH_A 0x0D80 #define DISP_LIN_TRANS_GRPH_B 0x0D84 #define DISP_LIN_TRANS_GRPH_C 0x0D88 #define DISP_LIN_TRANS_GRPH_D 0x0D8C #define DISP_LIN_TRANS_GRPH_E 0x0D90 #define DISP_LIN_TRANS_GRPH_F 0x0D94 #define DISP_LIN_TRANS_VID_A 0x0D98 #define DISP_LIN_TRANS_VID_B 0x0D9C #define DISP_LIN_TRANS_VID_C 0x0DA0 #define DISP_LIN_TRANS_VID_D 0x0DA4 #define DISP_LIN_TRANS_VID_E 0x0DA8 #define DISP_LIN_TRANS_VID_F 0x0DAC #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 #define RMX_HORZ_PHASE 0x0DBC #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 #define DAC_BROAD_PULSE 0x0DC4 #define DAC_SKEW_CLKS 0x0DC8 #define DAC_INCR 0x0DCC #define DAC_NEG_SYNC_LEVEL 0x0DD0 #define DAC_POS_SYNC_LEVEL 0x0DD4 #define DAC_BLANK_LEVEL 0x0DD8 #define CLOCK_CNTL_INDEX 0x0008 /* CLOCK_CNTL_INDEX bit constants */ #define PLL_WR_EN 0x00000080 #define PLL_DIV_SEL (3 << 8) #define PLL2_DIV_SEL_MASK ~(3 << 8) #define CLOCK_CNTL_DATA 0x000C #define CP_RB_CNTL 0x0704 #define CP_RB_BASE 0x0700 #define CP_RB_RPTR_ADDR 0x070C #define CP_RB_RPTR 0x0710 #define CP_RB_WPTR 0x0714 #define CP_RB_WPTR_DELAY 0x0718 #define CP_IB_BASE 0x0738 #define CP_IB_BUFSZ 0x073C #define SCRATCH_REG0 0x15E0 #define GUI_SCRATCH_REG0 0x15E0 #define SCRATCH_REG1 0x15E4 #define GUI_SCRATCH_REG1 0x15E4 #define SCRATCH_REG2 0x15E8 #define GUI_SCRATCH_REG2 0x15E8 #define SCRATCH_REG3 0x15EC #define GUI_SCRATCH_REG3 0x15EC #define SCRATCH_REG4 0x15F0 #define GUI_SCRATCH_REG4 0x15F0 #define SCRATCH_REG5 0x15F4 #define GUI_SCRATCH_REG5 0x15F4 #define SCRATCH_UMSK 0x0770 #define SCRATCH_ADDR 0x0774 #define DP_BRUSH_FRGD_CLR 0x147C #define DP_BRUSH_BKGD_CLR 0x1478 #define DST_LINE_START 0x1600 #define DST_LINE_END 0x1604 #define SRC_OFFSET 0x15AC #define SRC_PITCH 0x15B0 #define SRC_TILE 0x1704 #define SRC_PITCH_OFFSET 0x1428 #define SRC_X 0x1414 #define SRC_Y 0x1418 #define DST_WIDTH_X 0x1588 #define DST_HEIGHT_WIDTH_8 0x158C #define SRC_X_Y 0x1590 #define SRC_Y_X 0x1434 #define DST_Y_X 0x1438 #define DST_WIDTH_HEIGHT 0x1598 #define DST_HEIGHT_WIDTH 0x143c #define SRC_CLUT_ADDRESS 0x1780 #define SRC_CLUT_DATA 0x1784 #define SRC_CLUT_DATA_RD 0x1788 #define HOST_DATA0 0x17C0 #define HOST_DATA1 0x17C4 #define HOST_DATA2 0x17C8 #define HOST_DATA3 0x17CC #define HOST_DATA4 0x17D0 #define HOST_DATA5 0x17D4 #define HOST_DATA6 0x17D8 #define HOST_DATA7 0x17DC #define HOST_DATA_LAST 0x17E0 #define DP_SRC_ENDIAN 0x15D4 #define DP_SRC_FRGD_CLR 0x15D8 #define DP_SRC_BKGD_CLR 0x15DC #define DP_WRITE_MASK 0x16cc #define SC_LEFT 0x1640 #define SC_RIGHT 0x1644 #define SC_TOP 0x1648 #define SC_BOTTOM 0x164C #define SRC_SC_RIGHT 0x1654 #define SRC_SC_BOTTOM 0x165C #define DP_CNTL 0x16C0 /* DP_CNTL bit constants */ #define DST_X_RIGHT_TO_LEFT 0x00000000 #define DST_X_LEFT_TO_RIGHT 0x00000001 #define DST_Y_BOTTOM_TO_TOP 0x00000000 #define DST_Y_TOP_TO_BOTTOM 0x00000002 #define DST_X_MAJOR 0x00000000 #define DST_Y_MAJOR 0x00000004 #define DST_X_TILE 0x00000008 #define DST_Y_TILE 0x00000010 #define DST_LAST_PEL 0x00000020 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 #define DST_BRES_SIGN 0x00000100 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 #define DST_POLYLINE_NONLAST 0x00008000 #define DST_RASTER_STALL 0x00010000 #define DST_POLY_EDGE 0x00040000 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 /* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ #define DST_X_MAJOR_S 0x00000000 #define DST_Y_MAJOR_S 0x00000001 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 #define DST_X_RIGHT_TO_LEFT_S 0x00000000 #define DST_X_LEFT_TO_RIGHT_S 0x80000000 #define DP_DATATYPE 0x16C4 /* DP_DATATYPE bit constants */ #define DST_8BPP 0x00000002 #define DST_15BPP 0x00000003 #define DST_16BPP 0x00000004 #define DST_24BPP 0x00000005 #define DST_32BPP 0x00000006 #define DST_8BPP_RGB332 0x00000007 #define DST_8BPP_Y8 0x00000008 #define DST_8BPP_RGB8 0x00000009 #define DST_16BPP_VYUY422 0x0000000b #define DST_16BPP_YVYU422 0x0000000c #define DST_32BPP_AYUV444 0x0000000e #define DST_16BPP_ARGB4444 0x0000000f #define BRUSH_SOLIDCOLOR 0x00000d00 #define SRC_MONO 0x00000000 #define SRC_MONO_LBKGD 0x00010000 #define SRC_DSTCOLOR 0x00030000 #define BYTE_ORDER_MSB_TO_LSB 0x00000000 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 #define DP_CONVERSION_TEMP 0x80000000 #define HOST_BIG_ENDIAN_EN (1 << 29) #define DP_MIX 0x16C8 /* DP_MIX bit constants */ #define DP_SRC_RECT 0x00000200 #define DP_SRC_HOST 0x00000300 #define DP_SRC_HOST_BYTEALIGN 0x00000400 #define DP_WRITE_MSK 0x16CC #define DP_XOP 0x17F8 #define CLR_CMP_CLR_SRC 0x15C4 #define CLR_CMP_CLR_DST 0x15C8 #define CLR_CMP_CNTL 0x15C0 /* CLR_CMP_CNTL bit constants */ #define COMPARE_SRC_FALSE 0x00000000 #define COMPARE_SRC_TRUE 0x00000001 #define COMPARE_SRC_NOT_EQUAL 0x00000004 #define COMPARE_SRC_EQUAL 0x00000005 #define COMPARE_SRC_EQUAL_FLIP 0x00000007 #define COMPARE_DST_FALSE 0x00000000 #define COMPARE_DST_TRUE 0x00000100 #define COMPARE_DST_NOT_EQUAL 0x00000400 #define COMPARE_DST_EQUAL 0x00000500 #define COMPARE_DESTINATION 0x00000000 #define COMPARE_SOURCE 0x01000000 #define COMPARE_SRC_AND_DST 0x02000000 #define CLR_CMP_MSK 0x15CC #define DSTCACHE_MODE 0x1710 #define DSTCACHE_CTLSTAT 0x1714 /* DSTCACHE_CTLSTAT bit constants */ #define RB2D_DC_FLUSH (3 << 0) #define RB2D_DC_FLUSH_ALL 0xf #define RB2D_DC_BUSY (1 << 31) #define DEFAULT_OFFSET 0x16e0 #define DEFAULT_PITCH_OFFSET 0x16E0 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) #define DP_GUI_MASTER_CNTL 0x146C /* DP_GUI_MASTER_CNTL bit constants */ #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_SRC_CLIP_LEAVE 0x00000004 #define GMC_DST_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_LEAVE 0x00000008 #define GMC_BRUSH_8x8MONO 0x00000000 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 #define GMC_BRUSH_8x1MONO 0x00000020 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 #define GMC_BRUSH_1x8MONO 0x00000040 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 #define GMC_BRUSH_32x1MONO 0x00000060 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 #define GMC_BRUSH_32x32MONO 0x00000080 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 #define GMC_BRUSH_8x8COLOR 0x000000a0 #define GMC_BRUSH_8x1COLOR 0x000000b0 #define GMC_BRUSH_1x8COLOR 0x000000c0 //#define GMC_BRUSH_SOLID_COLOR 0x000000d0 //#define GMC_DST_8BPP 0x00000200 //#define GMC_DST_15BPP 0x00000300 //#define GMC_DST_16BPP 0x00000400 //#define GMC_DST_24BPP 0x00000500 //#define GMC_DST_32BPP 0x00000600 //#define GMC_DST_8BPP_RGB332 0x00000700 //#define GMC_DST_8BPP_Y8 0x00000800 //#define GMC_DST_8BPP_RGB8 0x00000900 //#define GMC_DST_16BPP_VYUY422 0x00000b00 //#define GMC_DST_16BPP_YVYU422 0x00000c00 //#define GMC_DST_32BPP_AYUV444 0x00000e00 //#define GMC_DST_16BPP_ARGB4444 0x00000f00 #define GMC_SRC_MONO 0x00000000 #define GMC_SRC_MONO_LBKGD 0x00001000 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 #define GMC_DP_SRC_RECT 0x02000000 #define GMC_DP_SRC_HOST 0x03000000 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 #define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_3D_FCN_EN_SET 0x08000000 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 #define GMC_AUX_CLIP_LEAVE 0x00000000 #define GMC_AUX_CLIP_CLEAR 0x20000000 #define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define ROP3_S 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000 #define ROP3_P 0x00f00000 #define ROP3_PATCOPY 0x00f00000 #define DP_SRC_SOURCE_MASK (7 << 24) #define GMC_BRUSH_NONE (15 << 4) #define DP_SRC_SOURCE_MEMORY (2 << 24) #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define SC_TOP_LEFT 0x16EC #define SC_BOTTOM_RIGHT 0x16F0 #define SRC_SC_BOTTOM_RIGHT 0x16F4 #define RB2D_DSTCACHE_CTLSTAT 0x342C #define RB2D_DSTCACHE_MODE 0x3428 #define CLK_PIN_CNTL 0x0001 #define PPLL_CNTL 0x0002 //#define PPLL_RESET (1 << 0) //#define PPLL_SLEEP (1 << 1) //#define PPLL_ATOMIC_UPDATE_EN (1 << 16) //#define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) //#define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) //#define PPLL_REF_DIV 0x0003 //#define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ //#define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define PPLL_DIV_0 0x0004 #define PPLL_DIV_1 0x0005 #define PPLL_DIV_2 0x0006 #define PPLL_DIV_3 0x0007 #define VCLK_ECP_CNTL 0x0008 #define VCLK_SRC_SEL_MASK 0x03 #define VCLK_SRC_SEL_CPUCLK 0x00 #define VCLK_SRC_SEL_PSCANCLK 0x01 #define VCLK_SRC_SEL_BYTECLK 0x02 #define VCLK_SRC_SEL_PPLLCLK 0x03 #define HTOTAL_CNTL 0x0009 #define HTOTAL2_CNTL 0x002e /* PLL */ #define M_SPLL_REF_FB_DIV 0x000a #define AGP_PLL_CNTL 0x000b #define SPLL_CNTL 0x000c #define SCLK_CNTL 0x000d #define DYN_STOP_LAT_MASK 0x00007ff8 #define CP_MAX_DYN_STOP_LAT 0x0008 #define SCLK_FORCEON_MASK 0xffff8000 #define SCLK_MORE_CNTL 0x0035 /* PLL */ #define SCLK_MORE_FORCEON 0x0700 #define MPLL_CNTL 0x000e #define MCLK_CNTL 0x0012 /* MCLK_CNTL bit constants */ #define FORCEON_MCLKA (1 << 16) #define FORCEON_MCLKB (1 << 17) #define FORCEON_YCLKA (1 << 18) #define FORCEON_YCLKB (1 << 19) #define FORCEON_MC (1 << 20) #define FORCEON_AIC (1 << 21) #define PLL_TEST_CNTL 0x0013 #define P2PLL_CNTL 0x002a /* P2PLL */ #define P2PLL_RESET (1 << 0) #define P2PLL_SLEEP (1 << 1) #define P2PLL_ATOMIC_UPDATE_EN (1 << 16) #define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) #define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define P2PLL_DIV_0 0x002c #define P2PLL_FB0_DIV_MASK 0x07ff #define P2PLL_POST0_DIV_MASK 0x00070000 #define P2PLL_REF_DIV_MASK 0x03ff #define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ #define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define PIXCLKS_CNTL 0x002d #define PIX2CLK_SRC_SEL_MASK 0x03 #define PIX2CLK_SRC_SEL_CPUCLK 0x00 #define PIX2CLK_SRC_SEL_PSCANCLK 0x01 #define PIX2CLK_SRC_SEL_BYTECLK 0x02 #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 /* masks */ #define CONFIG_MEMSIZE_MASK 0x1f000000 #define MEM_CFG_TYPE 0x40000000 #define DST_OFFSET_MASK 0x003fffff #define DST_PITCH_MASK 0x3fc00000 #define DEFAULT_TILE_MASK 0xc0000000 #define PPLL_DIV_SEL_MASK 0x00000300 #define PPLL_FB3_DIV_MASK 0x000007ff #define PPLL_POST3_DIV_MASK 0x00070000 /* Registers for 3D/TCL */ #define PP_BORDER_COLOR_0 0x1d40 #define PP_BORDER_COLOR_1 0x1d44 #define PP_BORDER_COLOR_2 0x1d48 #define PP_CNTL 0x1c38 #define STIPPLE_ENABLE (1 << 0) #define SCISSOR_ENABLE (1 << 1) #define PATTERN_ENABLE (1 << 2) #define SHADOW_ENABLE (1 << 3) #define TEX_ENABLE_MASK (0xf << 4) #define TEX_0_ENABLE (1 << 4) #define TEX_1_ENABLE (1 << 5) #define TEX_2_ENABLE (1 << 6) #define TEX_3_ENABLE (1 << 7) #define TEX_BLEND_ENABLE_MASK (0xf << 12) #define TEX_BLEND_0_ENABLE (1 << 12) #define TEX_BLEND_1_ENABLE (1 << 13) #define TEX_BLEND_2_ENABLE (1 << 14) #define TEX_BLEND_3_ENABLE (1 << 15) #define PLANAR_YUV_ENABLE (1 << 20) #define SPECULAR_ENABLE (1 << 21) #define FOG_ENABLE (1 << 22) #define ALPHA_TEST_ENABLE (1 << 23) #define ANTI_ALIAS_NONE (0 << 24) #define ANTI_ALIAS_LINE (1 << 24) #define ANTI_ALIAS_POLY (2 << 24) #define ANTI_ALIAS_LINE_POLY (3 << 24) #define BUMP_MAP_ENABLE (1 << 26) #define BUMPED_MAP_T0 (0 << 27) #define BUMPED_MAP_T1 (1 << 27) #define BUMPED_MAP_T2 (2 << 27) #define TEX_3D_ENABLE_0 (1 << 29) #define TEX_3D_ENABLE_1 (1 << 30) #define MC_ENABLE (1 << 31) #define PP_FOG_COLOR 0x1c18 #define FOG_COLOR_MASK 0x00ffffff #define FOG_VERTEX (0 << 24) #define FOG_TABLE (1 << 24) #define FOG_USE_DEPTH (0 << 25) #define FOG_USE_DIFFUSE_ALPHA (2 << 25) #define FOG_USE_SPEC_ALPHA (3 << 25) #define PP_LUM_MATRIX 0x1d00 #define PP_MISC 0x1c14 #define REF_ALPHA_MASK 0x000000ff #define ALPHA_TEST_FAIL (0 << 8) #define ALPHA_TEST_LESS (1 << 8) #define ALPHA_TEST_LEQUAL (2 << 8) #define ALPHA_TEST_EQUAL (3 << 8) #define ALPHA_TEST_GEQUAL (4 << 8) #define ALPHA_TEST_GREATER (5 << 8) #define ALPHA_TEST_NEQUAL (6 << 8) #define ALPHA_TEST_PASS (7 << 8) #define ALPHA_TEST_OP_MASK (7 << 8) #define CHROMA_FUNC_FAIL (0 << 16) #define CHROMA_FUNC_PASS (1 << 16) #define CHROMA_FUNC_NEQUAL (2 << 16) #define CHROMA_FUNC_EQUAL (3 << 16) #define CHROMA_KEY_NEAREST (0 << 18) #define CHROMA_KEY_ZERO (1 << 18) #define SHADOW_ID_AUTO_INC (1 << 20) #define SHADOW_FUNC_EQUAL (0 << 21) #define SHADOW_FUNC_NEQUAL (1 << 21) #define SHADOW_PASS_1 (0 << 22) #define SHADOW_PASS_2 (1 << 22) #define RIGHT_HAND_CUBE_D3D (0 << 24) #define RIGHT_HAND_CUBE_OGL (1 << 24) #define PP_ROT_MATRIX_0 0x1d58 #define PP_ROT_MATRIX_1 0x1d5c #define PP_TXFILTER_0 0x1c54 #define PP_TXFILTER_1 0x1c6c #define PP_TXFILTER_2 0x1c84 #define MAG_FILTER_NEAREST (0 << 0) #define MAG_FILTER_LINEAR (1 << 0) #define MAG_FILTER_MASK (1 << 0) #define MIN_FILTER_NEAREST (0 << 1) #define MIN_FILTER_LINEAR (1 << 1) #define MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) #define MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) #define MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) #define MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) #define MIN_FILTER_ANISO_NEAREST (8 << 1) #define MIN_FILTER_ANISO_LINEAR (9 << 1) #define MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) #define MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) #define MIN_FILTER_MASK (15 << 1) #define MAX_ANISO_1_TO_1 (0 << 5) #define MAX_ANISO_2_TO_1 (1 << 5) #define MAX_ANISO_4_TO_1 (2 << 5) #define MAX_ANISO_8_TO_1 (3 << 5) #define MAX_ANISO_16_TO_1 (4 << 5) #define MAX_ANISO_MASK (7 << 5) #define LOD_BIAS_MASK (0xff << 8) #define LOD_BIAS_SHIFT 8 #define MAX_MIP_LEVEL_MASK (0x0f << 16) #define MAX_MIP_LEVEL_SHIFT 16 #define YUV_TO_RGB (1 << 20) #define YUV_TEMPERATURE_COOL (0 << 21) #define YUV_TEMPERATURE_HOT (1 << 21) #define YUV_TEMPERATURE_MASK (1 << 21) #define WRAPEN_S (1 << 22) #define CLAMP_S_WRAP (0 << 23) #define CLAMP_S_MIRROR (1 << 23) #define CLAMP_S_CLAMP_LAST (2 << 23) #define CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) #define CLAMP_S_CLAMP_BORDER (4 << 23) #define CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) #define CLAMP_S_CLAMP_GL (6 << 23) #define CLAMP_S_MIRROR_CLAMP_GL (7 << 23) #define CLAMP_S_MASK (7 << 23) #define WRAPEN_T (1 << 26) #define CLAMP_T_WRAP (0 << 27) #define CLAMP_T_MIRROR (1 << 27) #define CLAMP_T_CLAMP_LAST (2 << 27) #define CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) #define CLAMP_T_CLAMP_BORDER (4 << 27) #define CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) #define CLAMP_T_CLAMP_GL (6 << 27) #define CLAMP_T_MIRROR_CLAMP_GL (7 << 27) #define CLAMP_T_MASK (7 << 27) #define BORDER_MODE_OGL (0 << 31) #define BORDER_MODE_D3D (1 << 31) #define PP_TXFORMAT_0 0x1c58 #define PP_TXFORMAT_1 0x1c70 #define PP_TXFORMAT_2 0x1c88 #define TXFORMAT_I8 (0 << 0) #define TXFORMAT_AI88 (1 << 0) #define TXFORMAT_RGB332 (2 << 0) #define TXFORMAT_ARGB1555 (3 << 0) #define TXFORMAT_RGB565 (4 << 0) #define TXFORMAT_ARGB4444 (5 << 0) #define TXFORMAT_ARGB8888 (6 << 0) #define TXFORMAT_RGBA8888 (7 << 0) #define TXFORMAT_Y8 (8 << 0) #define TXFORMAT_VYUY422 (10 << 0) #define TXFORMAT_YVYU422 (11 << 0) #define TXFORMAT_DXT1 (12 << 0) #define TXFORMAT_DXT23 (14 << 0) #define TXFORMAT_DXT45 (15 << 0) #define TXFORMAT_FORMAT_MASK (31 << 0) #define TXFORMAT_FORMAT_SHIFT 0 #define TXFORMAT_APPLE_YUV_MODE (1 << 5) #define TXFORMAT_ALPHA_IN_MAP (1 << 6) #define TXFORMAT_NON_POWER2 (1 << 7) #define TXFORMAT_WIDTH_MASK (15 << 8) #define TXFORMAT_WIDTH_SHIFT 8 #define TXFORMAT_HEIGHT_MASK (15 << 12) #define TXFORMAT_HEIGHT_SHIFT 12 #define TXFORMAT_F5_WIDTH_MASK (15 << 16) #define TXFORMAT_F5_WIDTH_SHIFT 16 #define TXFORMAT_F5_HEIGHT_MASK (15 << 20) #define TXFORMAT_F5_HEIGHT_SHIFT 20 #define TXFORMAT_ST_ROUTE_STQ0 (0 << 24) #define TXFORMAT_ST_ROUTE_MASK (3 << 24) #define TXFORMAT_ST_ROUTE_STQ1 (1 << 24) #define TXFORMAT_ST_ROUTE_STQ2 (2 << 24) #define TXFORMAT_ENDIAN_NO_SWAP (0 << 26) #define TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) #define TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) #define TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) #define TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) #define TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) #define TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) #define TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) #define PP_CUBIC_FACES_0 0x1d24 #define PP_CUBIC_FACES_1 0x1d28 #define PP_CUBIC_FACES_2 0x1d2c #define FACE_WIDTH_1_SHIFT 0 #define FACE_HEIGHT_1_SHIFT 4 #define FACE_WIDTH_1_MASK (0xf << 0) #define FACE_HEIGHT_1_MASK (0xf << 4) #define FACE_WIDTH_2_SHIFT 8 #define FACE_HEIGHT_2_SHIFT 12 #define FACE_WIDTH_2_MASK (0xf << 8) #define FACE_HEIGHT_2_MASK (0xf << 12) #define FACE_WIDTH_3_SHIFT 16 #define FACE_HEIGHT_3_SHIFT 20 #define FACE_WIDTH_3_MASK (0xf << 16) #define FACE_HEIGHT_3_MASK (0xf << 20) #define FACE_WIDTH_4_SHIFT 24 #define FACE_HEIGHT_4_SHIFT 28 #define FACE_WIDTH_4_MASK (0xf << 24) #define FACE_HEIGHT_4_MASK (0xf << 28) #define PP_TXOFFSET_0 0x1c5c #define PP_TXOFFSET_1 0x1c74 #define PP_TXOFFSET_2 0x1c8c #define TXO_ENDIAN_NO_SWAP (0 << 0) #define TXO_ENDIAN_BYTE_SWAP (1 << 0) #define TXO_ENDIAN_WORD_SWAP (2 << 0) #define TXO_ENDIAN_HALFDW_SWAP (3 << 0) #define TXO_MACRO_LINEAR (0 << 2) #define TXO_MACRO_TILE (1 << 2) #define TXO_MICRO_LINEAR (0 << 3) #define TXO_MICRO_TILE_X2 (1 << 3) #define TXO_MICRO_TILE_OPT (2 << 3) #define TXO_OFFSET_MASK 0xffffffe0 #define TXO_OFFSET_SHIFT 5 #define PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ #define PP_CUBIC_OFFSET_T0_1 0x1dd4 #define PP_CUBIC_OFFSET_T0_2 0x1dd8 #define PP_CUBIC_OFFSET_T0_3 0x1ddc #define PP_CUBIC_OFFSET_T0_4 0x1de0 #define PP_CUBIC_OFFSET_T1_0 0x1e00 #define PP_CUBIC_OFFSET_T1_1 0x1e04 #define PP_CUBIC_OFFSET_T1_2 0x1e08 #define PP_CUBIC_OFFSET_T1_3 0x1e0c #define PP_CUBIC_OFFSET_T1_4 0x1e10 #define PP_CUBIC_OFFSET_T2_0 0x1e14 #define PP_CUBIC_OFFSET_T2_1 0x1e18 #define PP_CUBIC_OFFSET_T2_2 0x1e1c #define PP_CUBIC_OFFSET_T2_3 0x1e20 #define PP_CUBIC_OFFSET_T2_4 0x1e24 #define PP_TEX_SIZE_0 0x1d04 /* NPOT */ #define PP_TEX_SIZE_1 0x1d0c #define PP_TEX_SIZE_2 0x1d14 #define TEX_USIZE_MASK (0x7ff << 0) #define TEX_USIZE_SHIFT 0 #define TEX_VSIZE_MASK (0x7ff << 16) #define TEX_VSIZE_SHIFT 16 #define SIGNED_RGB_MASK (1 << 30) #define SIGNED_RGB_SHIFT 30 #define SIGNED_ALPHA_MASK (1 << 31) #define SIGNED_ALPHA_SHIFT 31 #define PP_TEX_PITCH_0 0x1d08 /* NPOT */ #define PP_TEX_PITCH_1 0x1d10 /* NPOT */ #define PP_TEX_PITCH_2 0x1d18 /* NPOT */ /* note: bits 13-5: 32 byte aligned stride of texture map */ #define PP_TXCBLEND_0 0x1c60 #define PP_TXCBLEND_1 0x1c78 #define PP_TXCBLEND_2 0x1c90 #define COLOR_ARG_A_SHIFT 0 #define COLOR_ARG_A_MASK (0x1f << 0) #define COLOR_ARG_A_ZERO (0 << 0) #define COLOR_ARG_A_CURRENT_COLOR (2 << 0) #define COLOR_ARG_A_CURRENT_ALPHA (3 << 0) #define COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) #define COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) #define COLOR_ARG_A_SPECULAR_COLOR (6 << 0) #define COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) #define COLOR_ARG_A_TFACTOR_COLOR (8 << 0) #define COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) #define COLOR_ARG_A_T0_COLOR (10 << 0) #define COLOR_ARG_A_T0_ALPHA (11 << 0) #define COLOR_ARG_A_T1_COLOR (12 << 0) #define COLOR_ARG_A_T1_ALPHA (13 << 0) #define COLOR_ARG_A_T2_COLOR (14 << 0) #define COLOR_ARG_A_T2_ALPHA (15 << 0) #define COLOR_ARG_A_T3_COLOR (16 << 0) #define COLOR_ARG_A_T3_ALPHA (17 << 0) #define COLOR_ARG_B_SHIFT 5 #define COLOR_ARG_B_MASK (0x1f << 5) #define COLOR_ARG_B_ZERO (0 << 5) #define COLOR_ARG_B_CURRENT_COLOR (2 << 5) #define COLOR_ARG_B_CURRENT_ALPHA (3 << 5) #define COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) #define COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) #define COLOR_ARG_B_SPECULAR_COLOR (6 << 5) #define COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) #define COLOR_ARG_B_TFACTOR_COLOR (8 << 5) #define COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) #define COLOR_ARG_B_T0_COLOR (10 << 5) #define COLOR_ARG_B_T0_ALPHA (11 << 5) #define COLOR_ARG_B_T1_COLOR (12 << 5) #define COLOR_ARG_B_T1_ALPHA (13 << 5) #define COLOR_ARG_B_T2_COLOR (14 << 5) #define COLOR_ARG_B_T2_ALPHA (15 << 5) #define COLOR_ARG_B_T3_COLOR (16 << 5) #define COLOR_ARG_B_T3_ALPHA (17 << 5) #define COLOR_ARG_C_SHIFT 10 #define COLOR_ARG_C_MASK (0x1f << 10) #define COLOR_ARG_C_ZERO (0 << 10) #define COLOR_ARG_C_CURRENT_COLOR (2 << 10) #define COLOR_ARG_C_CURRENT_ALPHA (3 << 10) #define COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) #define COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) #define COLOR_ARG_C_SPECULAR_COLOR (6 << 10) #define COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) #define COLOR_ARG_C_TFACTOR_COLOR (8 << 10) #define COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) #define COLOR_ARG_C_T0_COLOR (10 << 10) #define COLOR_ARG_C_T0_ALPHA (11 << 10) #define COLOR_ARG_C_T1_COLOR (12 << 10) #define COLOR_ARG_C_T1_ALPHA (13 << 10) #define COLOR_ARG_C_T2_COLOR (14 << 10) #define COLOR_ARG_C_T2_ALPHA (15 << 10) #define COLOR_ARG_C_T3_COLOR (16 << 10) #define COLOR_ARG_C_T3_ALPHA (17 << 10) #define COMP_ARG_A (1 << 15) #define COMP_ARG_A_SHIFT 15 #define COMP_ARG_B (1 << 16) #define COMP_ARG_B_SHIFT 16 #define COMP_ARG_C (1 << 17) #define COMP_ARG_C_SHIFT 17 #define BLEND_CTL_MASK (7 << 18) #define BLEND_CTL_ADD (0 << 18) #define BLEND_CTL_SUBTRACT (1 << 18) #define BLEND_CTL_ADDSIGNED (2 << 18) #define BLEND_CTL_BLEND (3 << 18) #define BLEND_CTL_DOT3 (4 << 18) #define SCALE_SHIFT 21 #define SCALE_MASK (3 << 21) #define SCALE_1X (0 << 21) #define SCALE_2X (1 << 21) #define SCALE_4X (2 << 21) #define CLAMP_TX (1 << 23) #define T0_EQ_TCUR (1 << 24) #define T1_EQ_TCUR (1 << 25) #define T2_EQ_TCUR (1 << 26) #define T3_EQ_TCUR (1 << 27) #define COLOR_ARG_MASK 0x1f #define COMP_ARG_SHIFT 15 #define PP_TXABLEND_0 0x1c64 #define PP_TXABLEND_1 0x1c7c #define PP_TXABLEND_2 0x1c94 #define ALPHA_ARG_A_SHIFT 0 #define ALPHA_ARG_A_MASK (0xf << 0) #define ALPHA_ARG_A_ZERO (0 << 0) #define ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) #define ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) #define ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) #define ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) #define ALPHA_ARG_A_T0_ALPHA (5 << 0) #define ALPHA_ARG_A_T1_ALPHA (6 << 0) #define ALPHA_ARG_A_T2_ALPHA (7 << 0) #define ALPHA_ARG_A_T3_ALPHA (8 << 0) #define ALPHA_ARG_B_SHIFT 4 #define ALPHA_ARG_B_MASK (0xf << 4) #define ALPHA_ARG_B_ZERO (0 << 4) #define ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) #define ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) #define ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) #define ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) #define ALPHA_ARG_B_T0_ALPHA (5 << 4) #define ALPHA_ARG_B_T1_ALPHA (6 << 4) #define ALPHA_ARG_B_T2_ALPHA (7 << 4) #define ALPHA_ARG_B_T3_ALPHA (8 << 4) #define ALPHA_ARG_C_SHIFT 8 #define ALPHA_ARG_C_MASK (0xf << 8) #define ALPHA_ARG_C_ZERO (0 << 8) #define ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) #define ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) #define ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) #define ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) #define ALPHA_ARG_C_T0_ALPHA (5 << 8) #define ALPHA_ARG_C_T1_ALPHA (6 << 8) #define ALPHA_ARG_C_T2_ALPHA (7 << 8) #define ALPHA_ARG_C_T3_ALPHA (8 << 8) #define DOT_ALPHA_DONT_REPLICATE (1 << 9) #define ALPHA_ARG_MASK 0xf #define PP_TFACTOR_0 0x1c68 #define PP_TFACTOR_1 0x1c80 #define PP_TFACTOR_2 0x1c98 #define RB3D_BLENDCNTL 0x1c20 #define COMB_FCN_MASK (3 << 12) #define COMB_FCN_ADD_CLAMP (0 << 12) #define COMB_FCN_ADD_NOCLAMP (1 << 12) #define COMB_FCN_SUB_CLAMP (2 << 12) #define COMB_FCN_SUB_NOCLAMP (3 << 12) #define SRC_BLEND_GL_ZERO (32 << 16) #define SRC_BLEND_GL_ONE (33 << 16) #define SRC_BLEND_GL_SRC_COLOR (34 << 16) #define SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) #define SRC_BLEND_GL_DST_COLOR (36 << 16) #define SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) #define SRC_BLEND_GL_SRC_ALPHA (38 << 16) #define SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) #define SRC_BLEND_GL_DST_ALPHA (40 << 16) #define SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) #define SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) #define SRC_BLEND_MASK (63 << 16) #define DST_BLEND_GL_ZERO (32 << 24) #define DST_BLEND_GL_ONE (33 << 24) #define DST_BLEND_GL_SRC_COLOR (34 << 24) #define DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) #define DST_BLEND_GL_DST_COLOR (36 << 24) #define DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) #define DST_BLEND_GL_SRC_ALPHA (38 << 24) #define DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) #define DST_BLEND_GL_DST_ALPHA (40 << 24) #define DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) #define DST_BLEND_MASK (63 << 24) #define RB3D_CNTL 0x1C3C #define ALPHA_BLEND_ENABLE (1 << 0) #define PLANE_MASK_ENABLE (1 << 1) #define DITHER_ENABLE (1 << 2) #define ROUND_ENABLE (1 << 3) #define SCALE_DITHER_ENABLE (1 << 4) #define DITHER_INIT (1 << 5) #define ROP_ENABLE (1 << 6) #define STENCIL_ENABLE (1 << 7) #define Z_ENABLE (1 << 8) #define DEPTH_XZ_OFFEST_ENABLE (1 << 9) #define COLOR_FORMAT_ARGB1555 (3 << 10) #define COLOR_FORMAT_RGB565 (4 << 10) #define COLOR_FORMAT_ARGB8888 (6 << 10) #define COLOR_FORMAT_RGB332 (7 << 10) #define COLOR_FORMAT_Y8 (8 << 10) #define COLOR_FORMAT_RGB8 (9 << 10) #define COLOR_FORMAT_YUV422_VYUY (11 << 10) #define COLOR_FORMAT_YUV422_YVYU (12 << 10) #define COLOR_FORMAT_aYUV444 (14 << 10) #define COLOR_FORMAT_ARGB4444 (15 << 10) #define CLRCMP_FLIP_ENABLE (1 << 14) #define RB3D_COLOROFFSET 0x1c40 #define COLOROFFSET_MASK 0xfffffff0 #define RB3D_COLORPITCH 0x1c48 #define COLORPITCH_MASK 0x000001ff8 #define COLOR_TILE_ENABLE (1 << 16) #define COLOR_MICROTILE_ENABLE (1 << 17) #define COLOR_ENDIAN_NO_SWAP (0 << 18) #define COLOR_ENDIAN_WORD_SWAP (1 << 18) #define COLOR_ENDIAN_DWORD_SWAP (2 << 18) #define RB3D_DEPTHOFFSET 0x1c24 #define RB3D_DEPTHPITCH 0x1c28 #define DEPTHPITCH_MASK 0x00001ff8 #define DEPTH_ENDIAN_NO_SWAP (0 << 18) #define DEPTH_ENDIAN_WORD_SWAP (1 << 18) #define DEPTH_ENDIAN_DWORD_SWAP (2 << 18) #define RB3D_PLANEMASK 0x1d84 #define RB3D_ROPCNTL 0x1d80 #define ROP_MASK (15 << 8) #define ROP_CLEAR (0 << 8) #define ROP_NOR (1 << 8) #define ROP_AND_INVERTED (2 << 8) #define ROP_COPY_INVERTED (3 << 8) #define ROP_AND_REVERSE (4 << 8) #define ROP_INVERT (5 << 8) #define ROP_XOR (6 << 8) #define ROP_NAND (7 << 8) #define ROP_AND (8 << 8) #define ROP_EQUIV (9 << 8) #define ROP_NOOP (10 << 8) #define ROP_OR_INVERTED (11 << 8) #define ROP_COPY (12 << 8) #define ROP_OR_REVERSE (13 << 8) #define ROP_OR (14 << 8) #define ROP_SET (15 << 8) #define RB3D_STENCILREFMASK 0x1d7c #define STENCIL_REF_SHIFT 0 #define STENCIL_REF_MASK (0xff << 0) #define STENCIL_MASK_SHIFT 16 #define STENCIL_VALUE_MASK (0xff << 16) #define STENCIL_WRITEMASK_SHIFT 24 #define STENCIL_WRITE_MASK (0xff << 24) #define RB3D_ZSTENCILCNTL 0x1c2c #define DEPTH_FORMAT_MASK (0xf << 0) #define DEPTH_FORMAT_16BIT_INT_Z (0 << 0) #define DEPTH_FORMAT_24BIT_INT_Z (2 << 0) #define DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) #define DEPTH_FORMAT_32BIT_INT_Z (4 << 0) #define DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) #define DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) #define DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) #define DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) #define Z_TEST_NEVER (0 << 4) #define Z_TEST_LESS (1 << 4) #define Z_TEST_LEQUAL (2 << 4) #define Z_TEST_EQUAL (3 << 4) #define Z_TEST_GEQUAL (4 << 4) #define Z_TEST_GREATER (5 << 4) #define Z_TEST_NEQUAL (6 << 4) #define Z_TEST_ALWAYS (7 << 4) #define Z_TEST_MASK (7 << 4) #define STENCIL_TEST_NEVER (0 << 12) #define STENCIL_TEST_LESS (1 << 12) #define STENCIL_TEST_LEQUAL (2 << 12) #define STENCIL_TEST_EQUAL (3 << 12) #define STENCIL_TEST_GEQUAL (4 << 12) #define STENCIL_TEST_GREATER (5 << 12) #define STENCIL_TEST_NEQUAL (6 << 12) #define STENCIL_TEST_ALWAYS (7 << 12) #define STENCIL_TEST_MASK (0x7 << 12) #define STENCIL_FAIL_KEEP (0 << 16) #define STENCIL_FAIL_ZERO (1 << 16) #define STENCIL_FAIL_REPLACE (2 << 16) #define STENCIL_FAIL_INC (3 << 16) #define STENCIL_FAIL_DEC (4 << 16) #define STENCIL_FAIL_INVERT (5 << 16) #define STENCIL_FAIL_MASK (0x7 << 16) #define STENCIL_ZPASS_KEEP (0 << 20) #define STENCIL_ZPASS_ZERO (1 << 20) #define STENCIL_ZPASS_REPLACE (2 << 20) #define STENCIL_ZPASS_INC (3 << 20) #define STENCIL_ZPASS_DEC (4 << 20) #define STENCIL_ZPASS_INVERT (5 << 20) #define STENCIL_ZPASS_MASK (0x7 << 20) #define STENCIL_ZFAIL_KEEP (0 << 24) #define STENCIL_ZFAIL_ZERO (1 << 24) #define STENCIL_ZFAIL_REPLACE (2 << 24) #define STENCIL_ZFAIL_INC (3 << 24) #define STENCIL_ZFAIL_DEC (4 << 24) #define STENCIL_ZFAIL_INVERT (5 << 24) #define STENCIL_ZFAIL_MASK (0x7 << 24) #define Z_COMPRESSION_ENABLE (1 << 28) #define FORCE_Z_DIRTY (1 << 29) #define Z_WRITE_ENABLE (1 << 30) #define RE_LINE_PATTERN 0x1cd0 #define LINE_PATTERN_MASK 0x0000ffff #define LINE_REPEAT_COUNT_SHIFT 16 #define LINE_PATTERN_START_SHIFT 24 #define LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) #define LINE_PATTERN_BIG_BIT_ORDER (1 << 28) #define LINE_PATTERN_AUTO_RESET (1 << 29) #define RE_LINE_STATE 0x1cd4 #define LINE_CURRENT_PTR_SHIFT 0 #define LINE_CURRENT_COUNT_SHIFT 8 #define RE_MISC 0x26c4 #define STIPPLE_COORD_MASK 0x1f #define STIPPLE_X_OFFSET_SHIFT 0 #define STIPPLE_X_OFFSET_MASK (0x1f << 0) #define STIPPLE_Y_OFFSET_SHIFT 8 #define STIPPLE_Y_OFFSET_MASK (0x1f << 8) #define STIPPLE_LITTLE_BIT_ORDER (0 << 16) #define STIPPLE_BIG_BIT_ORDER (1 << 16) #define RE_SOLID_COLOR 0x1c1c #define RE_TOP_LEFT 0x26c0 #define RE_LEFT_SHIFT 0 #define RE_TOP_SHIFT 16 #define RE_WIDTH_HEIGHT 0x1c44 #define RE_WIDTH_SHIFT 0 #define RE_HEIGHT_SHIFT 16 #define SE_CNTL 0x1c4c #define FFACE_CULL_CW (0 << 0) #define FFACE_CULL_CCW (1 << 0) #define FFACE_CULL_DIR_MASK (1 << 0) #define BFACE_CULL (0 << 1) #define BFACE_SOLID (3 << 1) #define FFACE_CULL (0 << 3) #define FFACE_SOLID (3 << 3) #define FFACE_CULL_MASK (3 << 3) #define BADVTX_CULL_DISABLE (1 << 5) #define FLAT_SHADE_VTX_0 (0 << 6) #define FLAT_SHADE_VTX_1 (1 << 6) #define FLAT_SHADE_VTX_2 (2 << 6) #define FLAT_SHADE_VTX_LAST (3 << 6) #define DIFFUSE_SHADE_SOLID (0 << 8) #define DIFFUSE_SHADE_FLAT (1 << 8) #define DIFFUSE_SHADE_GOURAUD (2 << 8) #define DIFFUSE_SHADE_MASK (3 << 8) #define ALPHA_SHADE_SOLID (0 << 10) #define ALPHA_SHADE_FLAT (1 << 10) #define ALPHA_SHADE_GOURAUD (2 << 10) #define ALPHA_SHADE_MASK (3 << 10) #define SPECULAR_SHADE_SOLID (0 << 12) #define SPECULAR_SHADE_FLAT (1 << 12) #define SPECULAR_SHADE_GOURAUD (2 << 12) #define SPECULAR_SHADE_MASK (3 << 12) #define FOG_SHADE_SOLID (0 << 14) #define FOG_SHADE_FLAT (1 << 14) #define FOG_SHADE_GOURAUD (2 << 14) #define FOG_SHADE_MASK (3 << 14) #define ZBIAS_ENABLE_POINT (1 << 16) #define ZBIAS_ENABLE_LINE (1 << 17) #define ZBIAS_ENABLE_TRI (1 << 18) #define WIDELINE_ENABLE (1 << 20) #define VPORT_XY_XFORM_ENABLE (1 << 24) #define VPORT_Z_XFORM_ENABLE (1 << 25) #define VTX_PIX_CENTER_D3D (0 << 27) #define VTX_PIX_CENTER_OGL (1 << 27) #define ROUND_MODE_TRUNC (0 << 28) #define ROUND_MODE_ROUND (1 << 28) #define ROUND_MODE_ROUND_EVEN (2 << 28) #define ROUND_MODE_ROUND_ODD (3 << 28) #define ROUND_PREC_16TH_PIX (0 << 30) #define ROUND_PREC_8TH_PIX (1 << 30) #define ROUND_PREC_4TH_PIX (2 << 30) #define ROUND_PREC_HALF_PIX (3 << 30) #define R200_RE_CNTL 0x1c50 #define R200_STIPPLE_ENABLE 0x1 #define R200_SCISSOR_ENABLE 0x2 #define R200_PATTERN_ENABLE 0x4 #define R200_PERSPECTIVE_ENABLE 0x8 #define R200_POINT_SMOOTH 0x20 #define R200_VTX_STQ0_D3D 0x00010000 #define R200_VTX_STQ1_D3D 0x00040000 #define R200_VTX_STQ2_D3D 0x00100000 #define R200_VTX_STQ3_D3D 0x00400000 #define R200_VTX_STQ4_D3D 0x01000000 #define R200_VTX_STQ5_D3D 0x04000000 #define SE_CNTL_STATUS 0x2140 #define VC_NO_SWAP (0 << 0) #define VC_16BIT_SWAP (1 << 0) #define VC_32BIT_SWAP (2 << 0) #define VC_HALF_DWORD_SWAP (3 << 0) #define TCL_BYPASS (1 << 8) #define SE_COORD_FMT 0x1c50 #define VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) #define VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) #define VTX_ST0_NONPARAMETRIC (1 << 8) #define VTX_ST1_NONPARAMETRIC (1 << 9) #define VTX_ST2_NONPARAMETRIC (1 << 10) #define VTX_ST3_NONPARAMETRIC (1 << 11) #define VTX_W0_NORMALIZE (1 << 12) #define VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) #define VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) #define VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) #define VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) #define VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) #define TEX1_W_ROUTING_USE_W0 (0 << 26) #define TEX1_W_ROUTING_USE_Q1 (1 << 26) #define SE_LINE_WIDTH 0x1db8 #define SE_TCL_LIGHT_MODEL_CTL 0x226c #define LIGHTING_ENABLE (1 << 0) #define LIGHT_IN_MODELSPACE (1 << 1) #define LOCAL_VIEWER (1 << 2) #define NORMALIZE_NORMALS (1 << 3) #define RESCALE_NORMALS (1 << 4) #define SPECULAR_LIGHTS (1 << 5) #define DIFFUSE_SPECULAR_COMBINE (1 << 6) #define LIGHT_ALPHA (1 << 7) #define LOCAL_LIGHT_VEC_GL (1 << 8) #define LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) #define LM_SOURCE_STATE_PREMULT 0 #define LM_SOURCE_STATE_MULT 1 #define LM_SOURCE_VERTEX_DIFFUSE 2 #define LM_SOURCE_VERTEX_SPECULAR 3 #define EMISSIVE_SOURCE_SHIFT 16 #define AMBIENT_SOURCE_SHIFT 18 #define DIFFUSE_SOURCE_SHIFT 20 #define SPECULAR_SOURCE_SHIFT 22 #define SE_TCL_MATERIAL_AMBIENT_RED 0x2220 #define SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 #define SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 #define SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c #define SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 #define SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 #define SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 #define SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c #define SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 #define SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 #define SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 #define SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c #define SE_TCL_MATERIAL_SPECULAR_RED 0x2240 #define SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 #define SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 #define SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c #define SE_TCL_MATRIX_SELECT_0 0x225c #define MODELVIEW_0_SHIFT 0 #define MODELVIEW_1_SHIFT 4 #define MODELVIEW_2_SHIFT 8 #define MODELVIEW_3_SHIFT 12 #define IT_MODELVIEW_0_SHIFT 16 #define IT_MODELVIEW_1_SHIFT 20 #define IT_MODELVIEW_2_SHIFT 24 #define IT_MODELVIEW_3_SHIFT 28 #define SE_TCL_MATRIX_SELECT_1 0x2260 #define MODELPROJECT_0_SHIFT 0 #define MODELPROJECT_1_SHIFT 4 #define MODELPROJECT_2_SHIFT 8 #define MODELPROJECT_3_SHIFT 12 #define TEXMAT_0_SHIFT 16 #define TEXMAT_1_SHIFT 20 #define TEXMAT_2_SHIFT 24 #define TEXMAT_3_SHIFT 28 #define SE_TCL_OUTPUT_VTX_FMT 0x2254 #define TCL_VTX_W0 (1 << 0) #define TCL_VTX_FP_DIFFUSE (1 << 1) #define TCL_VTX_FP_ALPHA (1 << 2) #define TCL_VTX_PK_DIFFUSE (1 << 3) #define TCL_VTX_FP_SPEC (1 << 4) #define TCL_VTX_FP_FOG (1 << 5) #define TCL_VTX_PK_SPEC (1 << 6) #define TCL_VTX_ST0 (1 << 7) #define TCL_VTX_ST1 (1 << 8) #define TCL_VTX_Q1 (1 << 9) #define TCL_VTX_ST2 (1 << 10) #define TCL_VTX_Q2 (1 << 11) #define TCL_VTX_ST3 (1 << 12) #define TCL_VTX_Q3 (1 << 13) #define TCL_VTX_Q0 (1 << 14) #define TCL_VTX_WEIGHT_COUNT_SHIFT 15 #define TCL_VTX_NORM0 (1 << 18) #define TCL_VTX_XY1 (1 << 27) #define TCL_VTX_Z1 (1 << 28) #define TCL_VTX_W1 (1 << 29) #define TCL_VTX_NORM1 (1 << 30) #define TCL_VTX_Z0 (1 << 31) #define SE_TCL_OUTPUT_VTX_SEL 0x2258 #define TCL_COMPUTE_XYZW (1 << 0) #define TCL_COMPUTE_DIFFUSE (1 << 1) #define TCL_COMPUTE_SPECULAR (1 << 2) #define TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) #define TCL_FORCE_INORDER_PROC (1 << 4) #define TCL_TEX_INPUT_TEX_0 0 #define TCL_TEX_INPUT_TEX_1 1 #define TCL_TEX_INPUT_TEX_2 2 #define TCL_TEX_INPUT_TEX_3 3 #define TCL_TEX_COMPUTED_TEX_0 8 #define TCL_TEX_COMPUTED_TEX_1 9 #define TCL_TEX_COMPUTED_TEX_2 10 #define TCL_TEX_COMPUTED_TEX_3 11 #define TCL_TEX_0_OUTPUT_SHIFT 16 #define TCL_TEX_1_OUTPUT_SHIFT 20 #define TCL_TEX_2_OUTPUT_SHIFT 24 #define TCL_TEX_3_OUTPUT_SHIFT 28 #define SE_TCL_PER_LIGHT_CTL_0 0x2270 #define LIGHT_0_ENABLE (1 << 0) #define LIGHT_0_ENABLE_AMBIENT (1 << 1) #define LIGHT_0_ENABLE_SPECULAR (1 << 2) #define LIGHT_0_IS_LOCAL (1 << 3) #define LIGHT_0_IS_SPOT (1 << 4) #define LIGHT_0_DUAL_CONE (1 << 5) #define LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) #define LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) #define LIGHT_0_SHIFT 0 #define LIGHT_1_ENABLE (1 << 16) #define LIGHT_1_ENABLE_AMBIENT (1 << 17) #define LIGHT_1_ENABLE_SPECULAR (1 << 18) #define LIGHT_1_IS_LOCAL (1 << 19) #define LIGHT_1_IS_SPOT (1 << 20) #define LIGHT_1_DUAL_CONE (1 << 21) #define LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) #define LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) #define LIGHT_1_SHIFT 16 #define SE_TCL_PER_LIGHT_CTL_1 0x2274 #define LIGHT_2_SHIFT 0 #define LIGHT_3_SHIFT 16 #define SE_TCL_PER_LIGHT_CTL_2 0x2278 #define LIGHT_4_SHIFT 0 #define LIGHT_5_SHIFT 16 #define SE_TCL_PER_LIGHT_CTL_3 0x227c #define LIGHT_6_SHIFT 0 #define LIGHT_7_SHIFT 16 #define SE_TCL_SHININESS 0x2250 #define SE_TCL_TEXTURE_PROC_CTL 0x2268 #define TEXGEN_TEXMAT_0_ENABLE (1 << 0) #define TEXGEN_TEXMAT_1_ENABLE (1 << 1) #define TEXGEN_TEXMAT_2_ENABLE (1 << 2) #define TEXGEN_TEXMAT_3_ENABLE (1 << 3) #define TEXMAT_0_ENABLE (1 << 4) #define TEXMAT_1_ENABLE (1 << 5) #define TEXMAT_2_ENABLE (1 << 6) #define TEXMAT_3_ENABLE (1 << 7) #define TEXGEN_INPUT_MASK 0xf #define TEXGEN_INPUT_TEXCOORD_0 0 #define TEXGEN_INPUT_TEXCOORD_1 1 #define TEXGEN_INPUT_TEXCOORD_2 2 #define TEXGEN_INPUT_TEXCOORD_3 3 #define TEXGEN_INPUT_OBJ 4 #define TEXGEN_INPUT_EYE 5 #define TEXGEN_INPUT_EYE_NORMAL 6 #define TEXGEN_INPUT_EYE_REFLECT 7 #define TEXGEN_INPUT_EYE_NORMALIZED 8 #define TEXGEN_0_INPUT_SHIFT 16 #define TEXGEN_1_INPUT_SHIFT 20 #define TEXGEN_2_INPUT_SHIFT 24 #define TEXGEN_3_INPUT_SHIFT 28 #define SE_TCL_UCP_VERT_BLEND_CTL 0x2264 #define UCP_IN_CLIP_SPACE (1 << 0) #define UCP_IN_MODEL_SPACE (1 << 1) #define UCP_ENABLE_0 (1 << 2) #define UCP_ENABLE_1 (1 << 3) #define UCP_ENABLE_2 (1 << 4) #define UCP_ENABLE_3 (1 << 5) #define UCP_ENABLE_4 (1 << 6) #define UCP_ENABLE_5 (1 << 7) #define TCL_FOG_MASK (3 << 8) #define TCL_FOG_DISABLE (0 << 8) #define TCL_FOG_EXP (1 << 8) #define TCL_FOG_EXP2 (2 << 8) #define TCL_FOG_LINEAR (3 << 8) #define RNG_BASED_FOG (1 << 10) #define LIGHT_TWOSIDE (1 << 11) #define BLEND_OP_COUNT_MASK (7 << 12) #define BLEND_OP_COUNT_SHIFT 12 #define POSITION_BLEND_OP_ENABLE (1 << 16) #define NORMAL_BLEND_OP_ENABLE (1 << 17) #define VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) #define VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) #define VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) #define VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) #define VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) #define VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) #define VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) #define VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) #define VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) #define CULL_FRONT_IS_CW (0 << 28) #define CULL_FRONT_IS_CCW (1 << 28) #define CULL_FRONT (1 << 29) #define CULL_BACK (1 << 30) #define FORCE_W_TO_ONE (1 << 31) #define SE_VPORT_XSCALE 0x1d98 #define SE_VPORT_XOFFSET 0x1d9c #define SE_VPORT_YSCALE 0x1da0 #define SE_VPORT_YOFFSET 0x1da4 #define SE_VPORT_ZSCALE 0x1da8 #define SE_VPORT_ZOFFSET 0x1dac #define SE_ZBIAS_FACTOR 0x1db0 #define SE_ZBIAS_CONSTANT 0x1db4 #define SE_VTX_FMT 0x2080 #define SE_VTX_FMT_XY 0x00000000 #define SE_VTX_FMT_W0 0x00000001 #define SE_VTX_FMT_FPCOLOR 0x00000002 #define SE_VTX_FMT_FPALPHA 0x00000004 #define SE_VTX_FMT_PKCOLOR 0x00000008 #define SE_VTX_FMT_FPSPEC 0x00000010 #define SE_VTX_FMT_FPFOG 0x00000020 #define SE_VTX_FMT_PKSPEC 0x00000040 #define SE_VTX_FMT_ST0 0x00000080 #define SE_VTX_FMT_ST1 0x00000100 #define SE_VTX_FMT_Q1 0x00000200 #define SE_VTX_FMT_ST2 0x00000400 #define SE_VTX_FMT_Q2 0x00000800 #define SE_VTX_FMT_ST3 0x00001000 #define SE_VTX_FMT_Q3 0x00002000 #define SE_VTX_FMT_Q0 0x00004000 #define SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 #define SE_VTX_FMT_N0 0x00040000 #define SE_VTX_FMT_XY1 0x08000000 #define SE_VTX_FMT_Z1 0x10000000 #define SE_VTX_FMT_W1 0x20000000 #define SE_VTX_FMT_N1 0x40000000 #define SE_VTX_FMT_Z 0x80000000 #define SE_VF_CNTL 0x2084 #define VF_PRIM_TYPE_POINT_LIST 1 #define VF_PRIM_TYPE_LINE_LIST 2 #define VF_PRIM_TYPE_LINE_STRIP 3 #define VF_PRIM_TYPE_TRIANGLE_LIST 4 #define VF_PRIM_TYPE_TRIANGLE_FAN 5 #define VF_PRIM_TYPE_TRIANGLE_STRIP 6 #define VF_PRIM_TYPE_TRIANGLE_FLAG 7 #define VF_PRIM_TYPE_RECTANGLE_LIST 8 #define VF_PRIM_TYPE_POINT_LIST_3 9 #define VF_PRIM_TYPE_LINE_LIST_3 10 #define VF_PRIM_TYPE_SPIRIT_LIST 11 #define VF_PRIM_TYPE_LINE_LOOP 12 #define VF_PRIM_TYPE_QUAD_LIST 13 #define VF_PRIM_TYPE_QUAD_STRIP 14 #define VF_PRIM_TYPE_POLYGON 15 #define VF_PRIM_WALK_STATE (0<<4) #define VF_PRIM_WALK_INDEX (1<<4) #define VF_PRIM_WALK_LIST (2<<4) #define VF_PRIM_WALK_DATA (3<<4) #define VF_COLOR_ORDER_RGBA (1<<6) #define VF_RADEON_MODE (1<<8) #define VF_TCL_OUTPUT_CTL_ENA (1<<9) #define VF_PROG_STREAM_ENA (1<<10) #define VF_INDEX_SIZE_SHIFT 11 #define VF_NUM_VERTICES_SHIFT 16 #define SE_PORT_DATA0 0x2000 #define R200_SE_VAP_CNTL 0x2080 #define R200_VAP_TCL_ENABLE 0x00000001 #define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 #define R200_VAP_FORCE_W_TO_ONE 0x00010000 #define R200_VAP_D3D_TEX_DEFAULT 0x00020000 #define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 #define R200_VAP_VF_MAX_VTX_NUM (9 << 18) #define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 #define R200_VF_MAX_VTX_INDX 0x210c #define R200_VF_MIN_VTX_INDX 0x2110 #define R200_SE_VTE_CNTL 0x20b0 #define R200_VPORT_X_SCALE_ENA 0x00000001 #define R200_VPORT_X_OFFSET_ENA 0x00000002 #define R200_VPORT_Y_SCALE_ENA 0x00000004 #define R200_VPORT_Y_OFFSET_ENA 0x00000008 #define R200_VPORT_Z_SCALE_ENA 0x00000010 #define R200_VPORT_Z_OFFSET_ENA 0x00000020 #define R200_VTX_XY_FMT 0x00000100 #define R200_VTX_Z_FMT 0x00000200 #define R200_VTX_W0_FMT 0x00000400 #define R200_VTX_W0_NORMALIZE 0x00000800 #define R200_VTX_ST_DENORMALIZED 0x00001000 #define R200_SE_VAP_CNTL_STATUS 0x2140 #define R200_VC_NO_SWAP (0 << 0) #define R200_VC_16BIT_SWAP (1 << 0) #define R200_VC_32BIT_SWAP (2 << 0) #define R200_PP_TXFILTER_0 0x2c00 #define R200_MAG_FILTER_NEAREST (0 << 0) #define R200_MAG_FILTER_LINEAR (1 << 0) #define R200_MAG_FILTER_MASK (1 << 0) #define R200_MIN_FILTER_NEAREST (0 << 1) #define R200_MIN_FILTER_LINEAR (1 << 1) #define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) #define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) #define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) #define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) #define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) #define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) #define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) #define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) #define R200_MIN_FILTER_MASK (15 << 1) #define R200_MAX_ANISO_1_TO_1 (0 << 5) #define R200_MAX_ANISO_2_TO_1 (1 << 5) #define R200_MAX_ANISO_4_TO_1 (2 << 5) #define R200_MAX_ANISO_8_TO_1 (3 << 5) #define R200_MAX_ANISO_16_TO_1 (4 << 5) #define R200_MAX_ANISO_MASK (7 << 5) #define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) #define R200_MAX_MIP_LEVEL_SHIFT 16 #define R200_YUV_TO_RGB (1 << 20) #define R200_YUV_TEMPERATURE_COOL (0 << 21) #define R200_YUV_TEMPERATURE_HOT (1 << 21) #define R200_YUV_TEMPERATURE_MASK (1 << 21) #define R200_WRAPEN_S (1 << 22) #define R200_CLAMP_S_WRAP (0 << 23) #define R200_CLAMP_S_MIRROR (1 << 23) #define R200_CLAMP_S_CLAMP_LAST (2 << 23) #define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) #define R200_CLAMP_S_CLAMP_BORDER (4 << 23) #define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) #define R200_CLAMP_S_CLAMP_GL (6 << 23) #define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) #define R200_CLAMP_S_MASK (7 << 23) #define R200_WRAPEN_T (1 << 26) #define R200_CLAMP_T_WRAP (0 << 27) #define R200_CLAMP_T_MIRROR (1 << 27) #define R200_CLAMP_T_CLAMP_LAST (2 << 27) #define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) #define R200_CLAMP_T_CLAMP_BORDER (4 << 27) #define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) #define R200_CLAMP_T_CLAMP_GL (6 << 27) #define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) #define R200_CLAMP_T_MASK (7 << 27) #define R200_KILL_LT_ZERO (1 << 30) #define R200_BORDER_MODE_OGL (0 << 31) #define R200_BORDER_MODE_D3D (1 << 31) #define R200_PP_TXFORMAT_0 0x2c04 #define R200_TXFORMAT_I8 (0 << 0) #define R200_TXFORMAT_AI88 (1 << 0) #define R200_TXFORMAT_RGB332 (2 << 0) #define R200_TXFORMAT_ARGB1555 (3 << 0) #define R200_TXFORMAT_RGB565 (4 << 0) #define R200_TXFORMAT_ARGB4444 (5 << 0) #define R200_TXFORMAT_ARGB8888 (6 << 0) #define R200_TXFORMAT_RGBA8888 (7 << 0) #define R200_TXFORMAT_Y8 (8 << 0) #define R200_TXFORMAT_AVYU4444 (9 << 0) #define R200_TXFORMAT_VYUY422 (10 << 0) #define R200_TXFORMAT_YVYU422 (11 << 0) #define R200_TXFORMAT_DXT1 (12 << 0) #define R200_TXFORMAT_DXT23 (14 << 0) #define R200_TXFORMAT_DXT45 (15 << 0) #define R200_TXFORMAT_FORMAT_MASK (31 << 0) #define R200_TXFORMAT_FORMAT_SHIFT 0 #define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) #define R200_TXFORMAT_NON_POWER2 (1 << 7) #define R200_TXFORMAT_WIDTH_MASK (15 << 8) #define R200_TXFORMAT_WIDTH_SHIFT 8 #define R200_TXFORMAT_HEIGHT_MASK (15 << 12) #define R200_TXFORMAT_HEIGHT_SHIFT 12 #define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ #define R200_TXFORMAT_F5_WIDTH_SHIFT 16 #define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) #define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 #define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) #define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) #define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) #define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) #define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) #define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) #define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) #define R200_TXFORMAT_ST_ROUTE_SHIFT 24 #define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) #define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) #define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) #define R200_PP_TXFORMAT_X_0 0x2c08 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ #define R200_PP_TXOFFSET_0 0x2d00 #define R200_TXO_ENDIAN_NO_SWAP (0 << 0) #define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) #define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) #define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) #define R200_TXO_OFFSET_MASK 0xffffffe0 #define R200_TXO_OFFSET_SHIFT 5 #define R200_PP_TFACTOR_0 0x2ee0 #define R200_PP_TFACTOR_1 0x2ee4 #define R200_PP_TFACTOR_2 0x2ee8 #define R200_PP_TFACTOR_3 0x2eec #define R200_PP_TFACTOR_4 0x2ef0 #define R200_PP_TFACTOR_5 0x2ef4 #define R200_PP_TXCBLEND_0 0x2f00 #define R200_TXC_ARG_A_ZERO (0) #define R200_TXC_ARG_A_CURRENT_COLOR (2) #define R200_TXC_ARG_A_CURRENT_ALPHA (3) #define R200_TXC_ARG_A_DIFFUSE_COLOR (4) #define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) #define R200_TXC_ARG_A_SPECULAR_COLOR (6) #define R200_TXC_ARG_A_SPECULAR_ALPHA (7) #define R200_TXC_ARG_A_TFACTOR_COLOR (8) #define R200_TXC_ARG_A_TFACTOR_ALPHA (9) #define R200_TXC_ARG_A_R0_COLOR (10) #define R200_TXC_ARG_A_R0_ALPHA (11) #define R200_TXC_ARG_A_R1_COLOR (12) #define R200_TXC_ARG_A_R1_ALPHA (13) #define R200_TXC_ARG_A_R2_COLOR (14) #define R200_TXC_ARG_A_R2_ALPHA (15) #define R200_TXC_ARG_A_R3_COLOR (16) #define R200_TXC_ARG_A_R3_ALPHA (17) #define R200_TXC_ARG_A_R4_COLOR (18) #define R200_TXC_ARG_A_R4_ALPHA (19) #define R200_TXC_ARG_A_R5_COLOR (20) #define R200_TXC_ARG_A_R5_ALPHA (21) #define R200_TXC_ARG_A_TFACTOR1_COLOR (26) #define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) #define R200_TXC_ARG_A_MASK (31 << 0) #define R200_TXC_ARG_A_SHIFT 0 #define R200_TXC_ARG_B_ZERO (0 << 5) #define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) #define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) #define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) #define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) #define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) #define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) #define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) #define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) #define R200_TXC_ARG_B_R0_COLOR (10 << 5) #define R200_TXC_ARG_B_R0_ALPHA (11 << 5) #define R200_TXC_ARG_B_R1_COLOR (12 << 5) #define R200_TXC_ARG_B_R1_ALPHA (13 << 5) #define R200_TXC_ARG_B_R2_COLOR (14 << 5) #define R200_TXC_ARG_B_R2_ALPHA (15 << 5) #define R200_TXC_ARG_B_R3_COLOR (16 << 5) #define R200_TXC_ARG_B_R3_ALPHA (17 << 5) #define R200_TXC_ARG_B_R4_COLOR (18 << 5) #define R200_TXC_ARG_B_R4_ALPHA (19 << 5) #define R200_TXC_ARG_B_R5_COLOR (20 << 5) #define R200_TXC_ARG_B_R5_ALPHA (21 << 5) #define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) #define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) #define R200_TXC_ARG_B_MASK (31 << 5) #define R200_TXC_ARG_B_SHIFT 5 #define R200_TXC_ARG_C_ZERO (0 << 10) #define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) #define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) #define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) #define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) #define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) #define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) #define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) #define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) #define R200_TXC_ARG_C_R0_COLOR (10 << 10) #define R200_TXC_ARG_C_R0_ALPHA (11 << 10) #define R200_TXC_ARG_C_R1_COLOR (12 << 10) #define R200_TXC_ARG_C_R1_ALPHA (13 << 10) #define R200_TXC_ARG_C_R2_COLOR (14 << 10) #define R200_TXC_ARG_C_R2_ALPHA (15 << 10) #define R200_TXC_ARG_C_R3_COLOR (16 << 10) #define R200_TXC_ARG_C_R3_ALPHA (17 << 10) #define R200_TXC_ARG_C_R4_COLOR (18 << 10) #define R200_TXC_ARG_C_R4_ALPHA (19 << 10) #define R200_TXC_ARG_C_R5_COLOR (20 << 10) #define R200_TXC_ARG_C_R5_ALPHA (21 << 10) #define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) #define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) #define R200_TXC_ARG_C_MASK (31 << 10) #define R200_TXC_ARG_C_SHIFT 10 #define R200_TXC_COMP_ARG_A (1 << 16) #define R200_TXC_COMP_ARG_A_SHIFT (16) #define R200_TXC_BIAS_ARG_A (1 << 17) #define R200_TXC_SCALE_ARG_A (1 << 18) #define R200_TXC_NEG_ARG_A (1 << 19) #define R200_TXC_COMP_ARG_B (1 << 20) #define R200_TXC_COMP_ARG_B_SHIFT (20) #define R200_TXC_BIAS_ARG_B (1 << 21) #define R200_TXC_SCALE_ARG_B (1 << 22) #define R200_TXC_NEG_ARG_B (1 << 23) #define R200_TXC_COMP_ARG_C (1 << 24) #define R200_TXC_COMP_ARG_C_SHIFT (24) #define R200_TXC_BIAS_ARG_C (1 << 25) #define R200_TXC_SCALE_ARG_C (1 << 26) #define R200_TXC_NEG_ARG_C (1 << 27) #define R200_TXC_OP_MADD (0 << 28) #define R200_TXC_OP_CND0 (2 << 28) #define R200_TXC_OP_LERP (3 << 28) #define R200_TXC_OP_DOT3 (4 << 28) #define R200_TXC_OP_DOT4 (5 << 28) #define R200_TXC_OP_CONDITIONAL (6 << 28) #define R200_TXC_OP_DOT2_ADD (7 << 28) #define R200_TXC_OP_MASK (7 << 28) #define R200_PP_TXCBLEND2_0 0x2f04 #define R200_TXC_TFACTOR_SEL_SHIFT 0 #define R200_TXC_TFACTOR_SEL_MASK 0x7 #define R200_TXC_TFACTOR1_SEL_SHIFT 4 #define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) #define R200_TXC_SCALE_SHIFT 8 #define R200_TXC_SCALE_MASK (7 << 8) #define R200_TXC_SCALE_1X (0 << 8) #define R200_TXC_SCALE_2X (1 << 8) #define R200_TXC_SCALE_4X (2 << 8) #define R200_TXC_SCALE_8X (3 << 8) #define R200_TXC_SCALE_INV2 (5 << 8) #define R200_TXC_SCALE_INV4 (6 << 8) #define R200_TXC_SCALE_INV8 (7 << 8) #define R200_TXC_CLAMP_SHIFT 12 #define R200_TXC_CLAMP_MASK (3 << 12) #define R200_TXC_CLAMP_WRAP (0 << 12) #define R200_TXC_CLAMP_0_1 (1 << 12) #define R200_TXC_CLAMP_8_8 (2 << 12) #define R200_TXC_OUTPUT_REG_MASK (7 << 16) #define R200_TXC_OUTPUT_REG_NONE (0 << 16) #define R200_TXC_OUTPUT_REG_R0 (1 << 16) #define R200_TXC_OUTPUT_REG_R1 (2 << 16) #define R200_TXC_OUTPUT_REG_R2 (3 << 16) #define R200_TXC_OUTPUT_REG_R3 (4 << 16) #define R200_TXC_OUTPUT_REG_R4 (5 << 16) #define R200_TXC_OUTPUT_REG_R5 (6 << 16) #define R200_TXC_OUTPUT_MASK_MASK (7 << 20) #define R200_TXC_OUTPUT_MASK_RGB (0 << 20) #define R200_TXC_OUTPUT_MASK_RG (1 << 20) #define R200_TXC_OUTPUT_MASK_RB (2 << 20) #define R200_TXC_OUTPUT_MASK_R (3 << 20) #define R200_TXC_OUTPUT_MASK_GB (4 << 20) #define R200_TXC_OUTPUT_MASK_G (5 << 20) #define R200_TXC_OUTPUT_MASK_B (6 << 20) #define R200_TXC_OUTPUT_MASK_NONE (7 << 20) #define R200_TXC_REPL_NORMAL 0 #define R200_TXC_REPL_RED 1 #define R200_TXC_REPL_GREEN 2 #define R200_TXC_REPL_BLUE 3 #define R200_TXC_REPL_ARG_A_SHIFT 26 #define R200_TXC_REPL_ARG_A_MASK (3 << 26) #define R200_TXC_REPL_ARG_B_SHIFT 28 #define R200_TXC_REPL_ARG_B_MASK (3 << 28) #define R200_TXC_REPL_ARG_C_SHIFT 30 #define R200_TXC_REPL_ARG_C_MASK (3 << 30) #define R200_PP_TXABLEND_0 0x2f08 #define R200_TXA_ARG_A_ZERO (0) #define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ #define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ #define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) #define R200_TXA_ARG_A_DIFFUSE_BLUE (5) #define R200_TXA_ARG_A_SPECULAR_ALPHA (6) #define R200_TXA_ARG_A_SPECULAR_BLUE (7) #define R200_TXA_ARG_A_TFACTOR_ALPHA (8) #define R200_TXA_ARG_A_TFACTOR_BLUE (9) #define R200_TXA_ARG_A_R0_ALPHA (10) #define R200_TXA_ARG_A_R0_BLUE (11) #define R200_TXA_ARG_A_R1_ALPHA (12) #define R200_TXA_ARG_A_R1_BLUE (13) #define R200_TXA_ARG_A_R2_ALPHA (14) #define R200_TXA_ARG_A_R2_BLUE (15) #define R200_TXA_ARG_A_R3_ALPHA (16) #define R200_TXA_ARG_A_R3_BLUE (17) #define R200_TXA_ARG_A_R4_ALPHA (18) #define R200_TXA_ARG_A_R4_BLUE (19) #define R200_TXA_ARG_A_R5_ALPHA (20) #define R200_TXA_ARG_A_R5_BLUE (21) #define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) #define R200_TXA_ARG_A_TFACTOR1_BLUE (27) #define R200_TXA_ARG_A_MASK (31 << 0) #define R200_TXA_ARG_A_SHIFT 0 #define R200_TXA_ARG_B_ZERO (0 << 5) #define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ #define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ #define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) #define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) #define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) #define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) #define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) #define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) #define R200_TXA_ARG_B_R0_ALPHA (10 << 5) #define R200_TXA_ARG_B_R0_BLUE (11 << 5) #define R200_TXA_ARG_B_R1_ALPHA (12 << 5) #define R200_TXA_ARG_B_R1_BLUE (13 << 5) #define R200_TXA_ARG_B_R2_ALPHA (14 << 5) #define R200_TXA_ARG_B_R2_BLUE (15 << 5) #define R200_TXA_ARG_B_R3_ALPHA (16 << 5) #define R200_TXA_ARG_B_R3_BLUE (17 << 5) #define R200_TXA_ARG_B_R4_ALPHA (18 << 5) #define R200_TXA_ARG_B_R4_BLUE (19 << 5) #define R200_TXA_ARG_B_R5_ALPHA (20 << 5) #define R200_TXA_ARG_B_R5_BLUE (21 << 5) #define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) #define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) #define R200_TXA_ARG_B_MASK (31 << 5) #define R200_TXA_ARG_B_SHIFT 5 #define R200_TXA_ARG_C_ZERO (0 << 10) #define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ #define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ #define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) #define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) #define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) #define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) #define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) #define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) #define R200_TXA_ARG_C_R0_ALPHA (10 << 10) #define R200_TXA_ARG_C_R0_BLUE (11 << 10) #define R200_TXA_ARG_C_R1_ALPHA (12 << 10) #define R200_TXA_ARG_C_R1_BLUE (13 << 10) #define R200_TXA_ARG_C_R2_ALPHA (14 << 10) #define R200_TXA_ARG_C_R2_BLUE (15 << 10) #define R200_TXA_ARG_C_R3_ALPHA (16 << 10) #define R200_TXA_ARG_C_R3_BLUE (17 << 10) #define R200_TXA_ARG_C_R4_ALPHA (18 << 10) #define R200_TXA_ARG_C_R4_BLUE (19 << 10) #define R200_TXA_ARG_C_R5_ALPHA (20 << 10) #define R200_TXA_ARG_C_R5_BLUE (21 << 10) #define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) #define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) #define R200_TXA_ARG_C_MASK (31 << 10) #define R200_TXA_ARG_C_SHIFT 10 #define R200_TXA_COMP_ARG_A (1 << 16) #define R200_TXA_COMP_ARG_A_SHIFT (16) #define R200_TXA_BIAS_ARG_A (1 << 17) #define R200_TXA_SCALE_ARG_A (1 << 18) #define R200_TXA_NEG_ARG_A (1 << 19) #define R200_TXA_COMP_ARG_B (1 << 20) #define R200_TXA_COMP_ARG_B_SHIFT (20) #define R200_TXA_BIAS_ARG_B (1 << 21) #define R200_TXA_SCALE_ARG_B (1 << 22) #define R200_TXA_NEG_ARG_B (1 << 23) #define R200_TXA_COMP_ARG_C (1 << 24) #define R200_TXA_COMP_ARG_C_SHIFT (24) #define R200_TXA_BIAS_ARG_C (1 << 25) #define R200_TXA_SCALE_ARG_C (1 << 26) #define R200_TXA_NEG_ARG_C (1 << 27) #define R200_TXA_OP_MADD (0 << 28) #define R200_TXA_OP_CND0 (2 << 28) #define R200_TXA_OP_LERP (3 << 28) #define R200_TXA_OP_CONDITIONAL (6 << 28) #define R200_TXA_OP_MASK (7 << 28) #define R200_PP_TXABLEND2_0 0x2f0c #define R200_TXA_TFACTOR_SEL_SHIFT 0 #define R200_TXA_TFACTOR_SEL_MASK 0x7 #define R200_TXA_TFACTOR1_SEL_SHIFT 4 #define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) #define R200_TXA_SCALE_SHIFT 8 #define R200_TXA_SCALE_MASK (7 << 8) #define R200_TXA_SCALE_1X (0 << 8) #define R200_TXA_SCALE_2X (1 << 8) #define R200_TXA_SCALE_4X (2 << 8) #define R200_TXA_SCALE_8X (3 << 8) #define R200_TXA_SCALE_INV2 (5 << 8) #define R200_TXA_SCALE_INV4 (6 << 8) #define R200_TXA_SCALE_INV8 (7 << 8) #define R200_TXA_CLAMP_SHIFT 12 #define R200_TXA_CLAMP_MASK (3 << 12) #define R200_TXA_CLAMP_WRAP (0 << 12) #define R200_TXA_CLAMP_0_1 (1 << 12) #define R200_TXA_CLAMP_8_8 (2 << 12) #define R200_TXA_OUTPUT_REG_MASK (7 << 16) #define R200_TXA_OUTPUT_REG_NONE (0 << 16) #define R200_TXA_OUTPUT_REG_R0 (1 << 16) #define R200_TXA_OUTPUT_REG_R1 (2 << 16) #define R200_TXA_OUTPUT_REG_R2 (3 << 16) #define R200_TXA_OUTPUT_REG_R3 (4 << 16) #define R200_TXA_OUTPUT_REG_R4 (5 << 16) #define R200_TXA_OUTPUT_REG_R5 (6 << 16) #define R200_TXA_DOT_ALPHA (1 << 20) #define R200_TXA_REPL_NORMAL 0 #define R200_TXA_REPL_RED 1 #define R200_TXA_REPL_GREEN 2 #define R200_TXA_REPL_ARG_A_SHIFT 26 #define R200_TXA_REPL_ARG_A_MASK (3 << 26) #define R200_TXA_REPL_ARG_B_SHIFT 28 #define R200_TXA_REPL_ARG_B_MASK (3 << 28) #define R200_TXA_REPL_ARG_C_SHIFT 30 #define R200_TXA_REPL_ARG_C_MASK (3 << 30) #define R200_SE_VTX_FMT_0 0x2088 #define R200_VTX_XY 0 /* always have xy */ #define R200_VTX_Z0 (1<<0) #define R200_VTX_W0 (1<<1) #define R200_VTX_WEIGHT_COUNT_SHIFT (2) #define R200_VTX_PV_MATRIX_SEL (1<<5) #define R200_VTX_N0 (1<<6) #define R200_VTX_POINT_SIZE (1<<7) #define R200_VTX_DISCRETE_FOG (1<<8) #define R200_VTX_SHININESS_0 (1<<9) #define R200_VTX_SHININESS_1 (1<<10) #define R200_VTX_COLOR_NOT_PRESENT 0 #define R200_VTX_PK_RGBA 1 #define R200_VTX_FP_RGB 2 #define R200_VTX_FP_RGBA 3 #define R200_VTX_COLOR_MASK 3 #define R200_VTX_COLOR_0_SHIFT 11 #define R200_VTX_COLOR_1_SHIFT 13 #define R200_VTX_COLOR_2_SHIFT 15 #define R200_VTX_COLOR_3_SHIFT 17 #define R200_VTX_COLOR_4_SHIFT 19 #define R200_VTX_COLOR_5_SHIFT 21 #define R200_VTX_COLOR_6_SHIFT 23 #define R200_VTX_COLOR_7_SHIFT 25 #define R200_VTX_XY1 (1<<28) #define R200_VTX_Z1 (1<<29) #define R200_VTX_W1 (1<<30) #define R200_VTX_N1 (1<<31) #define R200_SE_VTX_FMT_1 0x208c #define R200_VTX_TEX0_COMP_CNT_SHIFT 0 #define R200_VTX_TEX1_COMP_CNT_SHIFT 3 #define R200_VTX_TEX2_COMP_CNT_SHIFT 6 #define R200_VTX_TEX3_COMP_CNT_SHIFT 9 #define R200_VTX_TEX4_COMP_CNT_SHIFT 12 #define R200_VTX_TEX5_COMP_CNT_SHIFT 15 #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 #define R200_OUTPUT_XYZW (1<<0) #define R200_OUTPUT_COLOR_0 (1<<8) #define R200_OUTPUT_COLOR_1 (1<<9) #define R200_OUTPUT_TEX_0 (1<<16) #define R200_OUTPUT_TEX_1 (1<<17) #define R200_OUTPUT_TEX_2 (1<<18) #define R200_OUTPUT_TEX_3 (1<<19) #define R200_OUTPUT_TEX_4 (1<<20) #define R200_OUTPUT_TEX_5 (1<<21) #define R200_OUTPUT_TEX_MASK (0x3f<<16) #define R200_OUTPUT_DISCRETE_FOG (1<<24) #define R200_OUTPUT_PT_SIZE (1<<25) #define R200_FORCE_INORDER_PROC (1<<31) #define R200_PP_CNTL_X 0x2cc4 #define R200_PP_TXMULTI_CTL_0 0x2c1c #define R200_SE_VTX_STATE_CNTL 0x2180 #define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) /* BUS MASTERING */ #define BM_FRAME_BUF_OFFSET 0xA00 #define BM_SYSTEM_MEM_ADDR 0xA04 #define BM_COMMAND 0xA08 #define BM_INTERRUPT_DIS 0x08000000 #define BM_TRANSFER_DEST_REG 0x10000000 #define BM_FORCE_TO_PCI 0x20000000 #define BM_FRAME_OFFSET_HOLD 0x40000000 #define BM_END_OF_LIST 0x80000000 //#define BM_STATUS 0xA0c // !!!!!! already used #define BM_QUEUE_STATUS 0xA10 #define BM_QUEUE_FREE_STATUS 0xA14 #define BM_CHUNK_0_VAL 0xA18 #define BM_PTR_FORCE_TO_PCI 0x00200000 #define BM_PM4_RD_FORCE_TO_PCI 0x00400000 #define BM_GLOBAL_FORCE_TO_PCI 0x00800000 #define BM_VIP3_NOCHUNK 0x10000000 #define BM_VIP2_NOCHUNK 0x20000000 #define BM_VIP1_NOCHUNK 0x40000000 #define BM_VIP0_NOCHUNK 0x80000000 #define BM_CHUNK_1_VAL 0xA1C #define BM_VIP0_BUF 0xA20 #define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 #define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 #define BM_VIP0_ACTIVE 0xA24 #define BM_VIP1_BUF 0xA30 #define BM_VIP1_ACTIVE 0xA34 #define BM_VIP2_BUF 0xA40 #define BM_VIP2_ACTIVE 0xA44 #define BM_VIP3_BUF 0xA50 #define BM_VIP3_ACTIVE 0xA54 #define BM_VIDCAP_BUF0 0xA60 #define BM_VIDCAP_BUF1 0xA64 #define BM_VIDCAP_BUF2 0xA68 #define BM_VIDCAP_ACTIVE 0xA6c #define BM_GUI 0xA80 /* RAGE THEATER REGISTERS */ #define DMA_VIPH0_COMMAND 0x0A00 #define DMA_VIPH1_COMMAND 0x0A04 #define DMA_VIPH2_COMMAND 0x0A08 #define DMA_VIPH3_COMMAND 0x0A0C #define DMA_VIPH_STATUS 0x0A10 #define DMA_VIPH_CHUNK_0 0x0A18 #define DMA_VIPH_CHUNK_1_VAL 0x0A1C #define DMA_VIP0_TABLE_ADDR 0x0A20 #define DMA_VIPH0_ACTIVE 0x0A24 #define DMA_VIP1_TABLE_ADDR 0x0A30 #define DMA_VIPH1_ACTIVE 0x0A34 #define DMA_VIP2_TABLE_ADDR 0x0A40 #define DMA_VIPH2_ACTIVE 0x0A44 #define DMA_VIP3_TABLE_ADDR 0x0A50 #define DMA_VIPH3_ACTIVE 0x0A54 #define DMA_VIPH_ABORT 0x0A88 #define VIPH_CONTROL 0x0C40 #define VIPH_CH0_DATA 0x0C00 #define VIPH_CH1_DATA 0x0C04 #define VIPH_CH2_DATA 0x0C08 #define VIPH_CH3_DATA 0x0C0C #define VIPH_CH0_ADDR 0x0C10 #define VIPH_CH1_ADDR 0x0C14 #define VIPH_CH2_ADDR 0x0C18 #define VIPH_CH3_ADDR 0x0C1C #define VIPH_CH0_SBCNT 0x0C20 #define VIPH_CH1_SBCNT 0x0C24 #define VIPH_CH2_SBCNT 0x0C28 #define VIPH_CH3_SBCNT 0x0C2C #define VIPH_CH0_ABCNT 0x0C30 #define VIPH_CH1_ABCNT 0x0C34 #define VIPH_CH2_ABCNT 0x0C38 #define VIPH_CH3_ABCNT 0x0C3C #define VIPH_DV_LAT 0x0C44 #define VIPH_BM_CHUNK 0x0C48 #define VIPH_DV_INT 0x0C4C #define VIPH_TIMEOUT_STAT 0x0C50 #define VIPH_REG_DATA 0x0084 #define VIPH_REG_ADDR 0x0080 /* Address Space Rage Theatre Registers (VIP Access) */ #define VIP_VIP_VENDOR_DEVICE_ID 0x0000 #define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 #define VIP_VIP_COMMAND_STATUS 0x0008 #define VIP_VIP_REVISION_ID 0x000c #define VIP_HW_DEBUG 0x0010 #define VIP_SW_SCRATCH 0x0014 #define VIP_I2C_CNTL_0 0x0020 #define VIP_I2C_CNTL_1 0x0024 #define VIP_I2C_DATA 0x0028 #define VIP_INT_CNTL 0x002c #define VIP_INT_CNTL__FB_INT0 0x02000000 #define VIP_INT_CNTL__FB_INT0_CLR 0x02000000 #define VIP_GPIO_INOUT 0x0030 #define VIP_GPIO_CNTL 0x0034 #define VIP_CLKOUT_GPIO_CNTL 0x0038 #define VIP_RIPINTF_PORT_CNTL 0x003c #define VIP_HOSTINTF_PORT_CNTL 0x003c #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008 #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080 #define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100 #define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000 #define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000 #define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000 #define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000 #define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000 #define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000 #define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000 #define VIP_DSP_PLL_CNTL 0x0bc #define VIP_TC_SOURCE 0x300 #define VIP_TC_DESTINATION 0x304 #define VIP_TC_COMMAND 0x308 #define VIP_TC_STATUS 0x030c #define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff #define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000 #define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000 #define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000 #define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000 #define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000 #define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000 #define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000 #define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000 #define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000 #define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000 #define VIP_TC_DOWNLOAD 0x0310 #define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff #define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000 #define VIP_FB_INT 0x0314 #define VIP_FB_INT__INT_7 0x00000080 #define VIP_FB_SCRATCH0 0x0318 #define VIP_FB_SCRATCH1 0x031c #define VIP_ADC_CNTL 0x0400 #define VIP_ADC_DEBUG 0x0404 #define VIP_STANDARD_SELECT 0x0408 #define VIP_THERMO2BIN_STATUS 0x040c #define VIP_COMB_CNTL0 0x0440 #define VIP_COMB_CNTL1 0x0444 #define VIP_COMB_CNTL2 0x0448 #define VIP_COMB_LINE_LENGTH 0x044c #define VIP_NOISE_CNTL0 0x0450 #define VIP_HS_PLINE 0x0480 #define VIP_HS_DTOINC 0x0484 #define VIP_HS_PLLGAIN 0x0488 #define VIP_HS_MINMAXWIDTH 0x048c #define VIP_HS_GENLOCKDELAY 0x0490 #define VIP_HS_WINDOW_LIMIT 0x0494 #define VIP_HS_WINDOW_OC_SPEED 0x0498 #define VIP_HS_PULSE_WIDTH 0x049c #define VIP_HS_PLL_ERROR 0x04a0 #define VIP_HS_PLL_FS_PATH 0x04a4 #define VIP_SG_BLACK_GATE 0x04c0 #define VIP_SG_SYNCTIP_GATE 0x04c4 #define VIP_SG_UVGATE_GATE 0x04c8 #define VIP_LP_AGC_CLAMP_CNTL0 0x0500 #define VIP_LP_AGC_CLAMP_CNTL1 0x0504 #define VIP_LP_BRIGHTNESS 0x0508 #define VIP_LP_CONTRAST 0x050c #define VIP_LP_SLICE_LIMIT 0x0510 #define VIP_LP_WPA_CNTL0 0x0514 #define VIP_LP_WPA_CNTL1 0x0518 #define VIP_LP_BLACK_LEVEL 0x051c #define VIP_LP_SLICE_LEVEL 0x0520 #define VIP_LP_SYNCTIP_LEVEL 0x0524 #define VIP_LP_VERT_LOCKOUT 0x0528 #define VIP_VS_DETECTOR_CNTL 0x0540 #define VIP_VS_BLANKING_CNTL 0x0544 #define VIP_VS_FIELD_ID_CNTL 0x0548 #define VIP_VS_COUNTER_CNTL 0x054c #define VIP_VS_FRAME_TOTAL 0x0550 #define VIP_VS_LINE_COUNT 0x0554 #define VIP_CP_PLL_CNTL0 0x0580 #define VIP_CP_PLL_CNTL1 0x0584 #define VIP_CP_HUE_CNTL 0x0588 #define VIP_CP_BURST_GAIN 0x058c #define VIP_CP_AGC_CNTL 0x0590 #define VIP_CP_ACTIVE_GAIN 0x0594 #define VIP_CP_PLL_STATUS0 0x0598 #define VIP_CP_PLL_STATUS1 0x059c #define VIP_CP_PLL_STATUS2 0x05a0 #define VIP_CP_PLL_STATUS3 0x05a4 #define VIP_CP_PLL_STATUS4 0x05a8 #define VIP_CP_PLL_STATUS5 0x05ac #define VIP_CP_PLL_STATUS6 0x05b0 #define VIP_CP_PLL_STATUS7 0x05b4 #define VIP_CP_DEBUG_FORCE 0x05b8 #define VIP_CP_VERT_LOCKOUT 0x05bc #define VIP_H_ACTIVE_WINDOW 0x05c0 #define VIP_V_ACTIVE_WINDOW 0x05c4 #define VIP_H_VBI_WINDOW 0x05c8 #define VIP_V_VBI_WINDOW 0x05cc #define VIP_VBI_CONTROL 0x05d0 #define VIP_DECODER_DEBUG_CNTL 0x05d4 #define VIP_SINGLE_STEP_DATA 0x05d8 #define VIP_MASTER_CNTL 0x0040 #define VIP_RGB_CNTL 0x0048 #define VIP_CLKOUT_CNTL 0x004c #define VIP_SYNC_CNTL 0x0050 #define VIP_I2C_CNTL 0x0054 #define VIP_HTOTAL 0x0080 #define VIP_HDISP 0x0084 #define VIP_HSIZE 0x0088 #define VIP_HSTART 0x008c #define VIP_HCOUNT 0x0090 #define VIP_VTOTAL 0x0094 #define VIP_VDISP 0x0098 #define VIP_VCOUNT 0x009c #define VIP_VFTOTAL 0x00a0 #define VIP_DFCOUNT 0x00a4 #define VIP_DFRESTART 0x00a8 #define VIP_DHRESTART 0x00ac #define VIP_DVRESTART 0x00b0 #define VIP_SYNC_SIZE 0x00b4 #define VIP_TV_PLL_FINE_CNTL 0x00b8 #define VIP_CRT_PLL_FINE_CNTL 0x00bc #define VIP_TV_PLL_CNTL 0x00c0 #define VIP_CRT_PLL_CNTL 0x00c4 #define VIP_PLL_CNTL0 0x00c8 #define VIP_PLL_TEST_CNTL 0x00cc #define VIP_CLOCK_SEL_CNTL 0x00d0 #define VIP_VIN_PLL_CNTL 0x00d4 #define VIP_VIN_PLL_FINE_CNTL 0x00d8 #define VIP_AUD_PLL_CNTL 0x00e0 #define VIP_AUD_PLL_FINE_CNTL 0x00e4 #define VIP_AUD_CLK_DIVIDERS 0x00e8 #define VIP_AUD_DTO_INCREMENTS 0x00ec #define VIP_L54_PLL_CNTL 0x00f0 #define VIP_L54_PLL_FINE_CNTL 0x00f4 #define VIP_L54_DTO_INCREMENTS 0x00f8 #define VIP_PLL_CNTL1 0x00fc #define VIP_FRAME_LOCK_CNTL 0x0100 #define VIP_SYNC_LOCK_CNTL 0x0104 #define VIP_TVO_SYNC_PAT_ACCUM 0x0108 #define VIP_TVO_SYNC_THRESHOLD 0x010c #define VIP_TVO_SYNC_PAT_EXPECT 0x0110 #define VIP_DELAY_ONE_MAP_A 0x0114 #define VIP_DELAY_ONE_MAP_B 0x0118 #define VIP_DELAY_ZERO_MAP_A 0x011c #define VIP_DELAY_ZERO_MAP_B 0x0120 #define VIP_TVO_DATA_DELAY_A 0x0140 #define VIP_TVO_DATA_DELAY_B 0x0144 #define VIP_HOST_READ_DATA 0x0180 #define VIP_HOST_WRITE_DATA 0x0184 #define VIP_HOST_RD_WT_CNTL 0x0188 #define VIP_VSCALER_CNTL1 0x01c0 #define VIP_TIMING_CNTL 0x01c4 #define VIP_VSCALER_CNTL2 0x01c8 #define VIP_Y_FALL_CNTL 0x01cc #define VIP_Y_RISE_CNTL 0x01d0 #define VIP_Y_SAW_TOOTH_CNTL 0x01d4 #define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 #define VIP_GAIN_LIMIT_SETTINGS 0x01e4 #define VIP_LINEAR_GAIN_SETTINGS 0x01e8 #define VIP_MODULATOR_CNTL1 0x0200 #define VIP_MODULATOR_CNTL2 0x0204 #define VIP_MV_MODE_CNTL 0x0208 #define VIP_MV_STRIPE_CNTL 0x020c #define VIP_MV_LEVEL_CNTL1 0x0210 #define VIP_MV_LEVEL_CNTL2 0x0214 #define VIP_PRE_DAC_MUX_CNTL 0x0240 #define VIP_TV_DAC_CNTL 0x0280 #define VIP_CRC_CNTL 0x02c0 #define VIP_VIDEO_PORT_SIG 0x02c4 #define VIP_VBI_CC_CNTL 0x02c8 #define VIP_VBI_EDS_CNTL 0x02cc #define VIP_VBI_20BIT_CNTL 0x02d0 #define VIP_VBI_DTO_CNTL 0x02d4 #define VIP_VBI_LEVEL_CNTL 0x02d8 #define VIP_UV_ADR 0x0300 #define VIP_MV_STATUS 0x0330 #define VIP_UPSAMP_COEFF0_0 0x0340 #define VIP_UPSAMP_COEFF0_1 0x0344 #define VIP_UPSAMP_COEFF0_2 0x0348 #define VIP_UPSAMP_COEFF1_0 0x034c #define VIP_UPSAMP_COEFF1_1 0x0350 #define VIP_UPSAMP_COEFF1_2 0x0354 #define VIP_UPSAMP_COEFF2_0 0x0358 #define VIP_UPSAMP_COEFF2_1 0x035c #define VIP_UPSAMP_COEFF2_2 0x0360 #define VIP_UPSAMP_COEFF3_0 0x0364 #define VIP_UPSAMP_COEFF3_1 0x0368 #define VIP_UPSAMP_COEFF3_2 0x036c #define VIP_UPSAMP_COEFF4_0 0x0370 #define VIP_UPSAMP_COEFF4_1 0x0374 #define VIP_UPSAMP_COEFF4_2 0x0378 #define VIP_TV_DTO_INCREMENTS 0x0390 #define VIP_CRT_DTO_INCREMENTS 0x0394 #define VIP_VSYNC_DIFF_CNTL 0x03a0 #define VIP_VSYNC_DIFF_LIMITS 0x03a4 #define VIP_VSYNC_DIFF_RD_DATA 0x03a8 #define VIP_SCALER_IN_WINDOW 0x0618 #define VIP_SCALER_OUT_WINDOW 0x061c #define VIP_H_SCALER_CONTROL 0x0600 #define VIP_V_SCALER_CONTROL 0x0604 #define VIP_V_DEINTERLACE_CONTROL 0x0608 #define VIP_VBI_SCALER_CONTROL 0x060c #define VIP_DVS_PORT_CTRL 0x0610 #define VIP_DVS_PORT_READBACK 0x0614 #define VIP_FIFOA_CONFIG 0x0800 #define VIP_FIFOB_CONFIG 0x0804 #define VIP_FIFOC_CONFIG 0x0808 #define VIP_SPDIF_PORT_CNTL 0x080c #define VIP_SPDIF_CHANNEL_STAT 0x0810 #define VIP_SPDIF_AC3_PREAMBLE 0x0814 #define VIP_I2S_TRANSMIT_CNTL 0x0818 #define VIP_I2S_RECEIVE_CNTL 0x081c #define VIP_SPDIF_TX_CNT_REG 0x0820 #define VIP_IIS_TX_CNT_REG 0x0824 /* Status defines */ #define VIP_BUSY 0 #define VIP_IDLE 1 #define VIP_RESET 2 #define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT 0x00000001 #define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK 0x00000001 #define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT 0x00000002 #define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK 0x00000002 #define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT 0x00000004 #define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK 0x00000004 #define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT 0x00000008 #define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK 0x00000008 #define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 #define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 #define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 #define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 #define RT100_ATI_ID 0x4D541002 #define RT200_ATI_ID 0x4D4A1002 /* Register/Field values: */ #define RT_COMP0 0x0 #define RT_COMP1 0x1 #define RT_COMP2 0x2 #define RT_YF_COMP3 0x3 #define RT_YR_COMP3 0x4 #define RT_YCF_COMP4 0x5 #define RT_YCR_COMP4 0x6 /* Video standard defines */ #define RT_NTSC 0x0 #define RT_PAL 0x1 #define RT_SECAM 0x2 #define extNONE 0x0000 #define extNTSC 0x0100 #define extRsvd 0x0200 #define extPAL 0x0300 #define extPAL_M 0x0400 #define extPAL_N 0x0500 #define extSECAM 0x0600 #define extPAL_NCOMB 0x0700 #define extNTSC_J 0x0800 #define extNTSC_443 0x0900 #define extPAL_BGHI 0x0A00 #define extPAL_60 0x0B00 /* these are used in MSP3430 */ #define extPAL_DK1 0x0C00 #define extPAL_AUTO 0x0D00 /* these are used in RT200. Some are defined above */ #define extPAL_B 0x0E00 #define extPAL_D 0x0F00 #define extPAL_G 0x1000 #define extPAL_H 0x1100 #define extPAL_I 0x1200 #define extSECAM_B 0x1300 #define extSECAM_D 0x1400 #define extSECAM_G 0x1500 #define extSECAM_H 0x1600 #define extSECAM_K 0x1700 #define extSECAM_K1 0x1800 #define extSECAM_L 0x1900 #define extSECAM_L1 0x1A00 #define RT_FREF_2700 6 #define RT_FREF_2950 5 #define RT_COMPOSITE 0x0 #define RT_SVIDEO 0x1 #define RT_NORM_SHARPNESS 0x03 #define RT_HIGH_SHARPNESS 0x0F #define RT_HUE_PAL_DEF 0x00 #define RT_DECINTERLACED 0x1 #define RT_DECNONINTERLACED 0x0 #define NTSC_LINES 525 #define PAL_SECAM_LINES 625 #define RT_ASYNC_ENABLE 0x0 #define RT_ASYNC_DISABLE 0x1 #define RT_ASYNC_RESET 0x1 #define RT_VINRST_ACTIVE 0x0 #define RT_VINRST_RESET 0x1 #define RT_L54RST_RESET 0x1 #define RT_REF_CLK 0x0 #define RT_PLL_VIN_CLK 0x1 #define RT_VIN_ASYNC_RST 0x20 #define RT_DVS_ASYNC_RST 0x80 #define RT_ADC_ENABLE 0x0 #define RT_ADC_DISABLE 0x1 #define RT_DVSDIR_IN 0x0 #define RT_DVSDIR_OUT 0x1 #define RT_DVSCLK_HIGH 0x0 #define RT_DVSCLK_LOW 0x1 #define RT_DVSCLK_SEL_8FS 0x0 #define RT_DVSCLK_SEL_27MHZ 0x1 #define RT_DVS_CONTSTREAM 0x1 #define RT_DVS_NONCONTSTREAM 0x0 #define RT_DVSDAT_HIGH 0x0 #define RT_DVSDAT_LOW 0x1 #define RT_ADC_CNTL_DEFAULT 0x03252338 /* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ #define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 /* was 0x09438090 */ #define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 #define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 #define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 #define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ #define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 #define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 #define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 #define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 #define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 /* End of filter settings. */ /* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ #define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 #define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 #define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 #define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 #define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 #define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 #define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 #define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 #define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 #define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 /* End of filter settings. */ /* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ #define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 #define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF #define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ #define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 #define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ #define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 #define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 #define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 #define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 #define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 /* End of filter settings. */ /* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ #define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A #define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A #define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B #define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B #define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A #define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A #define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 #define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 #define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 #define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 /* End of filter settings. */ /* LP_AGC_CLAMP_CNTL0 */ #define RT_NTSCM_SYNCTIP_REF0 0x00000037 #define RT_NTSCM_SYNCTIP_REF1 0x00000029 #define RT_NTSCM_CLAMP_REF 0x0000003B #define RT_NTSCM_PEAKWHITE 0x000000FF #define RT_NTSCM_VBI_PEAKWHITE 0x000000D2 /* was 0xc2 - docs say d2 */ #define RT_NTSCM_WPA_THRESHOLD 0x00000406 #define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 #define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B #define RT_NTSCM_LP_LOCKOUT_START 0x00000206 #define RT_NTSCM_LP_LOCKOUT_END 0x00000021 #define RT_NTSCM_CH_DTO_INC 0x00400000 #define RT_NTSCM_CH_PLL_SGAIN 0x00000001 #define RT_NTSCM_CH_PLL_FGAIN 0x00000002 #define RT_NTSCM_CR_BURST_GAIN 0x0000007A #define RT_NTSCM_CB_BURST_GAIN 0x000000AC #define RT_NTSCM_CH_HEIGHT 0x000000CD #define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 #define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 #define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 #define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 #define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A #define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC #define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 #define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E #define RT_NTSCJ_SYNCTIP_REF0 0x00000004 #define RT_NTSCJ_SYNCTIP_REF1 0x00000012 #define RT_NTSCJ_CLAMP_REF 0x0000003B #define RT_NTSCJ_PEAKWHITE 0x000000CB #define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 #define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 #define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 #define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C #define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 #define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 #define RT_NTSCJ_CR_BURST_GAIN 0x00000071 #define RT_NTSCJ_CB_BURST_GAIN 0x0000009F #define RT_NTSCJ_CH_HEIGHT 0x000000CD #define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 #define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 #define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 #define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 #define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 #define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F #define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 #define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E #define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ #define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ #define RT_PAL_CLAMP_REF 0x0000003B #define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ #define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ #define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ #define RT_PAL_WPA_TRIGGER_LO 0x00000096 #define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 #define RT_PAL_LP_LOCKOUT_START 0x00000263 #define RT_PAL_LP_LOCKOUT_END 0x0000002C #define RT_PAL_CH_DTO_INC 0x00400000 #define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ #define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ #define RT_PAL_CR_BURST_GAIN 0x0000007A #define RT_PAL_CB_BURST_GAIN 0x000000AB #define RT_PAL_CH_HEIGHT 0x0000009C #define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ #define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ #define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ #define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 #define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ #define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ #define RT_PAL_VERT_LOCKOUT_START 0x00000269 #define RT_PAL_VERT_LOCKOUT_END 0x00000012 #define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ #define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ #define RT_SECAM_CLAMP_REF 0x0000003B #define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ #define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ #define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ #define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ #define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 #define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ #define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ #define RT_SECAM_CH_DTO_INC 0x003E7A28 #define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 - Volodya */ #define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ #define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ #define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ #define RT_SECAM_CH_HEIGHT 0x00000066 #define RT_SECAM_CH_KILL_LEVEL 0x00000060 #define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 #define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 #define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 #define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ #define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ #define RT_SECAM_VERT_LOCKOUT_START 0x00000269 #define RT_SECAM_VERT_LOCKOUT_END 0x00000012 #define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ #define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000a #define RT_NTSCM_FIELD_IDLOCATION 0x00000105 #define RT_PAL_FIELD_IDLOCATION 0x00000137 #define RT_NTSCM_H_ACTIVE_START 0x00000070 #define RT_NTSCM_H_ACTIVE_END 0x00000363 #define RT_PAL_H_ACTIVE_START 0x0000009A #define RT_PAL_H_ACTIVE_END 0x00000439 #define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) #define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) #define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ #define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ /* VBI */ #define RT_NTSCM_H_VBI_WIND_START 0x32 /* instead of 0x00000049 - V.D. */ #define RT_NTSCM_H_VBI_WIND_END 0x367 /* instead of 0x00000366 - V.D. */ #define RT_PAL_H_VBI_WIND_START 0x00000084 #define RT_PAL_H_VBI_WIND_END 0x0000041F #define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def #define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def #define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ #define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ #define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ #define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ #define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ #define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA #define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 #define RT_NTSCM_VSYNC_INT_HOLD 0x17 #define RT_PALSEM_VSYNC_INT_HOLD 0x1C #define RT_NTSCM_VS_FIELD_BLANK_START 0x206 #define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ #define RT_FIELD_FLIP_EN 0x4 #define RT_V_FIELD_FLIP_INVERTED 0x2000 #define RT_NTSCM_H_IN_START 0x70 #define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ #define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ #define RT_NTSC_H_ACTIVE_SIZE 744 #define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ #define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ #define RT_NTSCM_V_IN_START (0x23) #define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ #define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ #define RT_NTSCM_V_ACTIVE_SIZE 480 #define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ #define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ #define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D #define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D #define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F #define RT_PALM_WIN_CLOSE_LIMIT 0x4D #define RT_PALN_WIN_CLOSE_LIMIT 0x5F #define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ #define RT_NTSCM_VS_FIELD_BLANK_START 0x206 #define RT_NTSCM_HS_PLL_SGAIN 0x5 #define RT_NTSCM_HS_PLL_FGAIN 0x7 #define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 #define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 #define TV 0x1 #define LINEIN 0x2 #define MUTE 0x3 #define DEC_COMPOSITE 0 #define DEC_SVIDEO 1 #define DEC_TUNER 2 #define DEC_NTSC 0 #define DEC_PAL 1 #define DEC_SECAM 2 #define DEC_NTSC_J 8 #define DEC_SMOOTH 0 #define DEC_SHARP 1 /* RT Register Field Defaults: */ #define fld_tmpReg1_def (unsigned long) 0x00000000 #define fld_tmpReg2_def (unsigned long) 0x00000001 #define fld_tmpReg3_def (unsigned long) 0x00000002 #define fld_LP_CONTRAST_def (unsigned long) 0x0000006e #define fld_LP_BRIGHTNESS_def (unsigned long) 0x00003ff0 #define fld_CP_HUE_CNTL_def (unsigned long) 0x00000000 #define fld_LUMA_FILTER_def (unsigned long) 0x00000001 #define fld_H_SCALE_RATIO_def (unsigned long) 0x00010000 #define fld_H_SHARPNESS_def (unsigned long) 0x00000000 #define fld_V_SCALE_RATIO_def (unsigned long) 0x00000800 #define fld_V_DEINTERLACE_ON_def (unsigned long) 0x00000001 #define fld_V_BYPSS_def (unsigned long) 0x00000000 #define fld_V_DITHER_ON_def (unsigned long) 0x00000001 #define fld_EVENF_OFFSET_def (unsigned long) 0x00000000 #define fld_ODDF_OFFSET_def (unsigned long) 0x00000000 #define fld_INTERLACE_DETECTED_def (unsigned long) 0x00000000 #define fld_VS_LINE_COUNT_def (unsigned long) 0x00000000 #define fld_VS_DETECTED_LINES_def (unsigned long) 0x00000000 #define fld_VS_ITU656_VB_def (unsigned long) 0x00000000 #define fld_VBI_CC_DATA_def (unsigned long) 0x00000000 #define fld_VBI_CC_WT_def (unsigned long) 0x00000000 #define fld_VBI_CC_WT_ACK_def (unsigned long) 0x00000000 #define fld_VBI_CC_HOLD_def (unsigned long) 0x00000000 #define fld_VBI_DECODE_EN_def (unsigned long) 0x00000000 #define fld_VBI_CC_DTO_P_def (unsigned long) 0x00001802 #define fld_VBI_20BIT_DTO_P_def (unsigned long) 0x0000155c #define fld_VBI_CC_LEVEL_def (unsigned long) 0x0000003f #define fld_VBI_20BIT_LEVEL_def (unsigned long) 0x00000059 #define fld_VBI_CLK_RUNIN_GAIN_def (unsigned long) 0x0000010f #define fld_H_VBI_WIND_START_def (unsigned long) 0x00000041 #define fld_H_VBI_WIND_END_def (unsigned long) 0x00000366 #define fld_V_VBI_WIND_START_def (unsigned long) 0x0B /* instead of 0x0D - V.D. */ #define fld_V_VBI_WIND_END_def (unsigned long) 0x24 #define fld_VBI_20BIT_DATA0_def (unsigned long) 0x00000000 #define fld_VBI_20BIT_DATA1_def (unsigned long) 0x00000000 #define fld_VBI_20BIT_WT_def (unsigned long) 0x00000000 #define fld_VBI_20BIT_WT_ACK_def (unsigned long) 0x00000000 #define fld_VBI_20BIT_HOLD_def (unsigned long) 0x00000000 #define fld_VBI_CAPTURE_ENABLE_def (unsigned long) 0x00000000 #define fld_VBI_EDS_DATA_def (unsigned long) 0x00000000 #define fld_VBI_EDS_WT_def (unsigned long) 0x00000000 #define fld_VBI_EDS_WT_ACK_def (unsigned long) 0x00000000 #define fld_VBI_EDS_HOLD_def (unsigned long) 0x00000000 #define fld_VBI_SCALING_RATIO_def (unsigned long) 0x00010000 #define fld_VBI_ALIGNER_ENABLE_def (unsigned long) 0x00000000 #define fld_H_ACTIVE_START_def (unsigned long) 0x00000070 #define fld_H_ACTIVE_END_def (unsigned long) 0x000002f0 #define fld_V_ACTIVE_START_def (unsigned long) ((22-4)*2+1) #define fld_V_ACTIVE_END_def (unsigned long) ((22+240-4)*2+2) #define fld_CH_HEIGHT_def (unsigned long) 0x000000CD #define fld_CH_KILL_LEVEL_def (unsigned long) 0x000000C0 #define fld_CH_AGC_ERROR_LIM_def (unsigned long) 0x00000002 #define fld_CH_AGC_FILTER_EN_def (unsigned long) 0x00000000 #define fld_CH_AGC_LOOP_SPEED_def (unsigned long) 0x00000000 #define fld_HUE_ADJ_def (unsigned long) 0x00000000 #define fld_STANDARD_SEL_def (unsigned long) 0x00000000 #define fld_STANDARD_YC_def (unsigned long) 0x00000000 #define fld_ADC_PDWN_def (unsigned long) 0x00000001 #define fld_INPUT_SELECT_def (unsigned long) 0x00000000 #define fld_ADC_PREFLO_def (unsigned long) 0x00000003 #define fld_H_SYNC_PULSE_WIDTH_def (unsigned long) 0x00000000 #define fld_HS_GENLOCKED_def (unsigned long) 0x00000000 #define fld_HS_SYNC_IN_WIN_def (unsigned long) 0x00000000 #define fld_VIN_ASYNC_RST_def (unsigned long) 0x00000001 #define fld_DVS_ASYNC_RST_def (unsigned long) 0x00000001 /* Vendor IDs: */ #define fld_VIP_VENDOR_ID_def (unsigned long) 0x00001002 #define fld_VIP_DEVICE_ID_def (unsigned long) 0x00004d54 #define fld_VIP_REVISION_ID_def (unsigned long) 0x00000001 /* AGC Delay Register */ #define fld_BLACK_INT_START_def (unsigned long) 0x00000031 #define fld_BLACK_INT_LENGTH_def (unsigned long) 0x0000000f #define fld_UV_INT_START_def (unsigned long) 0x0000003b #define fld_U_INT_LENGTH_def (unsigned long) 0x0000000f #define fld_V_INT_LENGTH_def (unsigned long) 0x0000000f #define fld_CRDR_ACTIVE_GAIN_def (unsigned long) 0x0000007a #define fld_CBDB_ACTIVE_GAIN_def (unsigned long) 0x000000ac #define fld_DVS_DIRECTION_def (unsigned long) 0x00000000 #define fld_DVS_VBI_CARD8_SWAP_def (unsigned long) 0x00000000 #define fld_DVS_CLK_SELECT_def (unsigned long) 0x00000000 #define fld_CONTINUOUS_STREAM_def (unsigned long) 0x00000000 #define fld_DVSOUT_CLK_DRV_def (unsigned long) 0x00000001 #define fld_DVSOUT_DATA_DRV_def (unsigned long) 0x00000001 #define fld_COMB_CNTL0_def (unsigned long) 0x09438090 #define fld_COMB_CNTL1_def (unsigned long) 0x00000010 #define fld_COMB_CNTL2_def (unsigned long) 0x16161010 #define fld_COMB_LENGTH_def (unsigned long) 0x0718038A #define fld_SYNCTIP_REF0_def (unsigned long) 0x00000037 #define fld_SYNCTIP_REF1_def (unsigned long) 0x00000029 #define fld_CLAMP_REF_def (unsigned long) 0x0000003B #define fld_AGC_PEAKWHITE_def (unsigned long) 0x000000FF #define fld_VBI_PEAKWHITE_def (unsigned long) 0x000000D2 #define fld_WPA_THRESHOLD_def (unsigned long) 0x000003B0 #define fld_WPA_TRIGGER_LO_def (unsigned long) 0x000000B4 #define fld_WPA_TRIGGER_HIGH_def (unsigned long) 0x0000021C #define fld_LOCKOUT_START_def (unsigned long) 0x00000206 #define fld_LOCKOUT_END_def (unsigned long) 0x00000021 #define fld_CH_DTO_INC_def (unsigned long) 0x00400000 #define fld_PLL_SGAIN_def (unsigned long) 0x00000001 #define fld_PLL_FGAIN_def (unsigned long) 0x00000002 #define fld_CR_BURST_GAIN_def (unsigned long) 0x0000007a #define fld_CB_BURST_GAIN_def (unsigned long) 0x000000ac #define fld_VERT_LOCKOUT_START_def (unsigned long) 0x00000207 #define fld_VERT_LOCKOUT_END_def (unsigned long) 0x0000000E #define fld_H_IN_WIND_START_def (unsigned long) 0x00000070 #define fld_V_IN_WIND_START_def (unsigned long) 0x00000027 #define fld_H_OUT_WIND_WIDTH_def (unsigned long) 0x000002f4 #define fld_V_OUT_WIND_WIDTH_def (unsigned long) 0x000000f0 #define fld_HS_LINE_TOTAL_def (unsigned long) 0x0000038E #define fld_MIN_PULSE_WIDTH_def (unsigned long) 0x0000002F #define fld_MAX_PULSE_WIDTH_def (unsigned long) 0x00000046 #define fld_WIN_CLOSE_LIMIT_def (unsigned long) 0x0000004D #define fld_WIN_OPEN_LIMIT_def (unsigned long) 0x000001B7 #define fld_VSYNC_INT_TRIGGER_def (unsigned long) 0x000002AA #define fld_VSYNC_INT_HOLD_def (unsigned long) 0x0000001D #define fld_VIN_M0_def (unsigned long) 0x00000039 #define fld_VIN_N0_def (unsigned long) 0x0000014c #define fld_MNFLIP_EN_def (unsigned long) 0x00000000 #define fld_VIN_P_def (unsigned long) 0x00000006 #define fld_REG_CLK_SEL_def (unsigned long) 0x00000000 #define fld_VIN_M1_def (unsigned long) 0x00000000 #define fld_VIN_N1_def (unsigned long) 0x00000000 #define fld_VIN_DRIVER_SEL_def (unsigned long) 0x00000000 #define fld_VIN_MNFLIP_REQ_def (unsigned long) 0x00000000 #define fld_VIN_MNFLIP_DONE_def (unsigned long) 0x00000000 #define fld_TV_LOCK_TO_VIN_def (unsigned long) 0x00000000 #define fld_TV_P_FOR_WINCLK_def (unsigned long) 0x00000004 #define fld_VINRST_def (unsigned long) 0x00000001 #define fld_VIN_CLK_SEL_def (unsigned long) 0x00000000 #define fld_VS_FIELD_BLANK_START_def (unsigned long) 0x00000206 #define fld_VS_FIELD_BLANK_END_def (unsigned long) 0x0000000A /*#define fld_VS_FIELD_IDLOCATION_def (unsigned long) 0x00000105 */ #define fld_VS_FIELD_IDLOCATION_def (unsigned long) 0x00000001 #define fld_VS_FRAME_TOTAL_def (unsigned long) 0x00000217 #define fld_SYNC_TIP_START_def (unsigned long) 0x00000372 #define fld_SYNC_TIP_LENGTH_def (unsigned long) 0x0000000F #define fld_GAIN_FORCE_DATA_def (unsigned long) 0x00000000 #define fld_GAIN_FORCE_EN_def (unsigned long) 0x00000000 #define fld_I_CLAMP_SEL_def (unsigned long) 0x00000003 #define fld_I_AGC_SEL_def (unsigned long) 0x00000001 #define fld_EXT_CLAMP_CAP_def (unsigned long) 0x00000001 #define fld_EXT_AGC_CAP_def (unsigned long) 0x00000001 #define fld_DECI_DITHER_EN_def (unsigned long) 0x00000001 #define fld_ADC_PREFHI_def (unsigned long) 0x00000000 #define fld_ADC_CH_GAIN_SEL_def (unsigned long) 0x00000001 #define fld_HS_PLL_SGAIN_def (unsigned long) 0x00000003 #define fld_NREn_def (unsigned long) 0x00000000 #define fld_NRGainCntl_def (unsigned long) 0x00000000 #define fld_NRBWTresh_def (unsigned long) 0x00000000 #define fld_NRGCTresh_def (unsigned long) 0x00000000 #define fld_NRCoefDespeclMode_def (unsigned long) 0x00000000 #define fld_GPIO_5_OE_def (unsigned long) 0x00000000 #define fld_GPIO_6_OE_def (unsigned long) 0x00000000 #define fld_GPIO_5_OUT_def (unsigned long) 0x00000000 #define fld_GPIO_6_OUT_def (unsigned long) 0x00000000 /* End of field default values. */ #endif /* _RADEON_H */