27 Commits

Author SHA1 Message Date
Markus Fröschle
d0dedf92a1 add new file 2021-07-17 23:07:54 +02:00
Markus Fröschle
8ad16486ac fix indentation 2021-07-17 23:07:18 +02:00
Markus Fröschle
253ba1aec1 reenable forgotten memory deallocations 2021-07-17 23:06:22 +02:00
Markus Fröschle
da982d1e5c fix remaining tabs 2021-07-17 23:05:18 +02:00
Markus Fröschle
8ca995a9da fix indentation 2021-07-17 23:04:46 +02:00
Markus Fröschle
b7d702e4c8 fix volatile reference 2021-07-17 23:04:14 +02:00
Markus Fröschle
3ececfa405 fix diagnostics 2021-07-17 23:02:15 +02:00
Markus Fröschle
c8cc6c4625 fix diagnostics 2021-07-17 23:01:45 +02:00
Markus Fröschle
56c3604f7c fix ctags generation 2021-07-17 23:00:49 +02:00
Markus Fröschle
39f814cb72 disable XLB arbiter interrupt 2021-01-10 15:05:11 +01:00
Markus Fröschle
89c511f9ec disable PCI interrupts in PCI scan 2021-01-10 15:04:20 +01:00
Markus Fröschle
77d4a9352d clean debug output 2021-01-10 15:03:46 +01:00
Markus Fröschle
fcbcdd1cdb try to adjust polling wait times 2021-01-10 15:02:54 +01:00
Markus Fröschle
8e038efdb9 add m68k-atari-mint include paths to configuration 2021-01-10 13:43:32 +01:00
Markus Fröschle
5319aab544 make sure PCI cards can become bus masters 2021-01-10 12:52:07 +01:00
Markus Fröschle
72011bb875 more verbose diagnostics for USB device scan 2021-01-10 12:51:21 +01:00
Markus Fröschle
f3d4bba977 enable USB device scan 2021-01-10 12:48:21 +01:00
Markus Fröschle
dccd7af14f remove unnecessary comment 2021-01-10 12:47:36 +01:00
Markus Fröschle
d868021f86 fix hanging PCI memory writes 2021-01-08 13:37:10 +01:00
Markus Fröschle
ab430fd97b fix comments regarding ACR register 2021-01-08 13:36:52 +01:00
Markus Fröschle
8bb679071c add flash scripts for m548x-bas (EmuTOS) 2020-08-30 15:06:00 +02:00
Markus Fröschle
95e9b0ca11 change "*.bdm" script files' status bits back to +x 2020-06-27 13:40:39 +02:00
Markus
aba48384a0 improve wording 2020-06-24 08:40:51 +02:00
Markus
bb803e599e fix typos and improve wording 2020-06-24 08:01:39 +02:00
Markus
24b4eae02f correct directory contents info 2020-06-24 07:55:49 +02:00
Markus
2155af8a15 move travis build label to more prominent position (up) 2020-06-24 07:51:15 +02:00
Markus
36052a448e Update README.md 2020-06-23 16:09:54 +02:00
29 changed files with 359 additions and 178 deletions

View File

@@ -1,3 +1,4 @@
// Add predefined macros for your project here. For example:
// #define THE_ANSWER 42
#define MACHINE_FIREBEE
//#define MACHINE_FIREBEE
#define MACHINE_M5484LITE

View File

@@ -1,3 +1,4 @@
.travis.yml
Makefile
dma/dma.c
dma/MCD_dmaApi.c

View File

@@ -4,4 +4,4 @@ tos/pci_mem/include
tos/pci_test/include
tos/vmem_test/include
tos/fpga_test
.
/usr/lib/gcc/m68k-atari-mint/4.6.4/include

View File

@@ -351,7 +351,7 @@ indent: $(CSRCS)
.PHONY: tags
tags:
ctags $(patsubst %,%/*,$(VPATH))
ctags $(patsubst %,%/*[cS],$(VPATH))
.PHONY: printvars
printvars:

View File

@@ -1,3 +1,6 @@
[![Build Status](https://travis-ci.org/firebee-org/BaS_gcc.svg?branch=master)](https://travis-ci.org/firebee-org/BaS_gcc)
# BaS_gcc
**FireBee gcc-based firmware**
@@ -22,21 +25,22 @@ BaS_gcc aims to fully supports native EmuTOS + native FreeMiNT on the FireBee.
- checkout a copy of the BaS_gcc sources to your local machine
- make sure you have a suitable gcc toolchain available. This could be either an m68k-atari-mint toolchain or an m68k-elf gcc toolchain (see switches in the toplevel Makefile).
- type "make". The build should finish without errors
- for the FireBee, you'll find a flashable file (bas.s19) in the firebee directory
- for the m5484lite board files will reside in the m5475evb directory
- type "make". The build should finish without errors (just warnings about code not finished yet)
- for the FireBee, you'll find a flashable file (`bas.s19`) in the `firebee` directory
- for the m5484LITE evaluation board, files are in the `m5484lite` directory
- for the m5475evb board files will reside in the `m5475evb` directory
- for the m54455 FreeScale evaluation board, files (not functional yet) are in the respective directory
- `ram.s19` files are meant for testing. They are suitable for direct download to RAM (instead of flashing them). This saves wear on the flash chips and improves development turnaround
- `basflash.s19` is a proof of concept result. It goes on the SD card and BaS_gcc will load and execute it on boot. This is meant to provide flash upgrade services in future. For now, it only outputs a diagnostic message to the serial terminal
## How to flash:
These files can be flashed with either Didier Méquinon's flasher available from the firebee.org home page or any BDM hardware (urgently recommended as this is the only "parachute" available if something goes wrong during flashing). Personally, I'm using a parallel P&E flash solution that came with my m5484lite board and the BDM tools from here: https://sourceforge.net/projects/bdm/ since they are supported under Linux (my favorite) and also support the TBLCF (another, USB based open source BDM solution). See the firebee.org home page for more information.
**WARNING: with BaS_gcc installed, do not try to flash anything from EmuTOS with Didier's flasher tool if you do not have a BDM pod. This will not work currently and leave you with a bricked Firebee. This is not EmuTOS' fault but a "feature" (rather a missing one) of BaS_gcc that currently does not run from RAM (it could, but this has been disabled for now for the sake of easier debugging). It runs from flash and its (required) interrupt handlers reside there as well. Didier's flasher tool does not disable interrupts while flashing, so you will most likely run into a situation where Didier's flasher tool erased the flash to rewrite it and (innocent) EmuTOS will try to call an interrupt handler that is not there. Unfortunately, there is no way to remedy from this situation other than BDM.**
Note that this does not apply when flashing from FireTOS which is safe (as FireTOS replaces BaS_gcc's interrupt handlers with it's own copy in RAM).
Bottom line: if you want to flash BaS_gcc with Didier's tool, do it from FireTOS ONLY!
Unless you have a BDM device (which I'd personally recommend under all circumstances anyway), that is.
# ALL-CLEAR
The warning I had here before is superfluous. The problem has been fixed with R_0_9_4.
That means you can now savely flash BaS_gcc from EmuTOS (and FireTOS, of course, as this was working fine all the time) using `FLASH_CF.PRG`
## What do I gain using BaS_gcc compared to "original" BaS?
@@ -56,5 +60,3 @@ From a pure user's perspective (mainly using FireTOS, probably): very little (yo
These tools are available for all major platforms (Windows, Linux, Mac OS), and BaS_gcc has been tested to compile fine on all of these, so you are not limited to any specific configurations
- BaS_gcc enables (fast) networking using EmuTOS + FreeMiNT because it provides the ColdFire MDMA (multi channel DMA) and a suitable FEC driver. This way, you have a fully native OpenSource ColdFire environment without any slowdown through m68k emulation. Of course "legacy" (TOS) programs have to be compiled for this environment or can only used with m68k emulation (https://github.com/vinriviere/68kemu , for example), but if you intend to use the FireBee for new development, this is the fastest setup you can get with full access for all sources compilable with open source toolchains. A true OpenSorce environment.
[![Build Status](https://travis-ci.org/firebee-org/BaS_gcc.svg?branch=master)](https://travis-ci.org/firebee-org/BaS_gcc)

1
TODO Normal file
View File

@@ -0,0 +1 @@
- it appears TOS system variables aren't protected (at least the Cookie Jar can be read from user mode)

0
bas_m5484.bdm Normal file → Executable file
View File

0
check.bdm Normal file → Executable file
View File

0
dump.bdm Normal file → Executable file
View File

0
flash_scripts/flash_firebee_bas.bdm Normal file → Executable file
View File

0
flash_scripts/flash_firebee_etos.bdm Normal file → Executable file
View File

0
flash_scripts/flash_firebee_firetos.bdm Normal file → Executable file
View File

0
flash_scripts/flash_firebee_fpga.bdm Normal file → Executable file
View File

12
flash_scripts/flash_m548x_bas.bdm Normal file → Executable file
View File

@@ -77,16 +77,6 @@ erase 0xE0000000 10
erase 0xE0000000 11
erase 0xE0000000 12
erase 0xE0000000 13
#erase 0xE0000000 0x2000
#erase 0xE0000000 0x3000
#erase 0xE0000000 0x4000
#erase 0xE0000000 0x5000
#erase 0xE0000000 0x00006000
#erase 0xE0000000 0x00007000
#erase 0xE0000000 0x00008000
#erase 0xE0000000 0x00009000
#erase 0xE0000000 0x0000a000
#erase 0xE0000000 0x0000b000
#erase-wait 0xe0000000
load -v ../m5484lite/bas.elf
wait

View File

@@ -0,0 +1,7 @@
#!/bin/bash
pushd ../../BaS_gcc
make clean all
popd
time bdmctrl flash_m548x_bas.bdm /dev/tblcf4

0
flash_scripts/flash_m548x_dbug.bdm Normal file → Executable file
View File

21
flash_scripts/flash_m548x_etos.bdm Normal file → Executable file
View File

@@ -5,9 +5,6 @@
open $1
reset
# Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100007
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00001180 4
@@ -34,15 +31,25 @@ write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 10
# use sram as flashlib scratch area
# use system sdram as flashlib scratch area
# flashing EmuTOS with plugin does not work yet (at least not for 64bit hosts)
#flash-plugin 0xFF101000 0xffff flashintelc3.plugin
#flash-plugin 0x1000 0xf000 flash29.plugin
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
flash 0xe0000000
# Erase flash from 0xE0100000 to 0xE01FFFFF (reserved space for EmuTOS on the m5484lite)
# Erase flash from 0xE0600000 to 0xE06FFFFF (reserved space for EmuTOS)
#
# Caution: sector offset numbers need to be the ones from the x16 address range
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
#
# contrary to documentation, it seems we need to erase-wait after each sector
erase 0xe0000000 16
erase 0xe0000000 17
erase 0xe0000000 18
erase 0xe0000000 19
erase 0xe0000000 20
erase 0xe0000000 21
erase 0xe0000000 22
erase 0xe0000000 23
@@ -63,4 +70,4 @@ erase 0xe0000000 37
erase 0xe0000000 38
erase 0xe0000000 39
load ../../emutos/emutos-m548x-bas.elf
load -v emutos-m548x-bas.elf

View File

@@ -0,0 +1,8 @@
#!/bin/bash
pushd ../../emutos
make clean m548x-bas -j
m68k-elf-objcopy --alt-machine-code 4 -Isrec -Oelf32-m68k emutos-m548x-bas.s19 emutos-m548x-bas.elf
mv emutos-m548x-bas.elf ../BaS_gcc/flash_scripts/emutos-m548x-bas.elf
popd
time bdmctrl flash_m548x_etos.bdm /dev/tblcf4

0
flash_scripts/run_m548x_dbug.bdm Normal file → Executable file
View File

View File

@@ -207,8 +207,8 @@ struct usb_device
* Each instance needs its own set of data structures.
*/
uint32_t status;
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];

View File

@@ -27,6 +27,7 @@
#define _USB_DEFS_H_
#define CONFIG_USB_INTERRUPT_POLLING
/* USB constants */
/* Device and/or Interface Class codes */
@@ -226,7 +227,7 @@
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
#define USB_PORT_STAT_SPEED \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001

View File

@@ -271,7 +271,7 @@ static int ehci_reset(void)
if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC) && (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2))
{
dbg("ehci_reset set 48MHz clock\r\n");
pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
pci_write_config_longword(gehci.handle, 0xE4, swpl(0x20L)); // oscillator
wait(5);
}
@@ -607,7 +607,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
status_reg = (uint32_t *) &gehci.hcor->or_portsc[swpw(req->index) - 1];
srclen = 0;
dbg("ehci_submit_root req=%u (%#x), type=%u (%#x), value=%u, index=%u\r\n",
dbg("req=%u (%#x), type=%u (%#x), value=%u, index=%u\r\n",
req->request, req->request, req->requesttype, req->requesttype, swpw(req->value), swpw(req->index));
typeReq = req->request | req->requesttype << 8;
@@ -774,7 +774,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
* caller must wait, then call GetPortStatus
* usb 2.0 specification say 50 ms resets on root
*/
wait(50 * 1000);
wait_ms(50);
portreset |= (1 << swpw(req->index));
}
break;
@@ -827,7 +827,8 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
dbg("Unknown request\r\n");
goto unknown;
}
wait(1 * 1000);
//wait(1000);
wait_ms(2);
len = min3(srclen, swpw(req->length), length);
if (srcptr != NULL && len > 0)
memcpy(buffer, srcptr, len);
@@ -930,6 +931,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
struct pci_rd *pci_rsc_desc;
pci_rsc_desc = pci_get_resource(handle); /* USB EHCI */
if (handle && (ent != NULL))
{
memset(&gehci, 0, sizeof(struct ehci));

View File

@@ -43,23 +43,24 @@
*/
#include "wait.h" /* for wait_ms routines */
#include "wait.h" /* for wait_ms routines */
#include "bas_printf.h"
#include "bas_string.h" /* for memset() */
#include "pci.h"
#include "interrupts.h"
// #define DEBUG
//#define DEBUG
//#define DEBUG_OHCI
#include "debug.h"
#undef OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
#undef OHCI_FILL_TRACE
#include "usb.h"
#include "ohci.h"
#include "util.h" /* for endian conversions */
#include "util.h" /* for endian conversions */
/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
@@ -104,57 +105,57 @@ static inline void writel(uint32_t value, volatile uint32_t *address)
struct pci_device_id ohci_usb_pci_table[] =
{
{
PCI_VENDOR_ID_AL,
PCI_DEVICE_ID_AL_M5237,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* ULI1575 PCI OHCI module ids */
{
PCI_VENDOR_ID_NEC,
PCI_DEVICE_ID_NEC_USB,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* NEC PCI OHCI module ids */
{
PCI_VENDOR_ID_NEC,
PCI_DEVICE_ID_NEC_USB_A,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* NEC PCI OHCI module ids */
{
PCI_VENDOR_ID_PHILIPS,
PCI_DEVICE_ID_PHILIPS_ISP1561,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* Philips 1561 PCI OHCI module ids */
/* Please add supported PCI OHCI controller ids here */
{
0,
0,
0,
0,
0,
0,
0
}
{
PCI_VENDOR_ID_AL,
PCI_DEVICE_ID_AL_M5237,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* ULI1575 PCI OHCI module ids */
{
PCI_VENDOR_ID_NEC,
PCI_DEVICE_ID_NEC_USB,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* NEC PCI OHCI module ids */
{
PCI_VENDOR_ID_NEC,
PCI_DEVICE_ID_NEC_USB_A,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* NEC PCI OHCI module ids */
{
PCI_VENDOR_ID_PHILIPS,
PCI_DEVICE_ID_PHILIPS_ISP1561,
PCI_ANY_ID,
PCI_ANY_ID,
PCI_CLASS_SERIAL_USB_OHCI,
0,
0
}, /* Philips 1561 PCI OHCI module ids */
/* Please add supported PCI OHCI controller ids here */
{
0,
0,
0,
0,
0,
0,
0
}
};
/* global ohci_t */
static ohci_t gohci[10];
int ohci_inited;
static int ohci_inited;
static inline uint32_t roothub_a(volatile ohci_t *ohci) { return readl(&ohci->regs->roothub.a); }
static inline uint32_t roothub_b(volatile ohci_t *ohci) { return readl(&ohci->regs->roothub.b); }
@@ -168,6 +169,137 @@ static void td_submit_job(volatile ohci_t *ohci, struct usb_device *dev, uint32_
volatile urb_priv_t *urb, int interval);
void write_registers(volatile ohci_t *ohci)
{
int32_t reg;
dbg("--------REGISTERS----------\n\r");
readl(&ohci->regs->revision);
readl(&ohci->regs->control);
readl(&ohci->regs->cmdstatus);
readl(&ohci->regs->intrstatus);
readl(&ohci->regs->intrenable);
readl(&ohci->regs->intrdisable);
readl(&ohci->regs->hcca);
readl(&ohci->regs->ed_periodcurrent);
readl(&ohci->regs->ed_controlhead);
readl(&ohci->regs->ed_controlcurrent);
readl(&ohci->regs->ed_bulkhead);
readl(&ohci->regs->ed_bulkcurrent);
readl(&ohci->regs->donehead);
readl(&ohci->regs->fminterval);
readl(&ohci->regs->fmremaining);
readl(&ohci->regs->fmnumber);
readl(&ohci->regs->periodicstart);
readl(&ohci->regs->lsthresh);
readl(&ohci->regs->roothub.a);
readl(&ohci->regs->roothub.b);
readl(&ohci->regs->roothub.status);
readl(&ohci->regs->roothub.portstatus[0]);
dbg("--------REGISTERS W----------\n\r");
reg = readl(&ohci->regs->revision);
dbg("revision:................0x%lx\r\n", reg);
writel(reg, &ohci->regs->revision );
reg = readl(&ohci->regs->control);
dbg("control:.................0x%lx\r\n", reg);
writel(reg, &ohci->regs->control );
reg = readl(&ohci->regs->cmdstatus);
dbg("cmdstatus:...............0x%lx\r\n", reg);
writel(reg, &ohci->regs->cmdstatus);
reg = readl(&ohci->regs->intrstatus);
dbg("intrstatus:..............0x%lx\r\n", reg);
writel(reg, &ohci->regs->intrstatus);
reg = readl(&ohci->regs->intrenable);
dbg("intrenable:..............0x%lx\r\n", reg);
writel(reg, &ohci->regs->intrenable);
reg = readl(&ohci->regs->intrdisable);
dbg("intrdisable:.............0x%lx\r\n", reg);
writel(reg, &ohci->regs->intrdisable);
reg = readl(&ohci->regs->hcca);
dbg("hcca:....................0x%lx\r\n", reg);
writel(reg, &ohci->regs->hcca);
reg = readl(&ohci->regs->ed_periodcurrent);
dbg("periodcurrent:...........0x%lx\r\n", reg);
writel(reg, &ohci->regs->ed_periodcurrent);
reg = readl(&ohci->regs->ed_controlhead);
dbg("ed_controlhead:..........0x%lx\r\n", reg);
writel(reg, &ohci->regs->ed_controlhead);
reg = readl(&ohci->regs->ed_controlcurrent);
dbg("ed_controlcurrent:.......0x%lx\r\n", reg);
writel(reg, &ohci->regs->ed_controlcurrent);
reg = readl(&ohci->regs->ed_bulkhead);
dbg("ed_bulkhead:.............0x%lx\r\n", reg);
writel(reg, &ohci->regs->ed_bulkhead);
reg = readl(&ohci->regs->ed_bulkcurrent);
dbg("ed_bulkcurrent:..........0x%lx\r\n", reg);
writel(reg, &ohci->regs->ed_bulkcurrent);
reg = readl(&ohci->regs->donehead);
dbg("donehead:................0x%lx\r\n", reg);
writel(reg, &ohci->regs->donehead);
reg = readl(&ohci->regs->fminterval);
dbg("fminterval:..............0x%lx\r\n", reg);
writel(reg, &ohci->regs->fminterval);
reg = readl(&ohci->regs->fmremaining);
dbg("fmremaining:.............0x%lx\r\n", reg);
writel(reg, &ohci->regs->fmremaining);
reg = readl(&ohci->regs->fmnumber);
dbg("fmnumber:................0x%lx\r\n", reg);
writel(reg, &ohci->regs->fmnumber);
reg = readl(&ohci->regs->periodicstart);
dbg("periodicstart:...........0x%lx\r\n", reg);
writel(reg, &ohci->regs->periodicstart);
reg = readl(&ohci->regs->lsthresh);
dbg("lstresh:.................0x%lx\r\n", reg);
writel(reg, &ohci->regs->lsthresh);
reg = readl(&ohci->regs->roothub.a);
dbg("roothub_a:...............0x%lx\r\n", reg);
writel(reg, &ohci->regs->roothub.a);
reg = readl(&ohci->regs->roothub.b);
dbg("roothub_b:...............0x%lx\r\n", roothub_b);
writel(reg, &ohci->regs->roothub.b);
reg = readl(&ohci->regs->roothub.status);
dbg("roothub.status:..........0x%lx\r\n", reg);
writel(reg, &ohci->regs->roothub.status);
reg = readl(&ohci->regs->roothub.portstatus[0]);
dbg("roothub.portstatus[0]:...0x%lx\r\n", reg);
writel(reg, &ohci->regs->roothub.portstatus[0]);
}
void dump_hcca(ohci_t *ohci)
{
volatile struct ohci_hcca *hcca = ohci->hcca;
dbg("hcca pad1: 0x%lx\r\n", hcca->pad1);
dbg("hcca frame no: 0x%x\r\n", hcca->frame_no);
dbg("hcca done head: 0x%x\r\n", hcca->done_head);
dbg("hcca int table:\r\n");
#ifdef DEBUG
hexdump(hcca->int_table, sizeof(hcca->int_table));
dbg("\r\nhcca reserved area:\r\n");
hexdump(hcca->reserved_for_hc, sizeof(hcca->reserved_for_hc));
#endif
}
static struct td *ptd;
/* TDs ... */
@@ -214,7 +346,7 @@ static void urb_free_priv(volatile urb_priv_t *urb)
}
}
}
/* FIXME: driver_mem_free(urb); */
driver_mem_free(urb);
}
/*-------------------------------------------------------------------------*/
@@ -235,8 +367,8 @@ static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
usb_pipedevice(pipe),
usb_pipeendpoint(pipe),
usb_pipeout(pipe)? 'O': 'I',
usb_pipetype(pipe) < 2 ? \
(usb_pipeint(pipe)? "INTR": "ISOC"): \
usb_pipetype(pipe) < 2 ?
(usb_pipeint(pipe) ? "INTR": "ISOC") :
(usb_pipecontrol(pipe)? "CTRL": "BULK"),
(purb ? purb->actual_length : 0),
transfer_len, dev->status);
@@ -390,8 +522,8 @@ static void ohci_dump_roothub(ohci_t *controller, int verbose)
temp = roothub_a(controller);
(void) temp;
// ndp = (temp & RH_A_NDP);
ndp = controller->ndp;
ndp = (temp & RH_A_NDP);
// ndp = controller->ndp;
if (verbose)
{
dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d\r\n", temp,
@@ -1065,7 +1197,7 @@ static void check_status(volatile ohci_t *ohci, td_t *td_list)
if (cc)
{
err("OHCI usb-%s-%c error: %s (%x)\r\n", ohci->slot_name, (char) ohci->controller + '0', cc_to_string[cc], cc);
err("%s (%x)\r\n", ohci->slot_name, (char) ohci->controller + '0', cc_to_string[cc], cc);
if (*phwHeadP & swpl(0x1))
{
if (lurb_priv && ((td_list->index + 1) < urb_len))
@@ -1321,16 +1453,16 @@ static unsigned char root_hub_str_index1[] =
/*-------------------------------------------------------------------------*/
#define OK(x) len = (x); break
#define OK(x) len = (x); break
#ifdef DEBUG_OHCI
#define WR_RH_STAT(x) { err("WR:status %#8x", (x)); writel((x), &ohci->regs->roothub.status); }
#define WR_RH_PORTSTAT(x) { err("WR:portstatus[%d] %#8x", wIndex - 1, (x)); writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); }
#define WR_RH_STAT(x) { inf("WR:status %#8x", (x)); writel((x), &ohci->regs->roothub.status); }
#define WR_RH_PORTSTAT(x) { inf("WR:portstatus[%d] %#8x", wIndex - 1, (x)); writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); }
#else
#define WR_RH_STAT(x) { writel((x), &ohci->regs->roothub.status); }
#define WR_RH_PORTSTAT(x) { writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); }
#define WR_RH_STAT(x) { writel((x), &ohci->regs->roothub.status); }
#define WR_RH_PORTSTAT(x) { writel((x), &ohci->regs->roothub.portstatus[wIndex - 1]); }
#endif
#define RD_RH_STAT roothub_status(ohci)
#define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
#define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex - 1)
/* request to virtual root hub */
@@ -1370,7 +1502,7 @@ static int ohci_submit_rh_msg(volatile ohci_t *ohci, struct usb_device *dev, uin
int len = 0;
int stat = 0;
uint32_t datab[4];
uint8_t *data_buf = (uint8_t *)datab;
uint8_t *data_buf = (uint8_t *) datab;
uint16_t bmRType_bReq;
uint16_t wValue;
uint16_t wIndex;
@@ -1381,7 +1513,7 @@ static int ohci_submit_rh_msg(volatile ohci_t *ohci, struct usb_device *dev, uin
#else
if (ohci->irq)
{
wait_ms(10);
wait_ms(1);
}
#endif
@@ -1409,23 +1541,23 @@ static int ohci_submit_rh_msg(volatile ohci_t *ohci, struct usb_device *dev, uin
* RH_OTHER | RH_CLASS almost ever means HUB_PORT here
*/
case RH_GET_STATUS:
*(uint16_t *) data_buf = swpw(1);
* (uint16_t *) data_buf = swpw(1);
OK(2);
case RH_GET_STATUS | RH_INTERFACE:
*(uint16_t *) data_buf = swpw(0);
* (uint16_t *) data_buf = swpw(0);
OK(2);
case RH_GET_STATUS | RH_ENDPOINT:
*(uint16_t *) data_buf = swpw(0);
* (uint16_t *) data_buf = swpw(0);
OK(2);
case RH_GET_STATUS | RH_CLASS:
*(uint32_t *) data_buf = swpl(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
* (uint32_t *) data_buf = swpl(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
OK(4);
case RH_GET_STATUS | RH_OTHER | RH_CLASS:
*(uint32_t *) data_buf = swpl(RD_RH_PORTSTAT);
* (uint32_t *) data_buf = swpl(RD_RH_PORTSTAT);
OK(4);
case RH_CLEAR_FEATURE | RH_ENDPOINT:
@@ -1636,7 +1768,7 @@ static int submit_common_msg(volatile ohci_t *ohci, struct usb_device *dev, uint
#else
if (ohci->irq)
{
wait_us(10);
wait_ms(1);
}
#endif
@@ -1654,7 +1786,7 @@ static int submit_common_msg(volatile ohci_t *ohci, struct usb_device *dev, uint
#if 0
wait_us(10);
/* ohci_dump_status(ohci); */
ohci_dump_status(ohci);
#endif
/* allow more time for a BULK device to react - some are slow */
@@ -1710,7 +1842,7 @@ static int submit_common_msg(volatile ohci_t *ohci, struct usb_device *dev, uint
if (--timeout)
{
wait_ms(10);
wait_ms(1);
// if (!urb->finished)
// xprintf("*\r\n");
}
@@ -1730,7 +1862,7 @@ static int submit_common_msg(volatile ohci_t *ohci, struct usb_device *dev, uint
pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
#else
if (ohci->irq)
wait_ms(10);
wait_us(10);
#endif
/* free TDs in urb_priv */
if (!usb_pipeint(pipe))
@@ -1779,7 +1911,8 @@ int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer,
int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval)
{
err("submit_int_msg dev 0x%p ohci 0x%p buffer 0x%p len %d", dev, dev->priv_hcd, buffer, transfer_len);
err("submit_int_msg dev 0x%p ohci 0x%p buffer 0x%p len %d\r\n", dev, dev->priv_hcd, buffer, transfer_len);
return submit_common_msg((ohci_t *)dev->priv_hcd, dev, pipe, buffer, transfer_len, NULL, interval);
}
@@ -1814,14 +1947,15 @@ static int hc_reset(volatile ohci_t *ohci)
if (handle >= 0)
{
uint32_t id = 0;
id = pci_read_config_longword(handle, PCIIDR);
id = swpl(pci_read_config_longword(handle, PCIIDR));
if ((PCI_VENDOR_ID_PHILIPS == (id & 0xFFFF)) && (PCI_DEVICE_ID_PHILIPS_ISP1561_2 == (id >> 16)))
{
int timeout = 1000;
uint32_t usb_base_addr = 0xFFFFFFFF;
struct pci_rd *pci_rsc_desc;
pci_rsc_desc = pci_get_resource(handle); /* USB OHCI */
if ((long)pci_rsc_desc >= 0)
if ((long) pci_rsc_desc >= 0)
{
unsigned short flags;
do
@@ -1831,6 +1965,7 @@ static int hc_reset(volatile ohci_t *ohci)
if (usb_base_addr == 0xFFFFFFFF)
{
uint32_t base = pci_rsc_desc->offset + pci_rsc_desc->start;
writel((uint32_t) readl((uint32_t *) base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET, (uint32_t *) base + EHCI_USBCMD_OFF);
while (readl((uint32_t *) base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET)
{
@@ -1839,7 +1974,7 @@ static int hc_reset(volatile ohci_t *ohci)
err("USB RootHub reset timed out!\r\n");
break;
}
wait_us(1);
wait_ms(1);
}
}
}
@@ -1861,13 +1996,13 @@ static int hc_reset(volatile ohci_t *ohci)
#if defined(MACHINE_FIREBEE)
{
dbg("USB OHCI set 48MHz clock\r\n");
pci_write_config_longword(ohci->handle, 0xE4, 0x21); // oscillator & disable ehci
pci_write_config_longword(ohci->handle, 0xE4, swpw(0x21)); // oscillator & disable ehci
wait_us(1);
}
//else
#else
{
pci_write_config_longword(ohci->handle, 0xE4, pci_read_config_longword(ohci->handle, 0xE4) | 0x01); // disable ehci
pci_write_config_longword(ohci->handle, 0xE4, swpl(swpl(pci_read_config_longword(ohci->handle, 0xE4)) | 0x01)); // disable ehci
wait_us(1);
}
#endif
@@ -1916,6 +2051,7 @@ static int hc_reset(volatile ohci_t *ohci)
}
wait_us(1);
}
return 0;
}
@@ -1940,7 +2076,7 @@ static int hc_start(volatile ohci_t *ohci)
writel(0, &ohci->regs->ed_controlhead);
writel(0, &ohci->regs->ed_bulkhead);
writel((uint32_t) ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
writel((uint32_t) ohci->hcca /* + 0x40000000UL */, &ohci->regs->hcca); /* a reset clears this */
fminterval = 0x2edf;
writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
@@ -2001,7 +2137,6 @@ static int hc_interrupt(volatile ohci_t *ohci)
int ints;
int stat = -1;
dbg("\r\n");
if ((ohci->hcca->done_head != 0) && !(swpl(ohci->hcca->done_head) & 0x01))
{
ints = OHCI_INTR_WDH;
@@ -2020,7 +2155,7 @@ static int hc_interrupt(volatile ohci_t *ohci)
ints &= readl(&regs->intrenable);
if (ints == 0)
{
dbg("no interrupt...\r\n");
// dbg("no interrupt...\r\n");
return 0xff;
}
@@ -2039,7 +2174,7 @@ static int hc_interrupt(volatile ohci_t *ohci)
if (ints & OHCI_INTR_UE) /* e.g. due to PCI Master/Target Abort */
{
unsigned short status = pci_read_config_word(ohci->handle, PCISR);
unsigned short status = swpw(pci_read_config_word(ohci->handle, PCISR));
err("OHCI Unrecoverable Error, controller usb-%s-%c disabled\r\n(SR:0x%04X%s%s%s%s%s%s)",
ohci->slot_name, (char) ohci->controller + '0', status & 0xFFFF,
@@ -2155,17 +2290,17 @@ static void hc_free_buffers(volatile ohci_t *ohci)
{
if (ohci->td_unaligned != NULL)
{
/* FIXME: driver_mem_free(ohci->td_unaligned); */
driver_mem_free(ohci->td_unaligned);
ohci->td_unaligned = NULL;
}
if (ohci->ohci_dev_unaligned != NULL)
{
/* FIXME: driver_mem_free(ohci->ohci_dev_unaligned); */
driver_mem_free(ohci->ohci_dev_unaligned);
ohci->ohci_dev_unaligned = NULL;
}
if (ohci->hcca_unaligned != NULL)
{
/* FIXME: driver_mem_free(ohci->hcca_unaligned); */
driver_mem_free(ohci->hcca_unaligned);
ohci->hcca_unaligned = NULL;
}
}
@@ -2208,7 +2343,7 @@ int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void
/* align the storage */
ohci->hcca = (struct ohci_hcca *) (((uint32_t) ohci->hcca_unaligned + 255) & ~255);
memset((void *) ohci->hcca, 0, sizeof(struct ohci_hcca));
inf("aligned ghcca %p\r\n", ohci->hcca);
inf("aligned and cleared ghcca %p\r\n", ohci->hcca);
ohci->ohci_dev_unaligned = driver_mem_alloc(sizeof(struct ohci_device) + 8);
if (ohci->ohci_dev_unaligned == NULL)
@@ -2337,6 +2472,8 @@ int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void
/* Initialization failed */
return -1;
}
write_registers(ohci);
dump_hcca(ohci);
#ifdef DEBUG_OHCI
ohci_dump(ohci, 1);

View File

@@ -48,25 +48,25 @@ static struct pci_class
char *description;
} pci_classes[] =
{
{ 0x00, "device was built prior definition of the class code field" },
{ 0x01, "Mass Storage Controller" },
{ 0x02, "Network Controller" },
{ 0x03, "Display Controller" },
{ 0x04, "Multimedia Controller" },
{ 0x05, "Memory Controller" },
{ 0x06, "Bridge Device" },
{ 0x07, "Simple Communication Controller" },
{ 0x08, "Base System Peripherial" },
{ 0x09, "Input Device" },
{ 0x0a, "Docking Station" },
{ 0x0b, "Processor" },
{ 0x0c, "Serial Bus Controller" },
{ 0x0d, "Wireless Controller" },
{ 0x0e, "Intelligent I/O Controller" },
{ 0x0f, "Satellite Communication Controller" },
{ 0x10, "Encryption/Decryption Controller" },
{ 0x11, "Data Acquisition and Signal Processing Controller" },
{ 0xff, "Device does not fit any defined class" },
{ 0x00, "device was built prior definition of the class code field" },
{ 0x01, "Mass Storage Controller" },
{ 0x02, "Network Controller" },
{ 0x03, "Display Controller" },
{ 0x04, "Multimedia Controller" },
{ 0x05, "Memory Controller" },
{ 0x06, "Bridge Device" },
{ 0x07, "Simple Communication Controller" },
{ 0x08, "Base System Peripherial" },
{ 0x09, "Input Device" },
{ 0x0a, "Docking Station" },
{ 0x0b, "Processor" },
{ 0x0c, "Serial Bus Controller" },
{ 0x0d, "Wireless Controller" },
{ 0x0e, "Intelligent I/O Controller" },
{ 0x0f, "Satellite Communication Controller" },
{ 0x10, "Encryption/Decryption Controller" },
{ 0x11, "Data Acquisition and Signal Processing Controller" },
{ 0xff, "Device does not fit any defined class" },
};
static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
@@ -107,6 +107,7 @@ int32_t pci_get_interrupt_cause(void)
{
int32_t handle;
int32_t *hdl = &handles[0];
/*
* loop through all PCI devices...
*/
@@ -954,6 +955,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
cr |= PCICR_INT_DISABLE;
/* allow bus mastering */
cr |= PCICR_MASTER;
/*
* enable device memory or I/O access
*/
@@ -974,7 +978,7 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
pci_write_config_longword(handle, PCIBISTR, MCF_PCI_PCICR1_CACHELINESIZE(8) |
MCF_PCI_PCICR1_LATTIMER(0x20));
pci_write_config_longword(handle, PCIBAR0, swpl(0x80000000));
pci_write_config_longword(handle, PCIBAR0, swpl(0x40000000));
pci_write_config_longword(handle, PCIBAR1, 0x0);
pci_write_config_word(handle, PCI_LANESWAP_W(PCICR), swpw(
(1 << 1) /* memory space */

View File

@@ -741,7 +741,7 @@ void init_isr(void)
MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
// MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
@@ -757,10 +757,12 @@ void init_isr(void)
MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
#ifdef NOT_USED /* TODO: this appears to crash early and needs some further work */
if (!isr_register_handler(64 + INT_SOURCE_XLBARB, 7, 1, xlbarb_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for XLB ARB interrupts\r\n");
}
#endif
}
void ide_init(void)
@@ -787,11 +789,6 @@ void init_usb(void)
int usb_found = 0;
int index = 0;
/*
* disabled for now
*/
return;
inf("USB controller initialization:\r\n");
do
@@ -1051,7 +1048,14 @@ void BaS(void)
video_init();
/* initialize USB devices */
// init_usb();
/*
* FIXME: USB device scan sometimes finds mouse and keyboard but also sometimes just hangs or crashes.
* this seems to be related to XLBARB interrupts - need to investigate
*/
#ifdef NOT_USED
init_usb();
#endif /* FIXME */
set_ipl(7); /* disable interrupts */

View File

@@ -624,19 +624,19 @@ void mmu_init(void)
/* map PCI address space */
/* set SRAM and MBAR access */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
// ACR_SP(1) | /* supervisor only access permitted */
ACR_SP(1) | /* match on all accesses */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor and user mode */
ACR_S(ACR_S_ALL) | /* match addresses in supervisor and user mode */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
// ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
ACR_BA(0xe0000000));
ACR_BA(PCI_MEMORY_OFFSET)); /* (equals area from 3 to 4 GB */
// ACR_BA(0xe0000000));
#elif defined(MACHINE_M5484LITE) || defined(MACHINE_M5475EVB)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
// ACR_BA(PCI_MEMORY_OFFSET));
ACR_BA(0xe0000000));
ACR_BA(PCI_MEMORY_OFFSET));
// ACR_BA(0xe0000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
@@ -647,7 +647,7 @@ void mmu_init(void)
/* data access attributes for BaS in flash */
set_acr1(ACR_W(0) |
ACR_SP(0) |
ACR_SP(3) |
ACR_CM(0) |
#if defined(MACHINE_FIREBEE)
ACR_CM(ACR_CM_CACHEABLE_WT) |

View File

@@ -54,7 +54,7 @@
#include "usb.h"
#include "usb_hub.h"
// #define DEBUG
//#define DEBUG
#include "debug.h"
struct hci
@@ -155,12 +155,12 @@ int usb_init(int32_t handle, const struct pci_device_id *ent)
break;
case PCI_CLASS_SERIAL_USB_OHCI:
dbg("initialize ohci host controller interface\r\n");
inf("initialize ohci host controller interface\r\n");
res = ohci_usb_lowlevel_init(handle, ent, (void *) &priv);
break;
case PCI_CLASS_SERIAL_USB_EHCI:
dbg("initialize ehci host controller interface\r\n");
inf("initialize ehci host controller interface\r\n");
res = ehci_usb_lowlevel_init(handle, ent, (void *) &priv);
break;
@@ -184,11 +184,11 @@ int usb_init(int32_t handle, const struct pci_device_id *ent)
dbg("could not allocate memory\r\n");
return -1; /* no memory, no USB */
return -1; /* no memory, no USB */
}
}
xprintf("Scanning bus for devices... ");
xprintf("Scanning bus for devices...\r\n");
controller_priv[bus_index] = priv;
controller_priv[bus_index]->usbnum = bus_index;
@@ -399,7 +399,7 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len,
while (timeout--)
{
if (!((volatile uint32_t) dev->status & USB_ST_NOT_PROC)) /* FIXME: this volatile does nothing! */
if (!((* (volatile uint32_t *) &dev->status) & USB_ST_NOT_PROC))
break;
wait(1);
}
@@ -634,6 +634,7 @@ int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char
dbg("dev=%d type=%d, index=%d\r\n", dev->devnum, type, index);
res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, (type << 8) + index, 0, buf, size, USB_CNTL_TIMEOUT);
dbg("result=0x%x\r\n", res);
return res;
}
@@ -919,7 +920,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
if (tbuf == NULL)
{
dbg("usb_string: malloc failure\r\n");
err("usb_string: malloc failure\r\n");
return -1;
}
@@ -944,7 +945,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
dev->have_langid = -1;
dev->string_langid = tbuf[2] | (tbuf[3] << 8);
/* always use the first langid listed */
dbg("USB device number %d default language ID 0x%x\r\n", dev->devnum, dev->string_langid);
inf("USB device number %d default language ID 0x%x\r\n", dev->devnum, dev->string_langid);
}
}
error = usb_string_sub(dev, dev->string_langid, index, tbuf);
@@ -1056,7 +1057,7 @@ struct usb_device *usb_alloc_new_device(int bus, void *priv)
int index = dev_index[bus];
struct usb_device *dev;
dbg("USB %d new device %d\r\n", bus, index);
dbg("USB bus %d new device %d\r\n", bus, index);
if (index >= USB_MAX_DEVICE)
{
dbg("ERROR, too many USB Devices, max=%d\r\n", USB_MAX_DEVICE);
@@ -1118,7 +1119,6 @@ int usb_new_device(struct usb_device *dev)
return 1;
}
//#define CONFIG_LEGACY_USB_INIT_SEQ
#ifdef CONFIG_LEGACY_USB_INIT_SEQ
/*
* this is the old and known way of initializing devices, it is
@@ -1132,7 +1132,7 @@ int usb_new_device(struct usb_device *dev)
dev->epmaxpacketin[0] = 8;
dev->epmaxpacketout[0] = 8;
error = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8);
if (err < 8)
if (error < 8)
{
err("\r\nUSB device not responding, giving up (status=%lX)\r\n", dev->status);
driver_mem_free(tmpbuf);
@@ -1278,17 +1278,26 @@ int usb_new_device(struct usb_device *dev)
{
usb_string(dev, dev->descriptor.iManufacturer, dev->mf, sizeof(dev->mf));
}
else
strcpy(dev->mf, "NONE");
if (dev->descriptor.iProduct)
{
usb_string(dev, dev->descriptor.iProduct, dev->prod, sizeof(dev->prod));
}
else
strcpy(dev->prod, "NONE");
if (dev->descriptor.iSerialNumber)
{
usb_string(dev, dev->descriptor.iSerialNumber, dev->serial, sizeof(dev->serial));
}
inf("Manufacturer %s\r\n", dev->mf);
inf("Product %s\r\n", dev->prod);
inf("SerialNumber %s\r\n", dev->serial);
else
strcpy(dev->serial, "NONE");
inf("usb %d, dev %d: Manufacturer: %s, ", dev->usbnum, dev->devnum, dev->mf);
inf("Product : %s, ", dev->prod);
inf("SerialNumber: %s\r\n", dev->serial);
/* now probe if the device is a hub */
usb_hub_probe(dev, 0);
@@ -1319,7 +1328,6 @@ void usb_scan_devices(void *priv)
dev = usb_alloc_new_device(bus_index, priv);
if (usb_new_device(dev))
{
xprintf("No USB Device found\r\n");
if (dev != NULL)
{
dev_index[bus_index]--;

View File

@@ -563,7 +563,11 @@ int drv_usb_kbd_init(void)
if(dev == NULL)
break;
if(usb_kbd_register(dev) > 0)
{
xprintf("usb device %d, %d registered as keyboard\r\n", j, i);
return 1;
}
}
}
/* no USB Keyboard found */

View File

@@ -26,7 +26,7 @@
#include "exceptions.h"
#include "driver_mem.h"
// // #define DEBUG
// #define DEBUG
#include "debug.h"
extern void ltoa(char *buf, long n, unsigned long base);
@@ -97,9 +97,13 @@ int drv_usb_mouse_init(void)
break;
}
xprintf("Try to register usb device %d,%d as mouse\r\n", i, j);
if (usb_mouse_register(dev) > 0)
{
xprintf("usb device %d, %d registered as mouse\r\n", j, i);
return 1;
}
}
}
/* no USB Mouse found */