From f7985ca85c3c17eb8f719cbec5752be4b263f2a3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Fri, 20 Nov 2015 12:34:17 +0000
Subject: [PATCH] fix __MBAR and __RAMBAR for MCF54455

---
 BaS_gcc/bas.lk.in     | 11 +++++++++++
 BaS_gcc/sys/startcf.S | 16 ++++++++++++----
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/BaS_gcc/bas.lk.in b/BaS_gcc/bas.lk.in
index 2b90f33..fd829ab 100644
--- a/BaS_gcc/bas.lk.in
+++ b/BaS_gcc/bas.lk.in
@@ -223,6 +223,7 @@ SECTIONS
         /* MMU memory mapped registers */
         __MMUBAR                = 0xFF040000;
 
+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
         /*
          * 4KB on-chip Core SRAM0: -> exception table
          */
@@ -233,6 +234,11 @@ SECTIONS
         __RAMBAR1               = 0xFF101000;
         __RAMBAR1_SIZE          = 0x00001000;
         __SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
+#else
+        __RAMBAR0               = 0x80000000;   /* RAMBAR must be between 0x80000000 on MCF54455 */
+        __RAMBAR0_SIZE          = 0x1000;
+        __SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE + 0x1000 - 4;
+#endif
 
     /*
      * FPGA_JTAG_LOADED (if 1) indicates that FPGA configuration has been loaded through JTAG
@@ -240,8 +246,13 @@ SECTIONS
      * by a random uninitialised value), __FPGA_JTAG_VALID is used as a "magic value" and must be
      * 0xaffeaffe to make this work.
      */
+#if !defined(MACHINE_M54455)        /* MCF54455 does not have RAMBAR0 and RAMBAR1 */
     __FPGA_JTAG_LOADED      = __RAMBAR1;
     __FPGA_JTAG_VALID       = __RAMBAR1 + 4;
+#else
+    __FPGA_JTAG_LOADED      = __RAMBAR0 + 0x1000;
+    __FPGA_JTAG_VALID       = __RAMBAR0 + 0x1000 + 4;
+#endif
 
     /* system variables */
     /* RAMBAR0 0 to 0x7FF -> exception vectors */
diff --git a/BaS_gcc/sys/startcf.S b/BaS_gcc/sys/startcf.S
index 47099d5..6986135 100644
--- a/BaS_gcc/sys/startcf.S
+++ b/BaS_gcc/sys/startcf.S
@@ -18,20 +18,22 @@ _rom_header:
 		 * We replace it by bra.s to allow running the ROM from the first byte.
 		 * Then we add a fake jmp instruction for pretty disassembly.
 		 */
-		bra.s	_rom_entry	// Short jump to the real entry point
-		.short	0x4ef9		// Fake jmp instruction
+		bra.s	_rom_entry		// Short jump to the real entry point
+		.short	0x4ef9			// Fake jmp instruction
 		/* The second long is the initial PC */
-		.long	_rom_entry	// Real entry point
+		.long	_rom_entry		// Real entry point
 
 /* ROM entry point */
 _rom_entry:
 		/* disable interrupts */
 		move.w #0x2700,sr
 
+#if !defined(MACHINE_M54455)			// MCF54455 does not have the MBAR register
 		/* Initialize MBAR */
 		move.l	#__MBAR,d0
 		movec	d0,MBAR
 		move.l	d0,_rt_mbar
+#endif
 
 		/* mmu off */
 		move.l	#__MMUBAR+1,d0
@@ -40,11 +42,17 @@ _rom_entry:
 		clr.l	d0
 		move.l	d0,MCF_MMU_MMUCR
 
+#if !defined(MACHINE_M54455)			// MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
+
 		/* Initialize RAMBARs: locate SRAM and validate it */
-		move.l	#__RAMBAR0 + 0x7,d0 	/* supervisor only */
+		move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
 		movec	d0,RAMBAR0
 		move.l	#__RAMBAR1 + 0x1,d0
 		movec	d0,RAMBAR1
+#else
+		move.l	#__RAMBAR0 + 0x7,d0
+		movec	d0,RAMBAR
+#endif
 
 		/* set stack pointer to end of SRAM */
 		lea 	__SUP_SP,a7