diff --git a/BaS_gcc/include/sysinit.h b/BaS_gcc/include/sysinit.h index b59707e..2447f00 100644 --- a/BaS_gcc/include/sysinit.h +++ b/BaS_gcc/include/sysinit.h @@ -28,13 +28,17 @@ #ifndef __SYSINIT_H__ #define __SYSINIT_H__ +#include + /* function(s) from init_fpga.c */ -extern void init_fpga(void); +extern bool init_fpga(void); extern void init_usb(void); /* fault_vectors */ extern void setup_vectors(void); +extern bool fpga_configured; + #endif /* __SYSINIT_H__ */ diff --git a/BaS_gcc/sys/exceptions.S b/BaS_gcc/sys/exceptions.S index d8b76f1..a0ae926 100644 --- a/BaS_gcc/sys/exceptions.S +++ b/BaS_gcc/sys/exceptions.S @@ -48,26 +48,25 @@ .extern _irq7_handler /* Register read/write macros */ -#define MCF_MMU_MMUCR __MMUBAR -#define MCF_MMU_MMUOR __MMUBAR+0x04 -#define MCF_MMU_MMUSR __MMUBAR+0x08 -#define MCF_MMU_MMUAR __MMUBAR+0x10 -#define MCF_MMU_MMUTR __MMUBAR+0x14 -#define MCF_MMU_MMUDR __MMUBAR+0x18 +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 -#define MCF_EPORT_EPPAR __MBAR+0xF00 -#define MCF_EPORT_EPDDR __MBAR+0xF04 -#define MCF_EPORT_EPIER __MBAR+0xF05 -#define MCF_EPORT_EPDR __MBAR+0xF08 -#define MCF_EPORT_EPPDR __MBAR+0xF09 -#define MCF_EPORT_EPFR __MBAR+0xF0C +#define MCF_EPORT_EPPAR __MBAR+0xF00 +#define MCF_EPORT_EPDDR __MBAR+0xF04 +#define MCF_EPORT_EPIER __MBAR+0xF05 +#define MCF_EPORT_EPDR __MBAR+0xF08 +#define MCF_EPORT_EPPDR __MBAR+0xF09 +#define MCF_EPORT_EPFR __MBAR+0xF0C -#define MCF_GPIO_PODR_FEC1L __MBAR+0xA07 +#define MCF_GPIO_PODR_FEC1L __MBAR+0xA07 +#define MCF_PSC0_PSCTB_8BIT __MBAR+0x860C -#define MCF_PSC0_PSCTB_8BIT __MBAR+0x860C - -#define MCF_PSC3_PSCRB_8BIT __MBAR+0x890C -#define MCF_PSC3_PSCTB_8BIT __MBAR+0x890C +#define MCF_PSC3_PSCRB_8BIT __MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT __MBAR+0x890C .global _vec_init diff --git a/BaS_gcc/sys/init_fpga.c b/BaS_gcc/sys/init_fpga.c index 16459ff..01240f3 100644 --- a/BaS_gcc/sys/init_fpga.c +++ b/BaS_gcc/sys/init_fpga.c @@ -38,59 +38,50 @@ extern uint8_t _FPGA_FLASH_DATA[]; extern uint8_t _FPGA_FLASH_DATA_SIZE[]; #define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_FLASH_DATA_SIZE[0]) - -#ifdef _NOT_USED_ -void test_longword(void) +void config_gpio_for_fpga_config(void) { - uint32_t *fpga_data = (uint32_t *) FPGA_FLASH_DATA; - const uint32_t *fpga_flash_data_end = (uint32_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE; - do - { - uint32_t value = *fpga_data++; - xprintf("LONGWORDS: addr=%p, value=%08x\r", fpga_data, value); - } while (fpga_data < fpga_flash_data_end); - xprintf("finished. \r\n"); +#if defined(MACHINE_FIREBEE) + /* + * Configure GPIO FEC1L port directions (needed to load FPGA configuration) + */ + MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */ + 0 | /* bit 6 = input */ + 0 | /* bit 5 = input */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */ + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */ + 0; /* bit 0 => input */ +#endif /* MACHINE_FIREBEE */ } -void test_word(void) +void config_gpio_for_jtag_config(void) { - uint16_t *fpga_data = (uint16_t *) FPGA_FLASH_DATA; - const uint16_t *fpga_flash_data_end = (uint16_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE; - - do - { - uint16_t value = *fpga_data++; - xprintf("WORDS: addr=%p, value=%04x\r", fpga_data, value); - } while (fpga_data < fpga_flash_data_end); - xprintf("finished. \r\n"); + /* + * configure FEC1L port directions to enable external JTAG configuration download to FPGA + */ + MCF_GPIO_PDDR_FEC1L = 0 | + MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */ + /* all other bits = input */ + /* + * unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect + * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well... + */ } -void test_byte(void) -{ - uint8_t *fpga_data = (uint8_t *) FPGA_FLASH_DATA; - const uint8_t *fpga_flash_data_end = (uint8_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE; - - do - { - uint8_t value = *fpga_data++; - xprintf("LONGWORDS: addr=%p, value=%08x\r", fpga_data, value); - } while (fpga_data < fpga_flash_data_end); - xprintf("finished. \r\n"); -} -#endif /* _NOT_USED_ */ - /* * load FPGA */ -void init_fpga(void) +bool init_fpga(void) { uint8_t *fpga_data; volatile int32_t time, start, end; int i; xprintf("FPGA load config... "); - start = MCF_SLT0_SCNT; + start = MCF_SLT0_SCNT; + config_gpio_for_fpga_config(); MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ /* pulling FPGA_CONFIG to low resets the FPGA */ @@ -109,7 +100,7 @@ void init_fpga(void) * configuration cycle consists of 3 stages�reset, configuration, and initialization. * While nCONFIG is low, the device is in reset. When the device comes out of reset, * nCONFIG must be at a logic high level in order for the device to release the open-drain - * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA + * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA * is ready to receive configuration data. Before and during configuration, all user I/O pins * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors * on the I/O pins which are on, before and during configuration. @@ -159,11 +150,12 @@ void init_fpga(void) #endif /* _NOT_USED_ */ end = MCF_SLT0_SCNT; time = (start - end) / (SYSCLK / 1000) / 1000; - + xprintf("finished (took %f seconds).\r\n", time / 1000.0); + config_gpio_for_jtag_config(); + return true; } - else - { - xprintf("FAILED!\r\n"); - } + xprintf("FAILED!\r\n"); + config_gpio_for_jtag_config(); + return false; } diff --git a/BaS_gcc/sys/startcf.S b/BaS_gcc/sys/startcf.S index 47d448e..c2eb53f 100644 --- a/BaS_gcc/sys/startcf.S +++ b/BaS_gcc/sys/startcf.S @@ -1,3 +1,4 @@ + /* * This object file must be the first to be linked, * so it will be placed at the very beginning of the ROM. @@ -64,6 +65,3 @@ _rom_entry: /* initialize any hardware specific issues */ bra _initialize_hardware - - -// vim: set syntax=asm68k : diff --git a/BaS_gcc/sys/sysinit.c b/BaS_gcc/sys/sysinit.c index 6cac827..93e0308 100644 --- a/BaS_gcc/sys/sysinit.c +++ b/BaS_gcc/sys/sysinit.c @@ -55,7 +55,9 @@ #include "usb.h" #include "video.h" -#define UNUSED(x) (void)(x) /* Unused variable */ +#define UNUSED(x) (void)(x) /* Unused variable */ + +bool fpga_configured = false; /* for FPGA JTAG configuration */ extern volatile long _VRAM; /* start address of video ram from linker script */ @@ -207,20 +209,6 @@ void init_gpio(void) MCF_PAD_PAR_TIMER_PAR_TOUT3 | MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) | MCF_PAD_PAR_TIMER_PAR_TOUT2; - -#if defined(MACHINE_FIREBEE) - /* - * Configure GPIO FEC1L port directions (needed to load FPGA configuration) - */ - MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */ - 0 | /* bit 6 = input */ - 0 | /* bit 5 = input */ - MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */ - MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */ - MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */ - MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */ - 0; /* bit 0 => input */ -#endif /* MACHINE_FIREBEE */ } /* @@ -1109,34 +1097,12 @@ void initialize_hardware(void) #if MACHINE_FIREBEE if (coldboot) /* does not work with BDM */ ; - init_fpga(); + fpga_configured = init_fpga(); init_pll(); init_video_ddr(); dvi_on(); -#ifdef _NOT_USED_ - /* experimental */ - { - int i; - uint32_t *scradr = (uint32_t *) 0xd00000; - - for (i = 0; i < 100; i++) - { - uint32_t *p = scradr; - - for (p = scradr; p < scradr + 1024 * 150L; p++) - { - *p = 0xffffffff; - } - for (p = scradr; p < scradr + 1024 * 150L; p++) - { - *p = 0x0; - } - } - } -#endif /* _NOT_USED_ */ - #endif /* MACHINE_FIREBEE */ driver_mem_init(); init_pci();