diff --git a/BaS_gcc/sys/exceptions.S b/BaS_gcc/sys/exceptions.S
index c1491cc..28acd66 100644
--- a/BaS_gcc/sys/exceptions.S
+++ b/BaS_gcc/sys/exceptions.S
@@ -463,31 +463,6 @@ zd_end:
 		move.l	(a7)+,a0		
 		rte
 		
-#ifdef _NOT_USED_	
-linea:	
-		move.w	#0x2700,sr			// disable interrupt
-		halt
-		nop
-		nop
-linef:	
-		move.w	#0x2700,sr			// disable interrupt
-		halt
-		nop
-		nop
-format:
-		move.w	#0x2700,sr			// disable interrupt
-		halt
-		nop
-		nop
-
-//floating point		
-flpoow:
-		move.w	#0x2700,sr			// disable interrupt
-		halt
-		nop
-		nop
-#endif /* _NOT_USED */
-
 irq1:
 		irq		0x64,1,0x02
 
diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c
index 550178c..a9f2d70 100644
--- a/BaS_gcc/sys/mmu.c
+++ b/BaS_gcc/sys/mmu.c
@@ -441,7 +441,7 @@ bool access_exception(uint32_t pc, uint32_t format_status)
 		else
 		{
 			fault_address = MCF_MMU_MMUAR;	/* retrieve fault access address from MMU */
-			if (fault_address > FASTRAM_END)
+			if (fault_address >= FASTRAM_END)
 			{
 				is_tlb_miss = false;	/* this is a bus error */
 			}
@@ -459,7 +459,6 @@ bool access_exception(uint32_t pc, uint32_t format_status)
 void mmutr_miss(uint32_t address)
 {
 	dbg("MMU TLB MISS accessing 0x%08x\r\n", address);
-	flush_and_invalidate_caches();
 
 	/* add missed page to TLB */
 	MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */