Firebee/BaS_gcc
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fix indentation

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This commit is contained in:
Markus Fröschle
2017-04-08 16:31:02 +00:00
parent b78c21751a
commit dd402d57fc
1 changed files with 51 additions and 52 deletions
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39
BaS_gcc/sys/startcf.S
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@@ -1,8 +1,8 @@
/*
* This object file must be the first to be linked,
* so it will be placed at the very beginning of the ROM.
*/
//
// This object file must be the first to be linked,
// so it will be placed at the very beginning of the ROM.
//
.equ MCF_MMU_MMUCR, __MMUBAR + 0
@@ -14,18 +14,19 @@
/* ROM header */
_rom_header:
/* The first long is supposed to be the initial SP.
* We replace it by bra.s to allow running the ROM from the first byte.
* Then we add a fake jmp instruction for pretty disassembly.
*/
//
// The first long is supposed to be the initial SP.
// We replace it by bra.s to allow running the ROM from the first byte.
// Then we add a fake jmp instruction for pretty disassembly.
//
bra.s _rom_entry // Short jump to the real entry point
.short 0x4ef9 // Fake jmp instruction
/* The second long is the initial PC */
// The second long is the initial PC
.long _rom_entry // Real entry point
/* ROM entry point */
_rom_entry:
/* disable interrupts */
// disable interrupts
move.w #0x2700,sr
#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register
@@ -45,7 +46,7 @@ _rom_entry:
#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
/* Initialize RAMBARs: locate SRAM and validate it */
// Initialize RAMBARs: locate SRAM and validate it
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
@@ -55,23 +56,21 @@ _rom_entry:
movec d0,RAMBAR
#endif
/* set stack pointer to end of SRAM */
// set stack pointer to end of SRAM
lea __SUP_SP,a7
move.l #0,(sp)
/*
* Initialize the processor caches.
* The instruction cache is fully enabled.
* The data cache is enabled, but cache-inhibited by default.
* Later, the MMU will fully activate the data cache for specific areas.
* It is important to enable both caches now, otherwise cpushl would hang.
*/
// Initialize the processor caches.
// The instruction cache is fully enabled.
// The data cache is enabled, but cache-inhibited by default.
// Later, the MMU will fully activate the data cache for specific areas.
// It is important to enable both caches now, otherwise cpushl would hang.
move.l #0xa50c8120,d0
movec d0,cacr
andi.l #0xfefbfeff,d0 // Clear invalidate bits
move.l d0,_rt_cacr
/* initialize any hardware specific issues */
// initialize any hardware specific issues
bra _initialize_hardware