added interface structure to make the MCD DMA available to MiNT (DMAC cookie). MinT's FEC driver works somewhat, but not reliable yet.
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@@ -306,7 +306,7 @@ init_vec_loop:
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move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
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//move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
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move.l (sp)+,a2 // Restore registers
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@@ -994,7 +994,8 @@ _lowlevel_isr_handler:
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jsr _isr_execute_handler
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lea 4(sp),sp
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cmp.l #1,d0
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beq handled
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//beq handled // this is probably not a too bright idea for hw interrupts not known to TOS
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bra handled
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nothandled:
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movem.l (sp),d0-d1/a0-a1
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unlk a6
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