added interface structure to make the MCD DMA available to MiNT (DMAC cookie). MinT's FEC driver works somewhat, but not reliable yet.

This commit is contained in:
Markus Fröschle
2014-01-01 21:28:17 +00:00
parent 4d37bfcf42
commit dcf0797f11
15 changed files with 589 additions and 625 deletions

View File

@@ -262,9 +262,10 @@ void network_init(void)
handler = fec0_interrupt_handler;
vector = 103;
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL, (void *) &nif1))
{
dbg("%s: unable to register handler\r\n", __FUNCTION__);
dbg("%s: unable to register handler for vector %d\r\n", __FUNCTION__, vector);
return;
}
@@ -276,15 +277,16 @@ void network_init(void)
if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL,NULL))
{
xprintf("Error: Unable to register handler\n");
dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
return;
}
#ifdef _NOT_USED_
nif_init(&nif1);
nif1.mtu = ETH_MTU;
nif1.send = fec0_send;
fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
// fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
memcpy(nif1.hwa, mac, 6);
memcpy(nif1.broadcast, bc, 6);
@@ -293,10 +295,11 @@ void network_init(void)
ip_init(&ip_info, myip, gateway, netmask);
nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
#endif
dma_irq_enable(6, 6);
//set_ipl(0);
dma_irq_enable(6, 0);
//bootp_request(&nif1, 0);
// bootp_request(&nif1, 0);
}
void BaS(void)

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@@ -24,14 +24,7 @@
#include "m5484l.h"
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#undef DRIVER_MEM_DEBUG
//#undef DRIVER_MEM_DEBUG
#ifdef DRIVER_MEM_DEBUG
#define dbg(fmt, args...) xprintf(fmt, ##args)
@@ -114,7 +107,7 @@ static MD *ffit(long amount, MPB *mp)
}
maxval = 0;
maxflg = ((amount == -1) ? TRUE : FALSE) ;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{

View File

@@ -306,7 +306,7 @@ init_vec_loop:
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
//move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
move.l (sp)+,a2 // Restore registers
@@ -994,7 +994,8 @@ _lowlevel_isr_handler:
jsr _isr_execute_handler
lea 4(sp),sp
cmp.l #1,d0
beq handled
//beq handled // this is probably not a too bright idea for hw interrupts not known to TOS
bra handled
nothandled:
movem.l (sp),d0-d1/a0-a1
unlk a6

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@@ -36,7 +36,7 @@ extern void (*rt_vbr[])(void);
#define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
@@ -57,7 +57,7 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
if (source < 1 || source > 63)
{
xprintf("%s: interrupt source %d not defined\r\n", __FUNCTION__, source);
dbg("%s: interrupt source %d not defined\r\n", __FUNCTION__, source);
return -1;
}
@@ -68,7 +68,7 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
{
if (ICR[i] == lp)
{
xprintf("%s: level %d and priority %d already used for interrupt source %d!\r\n", __FUNCTION__,
dbg("%s: level %d and priority %d already used for interrupt source %d!\r\n", __FUNCTION__,
level, priority, i);
return -1;
}
@@ -158,10 +158,12 @@ int isr_register_handler(int type, int vector,
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
return true;
}
}
dbg("%s: no available slots\n\t", __FUNCTION__);
dbg("%s: no available slots to register handler for vector %d\n\r", __FUNCTION__, vector);
return false; /* no available slots */
}
@@ -183,8 +185,11 @@ void isr_remove_handler(int type, int (*handler)(void *, void *))
isrtab[index].handler = 0;
isrtab[index].hdev = 0;
isrtab[index].harg = 0;
return;
}
}
dbg("%s: no such handler registered (type=%d, handler=%p\r\n", __FUNCTION__, type, handler);
}
@@ -205,32 +210,14 @@ bool isr_execute_handler(int vector)
if ((isrtab[index].vector == vector) &&
(isrtab[index].type == ISR_DBUG_ISR))
{
xprintf("calling BaS isr handler at %p\r\n", isrtab[index].handler);
retval = true;
if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
{
retval = true;
break;
return retval;
}
}
}
/*
* Try to locate a user-registered Interrupt Service Routine handler.
*/
for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
{
if ((isrtab[index].vector == vector) &&
(isrtab[index].type == ISR_USER_ISR))
{
xprintf("calling USR isr handler at %p\r\n", isrtab[index].handler);
if (isrtab[index].handler(isrtab[index].hdev,isrtab[index].harg))
{
retval = true;
break;
}
}
}
dbg("%s: no BaS isr handler for vector %d found\r\n", __FUNCTION__, vector);
return retval;
}

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@@ -62,7 +62,7 @@
#define DEBUG_MMU
#ifdef DEBUG_MMU
#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg);} while(0)
#define dbg_mmu(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
#else
#define dbg_mmu(format, arg...) do {;} while (0)
#endif /* DEBUG_MMU */