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replaced DMA API routines by fresh download with originals

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moved more interrupt handlers to generalized handler
cleaned up lowlevel interrupt handling
fixed wrong assignment of interrupt masks
reformatted
This commit is contained in:
Markus Fröschle
2015-01-11 10:27:36 +00:00
parent df28a267da
commit d860191121
14 changed files with 842 additions and 873 deletions
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7
sys/BaS.c
View File

@@ -237,10 +237,11 @@ void enable_coldfire_interrupts()
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
//MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
MCF_INTC_IMRH = 0;
FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
FBEE_INTR_INT_MFP_IRQ6 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
FBEE_INTR_INT_FPGA_IRQ5 | /* enable MFP interrupts */
FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
FBEE_INTR_PCI_INTB |

40
sys/exceptions.S
View File

@@ -228,23 +228,23 @@ init_vec_loop:
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
// install lowlevel_isr_handler for the FEC0 interrupt
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
// install lowlevel_isr_handler for the PSC3 interrupt
move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
// install lowlevel_isr_handler for Coldfire DMA interrupts
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
// install lowlevel_isr_handler for the XLBPCI interrupt
move.l a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
// install lowlevel_isr_handler for the FEC0 interrupt
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
#ifndef MACHINE_FIREBEE
// FEC1 not wired on the FireBee (used for FPGA as GPIO), but available on other machines
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
#endif
// install lowlevel_isr_handler for Coldfire DMA interrupts
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
move.l (sp)+,a2 // Restore registers
rts
@@ -337,7 +337,7 @@ access:
bus_error:
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
bra std_exc_vec
bra std_exc_vec // FIXME: this seems to be bogous...
zero_divide:
move.w #0x2700,sr // disable interrupt
@@ -397,14 +397,14 @@ flpoow:
irq1: irq 0x64, 1, 0x02 // Level 1 autovector interrupt (unused)
irq2: irq 0x68, 2, 0x04 // Level 2 autovector interrupt (horizonatl blank)
irq2: irq 0x68, 2, 0x04 // Level 2 autovector interrupt (horizontal blank)
irq3: irq 0x6c, 3, 0x08 // Level 3 autovector interrupt (unused)
irq4: irq 0x70, 4, 0x10 // Level 4 autovector interrupt (vertical blank)
#if defined(MACHINE_FIREBEE) /* these handlers are only meaningful for the Firebee */
irq5: move.w #0x2700,sr // disable interrupts
irq5: //move.w #0x2700,sr // disable interrupts
subq.l #4,sp // extra space
link a6,#-4 * 4 // save gcc scratch registers
@@ -412,8 +412,8 @@ irq5: move.w #0x2700,sr // disable interrupts
jsr _irq5_handler // call C handler routine
tst.l d0 // handled?
bne irq5_forward
tst.b d0 // handled?
beq irq5_forward
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
@@ -434,7 +434,7 @@ irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector
* irq6 needs special treatment since - because the Coldfire only supports autovector interrupts
* - the exception vector is provided by the simulated MFP from the FPGA
*/
irq6: move.w #0x2700,sr // disable interrupt
irq6: //move.w #0x2700,sr // disable interrupt
subq.l #4,sp // extra space
link a6,#-4 * 4 // save gcc scratch registers
@@ -445,8 +445,8 @@ irq6: move.w #0x2700,sr // disable interrupt
jsr _irq6_handler // call C handler
lea 8(sp),sp // fix stack
tst.l d0 // interrupt handled?
bne irq6_forward // no, forward to TOS
tst.b d0 // interrupt handled?
beq irq6_forward // no, forward to TOS
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
@@ -506,7 +506,7 @@ irq7:
handler_gpt0:
.extern _gpt0_interrupt_handler
move.w #0x2700,sr // disable interrupts
//move.w #0x2700,sr // disable interrupts
link a6,#-4 * 4 // make room for
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
// other registers will be handled by gcc itself
@@ -524,7 +524,7 @@ handler_gpt0:
#else // handlers for M5484LITE
irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
move.w #0x2700,sr // disable interrupts
//move.w #0x2700,sr // disable interrupts
lea -4*4(sp),sp // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
@@ -545,7 +545,7 @@ irq6:
irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
move.w #0x2700,sr // disable interrupts
//move.w #0x2700,sr // disable interrupts
lea -4*4(sp),sp // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
@@ -567,7 +567,7 @@ irq7text:
/*
* low-level interrupt service routine for routines registered with
* isr_register_handler(int vector). If the higlevel routine (isr_execute_handler())
* returns != 0, the call is forwarded to the OS (through its own vector base).
* returns != true, the call is forwarded to the OS (through its own vector base).
*/
.global _lowlevel_isr_handler
.extern _isr_execute_handler
@@ -597,8 +597,8 @@ _lowlevel_isr_handler:
move.l d0,-(sp) // push it
jsr _isr_execute_handler // call the C handler
addq.l #4,sp // adjust stack
tst.l d0 // handled?
bne lowlevel_forward // no, we forward it to TOS
tst.b d0 // handled?
beq lowlevel_forward // no, forward it to TOS
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6

68
sys/interrupts.c
View File

@@ -53,10 +53,10 @@
struct isrentry
{
int vector;
bool (*handler)(void *, void *);
void *hdev;
void *harg;
int vector;
bool (*handler)(void *, void *);
void *hdev;
void *harg;
};
static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */
@@ -93,7 +93,7 @@ bool isr_set_prio_and_level(int int_source, int priority, int level)
}
/*
* enable internal int source in DMA controller
* enable internal int source in interrupt controller
*/
bool isr_enable_int_source(int int_source)
{
@@ -196,11 +196,14 @@ void isr_remove_handler(bool (*handler)(void *, void *))
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*
* This routine returns either true or false where
* true = interrupt has been handled, return to caller
* false= interrupt has been handled or hasn't, but needs to be forwarded to TOS
*/
bool isr_execute_handler(int vector)
{
int index;
bool retval = false;
dbg("vector = %d\r\n", vector);
@@ -216,7 +219,7 @@ bool isr_execute_handler(int vector)
}
err("no isr handler for vector %d found. Spurious?\r\n", vector);
return retval;
return true;
}
/*
@@ -225,7 +228,7 @@ bool isr_execute_handler(int vector)
* Handles PIC requests that come in from PSC3 serial interface. Currently, that
* is RTC/NVRAM requests only
*/
int pic_interrupt_handler(void *arg1, void *arg2)
bool pic_interrupt_handler(void *arg1, void *arg2)
{
uint8_t rcv_byte;
@@ -245,21 +248,21 @@ int pic_interrupt_handler(void *arg1, void *arg2)
MCF_PSC3_PSCTB_8BIT = *rtc_data;
} while (index++ < 64);
}
return 1;
return true;
}
int xlbpci_interrupt_handler(void *arg1, void *arg2)
bool xlbpci_interrupt_handler(void *arg1, void *arg2)
{
dbg("XLB PCI interrupt\r\n");
return 1;
return true;
}
int pciarb_interrupt_handler(void *arg1, void *arg2)
bool pciarb_interrupt_handler(void *arg1, void *arg2)
{
dbg("PCI ARB interrupt\r\n");
return 1;
return true;
}
#if defined(MACHINE_FIREBEE)
@@ -267,13 +270,12 @@ int pciarb_interrupt_handler(void *arg1, void *arg2)
* This gets called from irq5 in exceptions.S
*
* IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler
*
* Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
*/
int irq5_handler(void *arg1, void *arg2)
bool irq5_handler(void *arg1, void *arg2)
{
uint32_t pending_interrupts = FBEE_INTR_PENDING;
dbg("IRQ5!\r\n");
if (pending_interrupts & FBEE_INTR_PIC)
{
dbg("PIC interrupt\r\n");
@@ -312,13 +314,15 @@ int irq5_handler(void *arg1, void *arg2)
if (pending_interrupts & FBEE_INTR_VSYNC || pending_interrupts & FBEE_INTR_HSYNC)
{
dbg("vsync or hsync interrupt!\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_VSYNC | FBEE_INTR_HSYNC;
/* hsync and vsync should go to TOS unhandled */
return 1;
return false;
}
MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */
return 0;
return true;
}
/*
@@ -364,38 +368,41 @@ bool irq6_acsi_dma_interrupt(void)
bool irq6_handler(uint32_t sf1, uint32_t sf2)
{
bool handled = false;
// err("IRQ6!\r\n");
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
//err("IRQ6!\r\n");
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
{
blink_led();
}
return handled;
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
return false; /* always forward IRQ6 to TOS */
}
#else /* MACHINE_FIREBEE */
int irq5_handler(void *arg1, void *arg2)
bool irq5_handler(void *arg1, void *arg2)
{
return 0;
MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */
return true;
}
bool irq6_handler(void *arg1, void *arg2)
{
err("IRQ6!\r\n");
return 0;
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
return false; /* always forward IRQ6 to TOS */
}
/*
* This gets called from irq7 in exceptions.S
* Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
*/
void irq7_handler(void)
bool irq7_handler(void)
{
int32_t handle;
int32_t value = 0;
@@ -411,6 +418,9 @@ void irq7_handler(void)
dbg("interrupt not handled!\r\n");
}
}
MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */
return true;
}
#endif /* MACHINE_M548X */
@@ -429,12 +439,14 @@ void irq7_handler(void)
* video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
* RAM page.
*/
void gpt0_interrupt_handler(void)
bool gpt0_interrupt_handler(void)
{
dbg("handler called\n\r");
MCF_GPT0_GMS &= ~1; /* rearm trigger */
NOP();
MCF_GPT0_GMS |= 1;
return true;
}
#endif /* MACHINE_FIREBEE */

98
sys/mmu.c
View File

@@ -91,7 +91,7 @@ inline uint32_t set_asid(uint32_t value)
uint32_t ret = rt_asid;
__asm__ __volatile__(
"movec %[value],ASID\n\t"
"movec %[value],ASID\n\t"
: /* no output */
: [value] "r" (value)
:
@@ -113,7 +113,7 @@ inline uint32_t set_acr0(uint32_t value)
uint32_t ret = rt_acr0;
__asm__ __volatile__(
"movec %[value],ACR0\n\t"
"movec %[value],ACR0\n\t"
: /* not output */
: [value] "r" (value)
:
@@ -133,7 +133,7 @@ inline uint32_t set_acr1(uint32_t value)
uint32_t ret = rt_acr1;
__asm__ __volatile__(
"movec %[value],ACR1\n\t"
"movec %[value],ACR1\n\t"
: /* not output */
: [value] "r" (value)
:
@@ -154,7 +154,7 @@ inline uint32_t set_acr2(uint32_t value)
uint32_t ret = rt_acr2;
__asm__ __volatile__(
"movec %[value],ACR2\n\t"
"movec %[value],ACR2\n\t"
: /* not output */
: [value] "r" (value)
:
@@ -174,7 +174,7 @@ inline uint32_t set_acr3(uint32_t value)
uint32_t ret = rt_acr3;
__asm__ __volatile__(
"movec %[value],ACR3\n\t"
"movec %[value],ACR3\n\t"
: /* not output */
: [value] "r" (value)
:
@@ -190,7 +190,7 @@ inline uint32_t set_mmubar(uint32_t value)
uint32_t ret = rt_mmubar;
__asm__ __volatile__(
"movec %[value],MMUBAR\n\t"
"movec %[value],MMUBAR\n\t"
: /* no output */
: [value] "r" (value)
: /* no clobber */
@@ -311,22 +311,22 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
MCF_MMU_MMUAR = (virt & size_mask);
MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(page->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
@@ -341,7 +341,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
{
uint16_t ipl;
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
struct page_descriptor *page = &pages[page_index]; /* attributes of page to map */
int32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
@@ -365,21 +365,21 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
ipl = set_ipl(7); /* do not disturb */
MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(page->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
@@ -433,26 +433,26 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page
ipl = set_ipl(7); /* do not disturb */
MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(page_id) | /* address space id (ASID) */
(flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
(flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(sz) | /* page size */
MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(sz) | /* page size */
MCF_MMU_MMUDR_CM(flags->cache_mode) |
(flags->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(flags->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(flags->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(flags->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
NOP();
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
@@ -521,7 +521,7 @@ void mmu_init(void)
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#elif defined(MACHINE_M5484LITE)
@@ -564,7 +564,7 @@ void mmu_init(void)
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#elif defined(MACHINE_M54455)
@@ -607,33 +607,33 @@ void mmu_init(void)
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#else
#error Unknown machine!
#endif /* MACHINE_FIREBEE */
}
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
/* set data access attributes in ACR0 and ACR1 */
/* map PCI address space */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(1) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
ACR_E(1) | /* enable ACR */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(1) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
ACR_BA(0x80000000)); /* FIXME: not determined yet */
#else
#error unknown machine!
#endif /* MACHINE_FIREBEE */
@@ -680,7 +680,7 @@ void mmu_init(void)
set_acr3(0x0);
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
/* create locked TLB entries */