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support for JTAGWAIT.PRG (configure FPGA from JTAG port) implemented

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This commit is contained in:
Markus Fröschle
2014-08-09 13:07:28 +00:00
parent 6dbe795815
commit d842254b36
7 changed files with 138 additions and 76 deletions
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16
tos/jtagwait/Makefile
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@@ -33,18 +33,24 @@ APP=jtagwait.prg
TEST_APP=$(APP)
CFLAGS=\
-Os\
-O0\
-g\
-Wl,-Map,mapfile\
-Wl,--defsym -Wl,__MBAR=0xff000000\
-Wl,--defsym -Wl,__MMUBAR=0xff040000\
-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
-Wall
SRCDIR=sources
INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/jtagwait.c
ASRCS=
$(SRCDIR)/jtagwait.c \
$(SRCDIR)/bas_printf.c
ASRCS=$(SRCDIR)/printf_helper.S
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
@@ -91,7 +97,7 @@ clean:
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif

2
tos/jtagwait/jtagwait.creator.user
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@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject>
<!-- Written by QtCreator 3.0.1, 2014-08-04T18:51:58. -->
<!-- Written by QtCreator 3.0.1, 2014-08-09T06:49:40. -->
<qtcreator>
<data>
<variable>ProjectExplorer.Project.ActiveTarget</variable>

111
tos/jtagwait/sources/jtagwait.c
View File

@@ -3,73 +3,78 @@
#include <stdint.h>
#include <stdbool.h>
#include "bas_printf.h"
#include "MCF5475.h"
#include "driver_vec.h"
#define FPGA_JTAG_LOADED_FLAG ((volatile bool *) 0xFF101000)
extern bool _FPGA_JTAG_LOADED;
extern long _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
#define _MBAR ((volatile uint8_t *) 0xFF000000)
#define MCF_GPIO_PDDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA17]))
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA27]))
#define FPGA_CONFIG (1 << 2)
#define FPGA_CONF_DONE (1 << 5)
static inline uint32_t set_ipl(uint32_t ipl)
{
uint32_t ret;
__asm__ __volatile__(
" move.w sr,%[ret]\r\n" /* retrieve status register */
" andi.l #0x07,%[ipl]\n\t" /* mask out ipl bits on new value */
" lsl.l #8,%[ipl]\n\t" /* shift them to position */
" move.l %[ret],d0\n\t" /* retrieve original value */
" andi.l #0x0000f8ff,d0\n\t" /* clear ipl part */
" or.l %[ipl],d0\n\t" /* or in new value */
" move.w d0,sr\n\t" /* put it in place */
" andi.l #0x0700,%[ret]\r\n" /* mask out ipl bits */
" lsr.l #8,%[ret]\r\n" /* shift them to position */
: [ret] "=&d" (ret) /* output */
: [ipl] "d" (ipl) /* input */
: "d0", "cc" /* clobber */
);
return ret;
}
void wait_for_jtag(void)
{
set_ipl(7); /* disable interrupts */
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
*MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* now that this GPIO ports have been switched to input, we can poll for FPGA config
* started from the JTAG interface (CONFIGn goes high) and finish (CONF_DONE goes high)
*/
while (*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG); /* wait for JTAG reset */
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG)); /* wait for JTAG config load starting */
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
int i;
*FPGA_JTAG_LOADED_FLAG = true; /* indicate jtag loaded FPGA config to BaS */
/* set supervisor stack to end of SRAM1 */
__asm__ __volatile__ (
" move #0x2700,sr\n\t" /* disable interrupts */
" move.l #0xff101000 + 0x1000 - 4,d0\n\t" /* 4KB on-chip core SRAM1 */
" move.l d0,sp\n\t" /* set stack pointer */
:
:
: "d0", "cc" /* clobber */
);
/*
* reboot after configuration finished
*/
__asm__ __volatile__(
"jmp 0xE0000000\n\t"
);
MCF_EPORT_EPIER = 0x0; /* disable EPORT interrupts */
MCF_INTC_IMRL = 0xffffffff;
MCF_INTC_IMRH = 0xffffffff; /* disable interrupt controller */
MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
xprintf("waiting for JTAG configuration start\r\n");
/*
* now that this GPIO ports have been switched to input, we can poll for FPGA config
* started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
*/
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */
xprintf("waiting for JTAG configuration finished\r\n");
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
xprintf("JTAG configuration finished.\r\n");
_FPGA_JTAG_LOADED = true; /* indicate jtag loaded FPGA config to BaS */
_FPGA_JTAG_VALID = VALID_JTAG;
/* wait */
xprintf("wait a little to let things settle...\r\n");
for (i = 0; i < 1000000; i++);
__asm__ __volatile__(
" jmp 0xe0000000\n\t"
: : :
);
}
int main(int argc, char *argv[])
{
printf("\033E\r\nFPGA JTAG configuration support\r\n");
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
"and your Firebee will reboot once finished using that new configuration.\r\n");
Supexec(wait_for_jtag);
printf("\033E\r\nFPGA JTAG configuration support\r\n");
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
"and your Firebee will reboot once finished using that new configuration.\r\n");
Supexec(wait_for_jtag);
return 0; /* just to make the compiler happy, we will never return */
return 0; /* just to make the compiler happy, we will never return */
}