changed types to use <stdint.h>
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@@ -24,54 +24,54 @@
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000]))
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#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004]))
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#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008]))
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#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C]))
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#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010]))
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#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014]))
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#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018]))
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#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C]))
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#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020]))
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#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028]))
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#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C]))
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#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030]))
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#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038]))
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#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C]))
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#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010]))
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#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014]))
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#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044]))
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#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C]))
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#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C]))
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#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010]))
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#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014]))
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#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044]))
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#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C]))
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#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018]))
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#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028]))
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#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030]))
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#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038]))
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#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018]))
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#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028]))
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#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030]))
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#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038]))
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#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018]))
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#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028]))
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#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030]))
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#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038]))
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#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018]))
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#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028]))
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#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030]))
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#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038]))
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#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018]))
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#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028]))
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#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030]))
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#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038]))
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#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)]))
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#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)]))
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#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)]))
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#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)]))
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#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)]))
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#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&__MBAR[0x21000]))
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#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&__MBAR[0x21004]))
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#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&__MBAR[0x21008]))
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#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&__MBAR[0x2100C]))
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#define MCF_SEC_SISRH (*(volatile uint32_t*)(&__MBAR[0x21010]))
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#define MCF_SEC_SISRL (*(volatile uint32_t*)(&__MBAR[0x21014]))
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#define MCF_SEC_SICRH (*(volatile uint32_t*)(&__MBAR[0x21018]))
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#define MCF_SEC_SICRL (*(volatile uint32_t*)(&__MBAR[0x2101C]))
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#define MCF_SEC_SIDR (*(volatile uint32_t*)(&__MBAR[0x21020]))
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#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&__MBAR[0x21028]))
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#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&__MBAR[0x2102C]))
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#define MCF_SEC_SMCR (*(volatile uint32_t*)(&__MBAR[0x21030]))
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#define MCF_SEC_MEAR (*(volatile uint32_t*)(&__MBAR[0x21038]))
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#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&__MBAR[0x2200C]))
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#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&__MBAR[0x22010]))
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#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&__MBAR[0x22014]))
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#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&__MBAR[0x22044]))
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#define MCF_SEC_FR0 (*(volatile uint32_t*)(&__MBAR[0x2204C]))
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#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&__MBAR[0x2300C]))
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#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&__MBAR[0x23010]))
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#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&__MBAR[0x23014]))
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#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&__MBAR[0x23044]))
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#define MCF_SEC_FR1 (*(volatile uint32_t*)(&__MBAR[0x2304C]))
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#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&__MBAR[0x28018]))
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#define MCF_SEC_AFSR (*(volatile uint32_t*)(&__MBAR[0x28028]))
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#define MCF_SEC_AFISR (*(volatile uint32_t*)(&__MBAR[0x28030]))
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#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&__MBAR[0x28038]))
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#define MCF_SEC_DRCR (*(volatile uint32_t*)(&__MBAR[0x2A018]))
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#define MCF_SEC_DSR (*(volatile uint32_t*)(&__MBAR[0x2A028]))
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#define MCF_SEC_DISR (*(volatile uint32_t*)(&__MBAR[0x2A030]))
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#define MCF_SEC_DIMR (*(volatile uint32_t*)(&__MBAR[0x2A038]))
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#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&__MBAR[0x2C018]))
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#define MCF_SEC_MDSR (*(volatile uint32_t*)(&__MBAR[0x2C028]))
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#define MCF_SEC_MDISR (*(volatile uint32_t*)(&__MBAR[0x2C030]))
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#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&__MBAR[0x2C038]))
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#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&__MBAR[0x2E018]))
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#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&__MBAR[0x2E028]))
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#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&__MBAR[0x2E030]))
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#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&__MBAR[0x2E038]))
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#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&__MBAR[0x32018]))
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#define MCF_SEC_AESSR (*(volatile uint32_t*)(&__MBAR[0x32028]))
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#define MCF_SEC_AESISR (*(volatile uint32_t*)(&__MBAR[0x32030]))
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#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&__MBAR[0x32038]))
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#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&__MBAR[0x2200C + ((x)*0x1000)]))
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#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&__MBAR[0x22010 + ((x)*0x1000)]))
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#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&__MBAR[0x22014 + ((x)*0x1000)]))
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#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&__MBAR[0x22044 + ((x)*0x1000)]))
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#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&__MBAR[0x2204C + ((x)*0x1000)]))
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/* Bit definitions and macros for MCF_SEC_EUACRH */
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