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changed types to use <stdint.h>

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This commit is contained in:
Markus Fröschle
2012-10-12 15:45:50 +00:00
parent d4ecd8a366
commit cd603546d7
44 changed files with 1990 additions and 1290 deletions
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104
BaS_GNU/include/MCF5475_GPIO.h
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@@ -24,70 +24,70 @@
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31]))
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA31]))
#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32]))
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&__MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&__MBAR[0xA32]))
#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37]))
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA37]))
#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38]))
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA38]))
#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A]))
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA3A]))
#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C]))
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA3C]))
#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D]))
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA3D]))
#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E]))
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA3E]))