modified dbg() in several files
This commit is contained in:
131
net/fec.c
131
net/fec.c
@@ -32,9 +32,9 @@
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#error Unknown machine!
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#endif
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//#define DBG_FEC
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#define DBG_FEC
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#ifdef DBG_FEC
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#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
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#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
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#else
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#define dbg(format, arg...) do { ; } while (0)
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#endif /* DBG_FEC */
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@@ -237,33 +237,33 @@ void fec_log_init(uint8_t ch)
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*/
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void fec_log_dump(uint8_t ch)
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{
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dbg("%s: \r\n FEC%d Log\r\n", __FUNCTION__, ch);
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dbg("%s: ---------------\r\n", __FUNCTION__);
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dbg("%s: Total: %4d\r\n", __FUNCTION__, fec_log[ch].total);
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dbg("%s: hberr: %4d\r\n", __FUNCTION__, fec_log[ch].hberr);
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dbg("%s: babr: %4d\r\n", __FUNCTION__, fec_log[ch].babr);
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dbg("%s: babt: %4d\r\n", __FUNCTION__, fec_log[ch].babt);
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dbg("%s: gra: %4d\r\n", __FUNCTION__, fec_log[ch].gra);
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dbg("%s: txf: %4d\r\n", __FUNCTION__, fec_log[ch].txf);
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dbg("%s: mii: %4d\r\n", __FUNCTION__, fec_log[ch].mii);
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dbg("%s: lc: %4d\r\n", __FUNCTION__, fec_log[ch].lc);
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dbg("%s: rl: %4d\r\n", __FUNCTION__, fec_log[ch].rl);
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dbg("%s: xfun: %4d\r\n", __FUNCTION__, fec_log[ch].xfun);
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dbg("%s: xferr: %4d\r\n", __FUNCTION__, fec_log[ch].xferr);
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dbg("%s: rferr: %4d\r\n", __FUNCTION__, fec_log[ch].rferr);
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dbg("%s: dtxf: %4d\r\n", __FUNCTION__, fec_log[ch].dtxf);
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dbg("%s: drxf: %4d\r\n", __FUNCTION__, fec_log[ch].drxf);
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dbg("%s: \r\nRFSW:\r\n", __FUNCTION__);
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dbg("%s: inv: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_inv);
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dbg("%s: m: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_m);
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dbg("%s: bc: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_bc);
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dbg("%s: mc: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_mc);
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dbg("%s: lg: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_lg);
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dbg("%s: no: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_no);
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dbg("%s: cr: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_cr);
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dbg("%s: ov: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_ov);
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dbg("%s: tr: %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_tr);
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dbg("%s: ---------------\r\n\r\n", __FUNCTION__);
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dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch);
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dbg(" ---------------\r\n", __FUNCTION__);
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dbg(" Total: %4d\r\n", fec_log[ch].total);
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dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
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dbg(" babr: %4d\r\n", fec_log[ch].babr);
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dbg(" babt: %4d\r\n", fec_log[ch].babt);
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dbg(" gra: %4d\r\n", fec_log[ch].gra);
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dbg(" txf: %4d\r\n", fec_log[ch].txf);
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dbg(" mii: %4d\r\n", fec_log[ch].mii);
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dbg(" lc: %4d\r\n", fec_log[ch].lc);
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dbg(" rl: %4d\r\n", fec_log[ch].rl);
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dbg(" xfun: %4d\r\n", fec_log[ch].xfun);
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dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
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dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
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dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf);
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dbg(" drxf: %4d\r\n", fec_log[ch].drxf);
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dbg(" \r\nRFSW:\r\n");
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dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv);
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dbg(" m: %4d\r\n", fec_log[ch].rfsw_m);
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dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc);
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dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc);
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dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg);
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dbg(" no: %4d\r\n", fec_log[ch].rfsw_no);
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dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr);
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dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov);
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dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr);
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dbg(" ---------------\r\n\r\n");
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}
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/*
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@@ -544,13 +544,13 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
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* Make the initiator assignment
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*/
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res = dma_set_initiator(DMA_FEC_RX(ch));
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dbg("%s: dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", __FUNCTION__, ch, res);
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dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);
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/*
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* Grab the initiator number
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*/
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initiator = dma_get_initiator(DMA_FEC_RX(ch));
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dbg("%s: dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", __FUNCTION__, ch, initiator);
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dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);
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/*
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* Determine the DMA channel running the task for the
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@@ -558,7 +558,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
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*/
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channel = dma_set_channel(DMA_FEC_RX(ch),
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(ch == 0) ? fec0_rx_frame : fec1_rx_frame);
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dbg("%s: DMA channel for FEC%1d: %d\r\n", __FUNCTION__, ch, channel);
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dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);
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/*
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* Start the Rx DMA task
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@@ -583,7 +583,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
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| MCD_NO_CSUM
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| MCD_NO_BYTE_SWAP
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);
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dbg("%s: Rx DMA task for FEC%1d started\r\n", __FUNCTION__, ch);
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dbg("Rx DMA task for FEC%1d started\r\n", ch);
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}
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/*
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@@ -607,13 +607,13 @@ void fec_rx_continue(uint8_t ch)
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*/
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channel = dma_get_channel(DMA_FEC_RX(ch));
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dbg("%s: RX DMA channel for FEC%1d is %d\r\n", __FUNCTION__, ch, channel);
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dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);
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/*
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* Continue/restart the DMA task
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*/
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MCD_continDma(channel);
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dbg("%s: RX dma on channel %d continued\r\n", __FUNCTION__, channel);
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dbg("RX dma on channel %d continued\r\n", channel);
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}
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/*
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@@ -671,7 +671,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
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NBUF *cur_nbuf, *new_nbuf;
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int keep;
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dbg("%s: started\r\n", __FUNCTION__);
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dbg("started\r\n");
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while ((pRxBD = fecbd_rx_alloc(ch)) != NULL)
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{
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@@ -733,7 +733,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
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new_nbuf = nbuf_alloc();
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if (new_nbuf == NULL)
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{
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dbg("%s: nbuf_alloc() failed\n", __FUNCTION__);
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dbg("nbuf_alloc() failed\n");
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/*
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* Can't allocate a new network buffer, so we
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@@ -789,7 +789,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
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else
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{
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nbuf_free(cur_nbuf);
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dbg("%s: got unsupported packet %d, trashed it\r\n", __FUNCTION__, eth_hdr->type);
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dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
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}
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}
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else
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@@ -853,13 +853,13 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
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* Make the initiator assignment
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*/
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res = dma_set_initiator(DMA_FEC_TX(ch));
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dbg("%s: dma_set_initiator(%d) = %d\r\n", __FUNCTION__, ch, res);
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dbg("dma_set_initiator(%d) = %d\r\n", ch, res);
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/*
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* Grab the initiator number
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*/
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initiator = dma_get_initiator(DMA_FEC_TX(ch));
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dbg("%s: dma_get_initiator(%d) = %d\r\n", __FUNCTION__, ch, initiator);
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dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);
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/*
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@@ -868,7 +868,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
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*/
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channel = dma_set_channel(DMA_FEC_TX(ch),
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(ch == 0) ? fec0_tx_frame : fec1_tx_frame);
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dbg("%s: dma_set_channel(%d, ...) = %d\r\n", __FUNCTION__, ch, channel);
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dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);
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/*
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* Start the Tx DMA task
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@@ -893,7 +893,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
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| MCD_NO_CSUM
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| MCD_NO_BYTE_SWAP
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);
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dbg("%s: DMA tx task started\r\n", __FUNCTION__);
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dbg("DMA tx task started\r\n");
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}
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/*
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@@ -916,14 +916,13 @@ void fec_tx_continue(uint8_t ch)
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* selected FEC
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*/
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channel = dma_get_channel(DMA_FEC_TX(ch));
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dbg("%s: dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n",
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__FUNCTION__, ch, channel);
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dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);
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/*
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* Continue/restart the DMA task
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*/
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MCD_continDma(channel);
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dbg("%s: DMA TX task continue\r\n", __FUNCTION__);
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dbg("DMA TX task continue\r\n");
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}
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/*
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@@ -997,7 +996,7 @@ void fec_tx_frame(uint8_t ch)
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NBUF *pNbuf;
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bool is_empty = true;
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dbg("%s:\r\n", __FUNCTION__);
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dbg("\r\n");
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while ((pTxBD = fecbd_tx_free(ch)) != NULL)
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{
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fec_log[ch].dtxf++;
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@@ -1011,7 +1010,7 @@ void fec_tx_frame(uint8_t ch)
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* Free up the network buffer that was just transmitted
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*/
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nbuf_free(pNbuf);
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dbg("%s: free buffer %p from TX ring\r\n", __FUNCTION__, pNbuf);
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dbg("free buffer %p from TX ring\r\n", pNbuf);
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/*
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* Re-initialize the Tx BD
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@@ -1022,7 +1021,7 @@ void fec_tx_frame(uint8_t ch)
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}
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if (is_empty)
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dbg("%s: transmit queue was empty!\r\n", __FUNCTION__);
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dbg("transmit queue was empty!\r\n");
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}
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void fec0_tx_frame(void)
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@@ -1060,8 +1059,8 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
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/* Check the length */
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if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU)
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{
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dbg("%s: nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
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__FUNCTION__, nbuf->length, ETH_HDR_LEN, ETH_MTU);
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dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
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nbuf->length, ETH_HDR_LEN, ETH_MTU);
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return 0;
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}
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@@ -1193,7 +1192,7 @@ static void fec_irq_handler(uint8_t ch)
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event = eir & MCF_FEC_EIMR(ch);
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if (event != eir)
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dbg("%s: pending but not enabled: 0x%08x\r\n", __FUNCTION__, (event ^ eir));
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dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));
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/*
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* Clear the event(s) in the EIR immediately
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@@ -1204,8 +1203,8 @@ static void fec_irq_handler(uint8_t ch)
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{
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fec_log[ch].total++;
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fec_log[ch].rferr++;
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dbg("%s: RFERR\r\n", __FUNCTION__);
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dbg("%s: FECRFSR%d = 0x%08x\r\n", __FUNCTION__, ch, MCF_FEC_FECRFSR(ch));
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dbg("RFERR\r\n");
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dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
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//fec_eth_stop(ch);
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}
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@@ -1213,14 +1212,14 @@ static void fec_irq_handler(uint8_t ch)
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{
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fec_log[ch].total++;
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fec_log[ch].xferr++;
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dbg("%s: XFERR\r\n", __FUNCTION__);
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dbg("XFERR\r\n");
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}
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if (event & MCF_FEC_EIR_XFUN)
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{
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fec_log[ch].total++;
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fec_log[ch].xfun++;
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dbg("%s: XFUN\r\n", __FUNCTION__);
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dbg("XFUN\r\n");
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//fec_eth_stop(ch);
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}
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@@ -1228,54 +1227,54 @@ static void fec_irq_handler(uint8_t ch)
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{
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fec_log[ch].total++;
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fec_log[ch].rl++;
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dbg("%s: RL\r\n", __FUNCTION__);
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dbg("RL\r\n");
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}
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if (event & MCF_FEC_EIR_LC)
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{
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fec_log[ch].total++;
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fec_log[ch].lc++;
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dbg("%s: LC\r\n", __FUNCTION__);
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dbg("LC\r\n");
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}
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if (event & MCF_FEC_EIR_MII)
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{
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fec_log[ch].mii++;
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dbg("%s: MII\r\n", __FUNCTION__);
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dbg("MII\r\n");
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}
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if (event & MCF_FEC_EIR_TXF)
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{
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fec_log[ch].txf++;
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dbg("%s: TXF\r\n", __FUNCTION__);
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dbg("TXF\r\n");
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fec_log_dump(0);
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}
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if (event & MCF_FEC_EIR_GRA)
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{
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fec_log[ch].gra++;
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dbg("%s: GRA\r\n", __FUNCTION__);
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dbg("GRA\r\n");
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}
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if (event & MCF_FEC_EIR_BABT)
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{
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fec_log[ch].total++;
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fec_log[ch].babt++;
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dbg("%s: BABT\r\n", __FUNCTION__);
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dbg("BABT\r\n");
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}
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if (event & MCF_FEC_EIR_BABR)
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{
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fec_log[ch].total++;
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fec_log[ch].babr++;
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dbg("%s: BABR\r\n", __FUNCTION__);
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dbg("BABR\r\n");
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}
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if (event & MCF_FEC_EIR_HBERR)
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{
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fec_log[ch].total++;
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fec_log[ch].hberr++;
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dbg("%s: HBERR\r\n", __FUNCTION__);
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dbg("HBERR\r\n");
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}
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}
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@@ -1345,9 +1344,9 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
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*/
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#if defined(MACHINE_FIREBEE)
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if (am79c874_init(0, 0, speed, duplex))
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dbg("%s: PHY init completed\r\n", __FUNCTION__);
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dbg("PHY init completed\r\n");
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else
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dbg("%s: PHY init failed\r\n", __FUNCTION__);
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dbg("PHY init failed\r\n");
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#elif defined(MACHINE_M548X)
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bcm_5222_init(0, 0, speed, duplex);
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#else
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@@ -1400,7 +1399,7 @@ void fec_eth_stop(uint8_t ch)
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*/
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level = set_ipl(7);
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dbg("%s: fec %d stopped\r\n", __FUNCTION__, ch);
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dbg("fec %d stopped\r\n", ch);
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/*
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* Gracefully disable the receiver and transmitter
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*/
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