This version is working again, except network. For some reason, the DMA
interrupts don't seem to be triggered.
This commit is contained in:
Markus Fröschle
@@ -27,83 +27,80 @@
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#include <stdbool.h>
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/* interrupt sources */
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#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
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#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
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#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
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#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
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#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
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#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
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#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
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#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
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#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
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#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
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#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
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#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
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#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
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#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
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#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
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#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
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#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
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#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
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#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
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#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
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#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
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#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
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#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
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#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
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#define INT_SOURCE_PSC3 32 // PSC3 interrupt
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#define INT_SOURCE_PSC2 33 // PSC2 interrupt
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#define INT_SOURCE_PSC1 34 // PSC1 interrupt
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#define INT_SOURCE_PSC0 35 // PSC0 interrupt
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#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
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#define INT_SOURCE_SEC 37 // SEC interrupt
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#define INT_SOURCE_FEC1 38 // FEC1 interrupt
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#define INT_SOURCE_FEC0 39 // FEC0 interrupt
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#define INT_SOURCE_I2C 40 // I2C interrupt
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#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
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#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
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#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
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#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
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#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
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#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
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#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
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#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
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#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
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#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
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#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
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#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
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#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
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#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
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#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
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#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
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#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
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#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
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#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
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#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
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#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
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#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
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#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
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#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
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#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
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#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
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#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
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#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
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#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
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#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
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#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
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#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
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#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
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#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
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#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
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#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
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#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
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#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
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#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
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#define INT_SOURCE_PSC3 32 // PSC3 interrupt
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#define INT_SOURCE_PSC2 33 // PSC2 interrupt
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#define INT_SOURCE_PSC1 34 // PSC1 interrupt
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#define INT_SOURCE_PSC0 35 // PSC0 interrupt
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#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
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#define INT_SOURCE_SEC 37 // SEC interrupt
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#define INT_SOURCE_FEC1 38 // FEC1 interrupt
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#define INT_SOURCE_FEC0 39 // FEC0 interrupt
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#define INT_SOURCE_I2C 40 // I2C interrupt
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#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
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#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
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#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
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#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
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#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
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#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
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#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
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#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
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#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
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#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
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#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
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#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
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#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
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#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
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#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
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#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
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#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */
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#define FEC0_INTC_PRI 1 /* interrupt priority for FEC0 */
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#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */
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#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
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#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */
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#define FEC1_INTC_PRI 0 /* interrupt priority for FEC1 */
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#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */
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#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */
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#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
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#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
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#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
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#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
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#define FEC0RX_DMA_PRI 5
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#define FEC1RX_DMA_PRI 3
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#define FEC1RX_DMA_PRI 4
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#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
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#define FEC0TX_DMA_PRI 6
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#define FEC1TX_DMA_PRI 4
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#define FEC0TX_DMA_PRI 2
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#define FEC1TX_DMA_PRI 1
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#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
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#define ISR_DBUG_ISR 0x01
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#define ISR_USER_ISR 0x02
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#if defined(MACHINE_FIREBEE)
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/* Firebee FPGA interrupt controller */
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#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000)
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#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004)
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#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008)
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#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000)
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#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004)
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#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008)
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#define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c)
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/* register bits for Firebee FPGA-based interrupt controller */
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@@ -137,13 +134,13 @@
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#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
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#ifdef _NOT_USED_
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#define vbasehi * ((volatile uint8_t *) 0xffff8201)
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#define vbasemid * ((volatile uint8_t *) 0xffff8203)
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#define vbaselow * ((volatile uint8_t *) 0xffff820d)
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#define vbasehi * ((volatile uint8_t *) 0xffff8201)
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#define vbasemid * ((volatile uint8_t *) 0xffff8203)
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#define vbaselow * ((volatile uint8_t *) 0xffff820d)
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#define vwrap * ((volatile uint16_t *) 0xffff8210)
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#define vde * ((volatile uint16_t *) 0xffff82aa)
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#define vdb * ((volatile uint16_t *) 0xffff82a8)
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#define vwrap * ((volatile uint16_t *) 0xffff8210)
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#define vde * ((volatile uint16_t *) 0xffff82aa)
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#define vdb * ((volatile uint16_t *) 0xffff82a8)
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#endif /* _NOT_USED_ */
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#endif /* MACHINE_FIREBEE */
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