bit checks to wait for FPGA ready were the wrong way round.
Allowed the compiler to use m68k bitfield instructions (-mbitfield). Now produces nearly the same code than Fredi's assembler sources.
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@@ -219,7 +219,7 @@ void init_fpga(void)
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MCF_GPIO_PODR_FEC1L &= ~(1 << 1); /* FPGA clock => low */
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MCF_GPIO_PODR_FEC1L &= ~(1 << 2); /* FPGA config => low */
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while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5))));
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while (((MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) || ((MCF_GPIO_PPDSDR_FEC1L & (1 << 5))));
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wait_10us();
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MCF_GPIO_PODR_FEC1L |= (1 << 2);
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