bit checks to wait for FPGA ready were the wrong way round.

Allowed the compiler to use m68k bitfield instructions (-mbitfield). Now produces nearly the same code than Fredi's assembler sources.
This commit is contained in:
Markus Fröschle
2012-10-16 06:13:48 +00:00
parent 33d71f3d84
commit c4e048f152
2 changed files with 2 additions and 2 deletions

View File

@@ -219,7 +219,7 @@ void init_fpga(void)
MCF_GPIO_PODR_FEC1L &= ~(1 << 1); /* FPGA clock => low */
MCF_GPIO_PODR_FEC1L &= ~(1 << 2); /* FPGA config => low */
while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5))));
while (((MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) || ((MCF_GPIO_PPDSDR_FEC1L & (1 << 5))));
wait_10us();
MCF_GPIO_PODR_FEC1L |= (1 << 2);