diff --git a/BaS_gcc/BaS_gcc.files b/BaS_gcc/BaS_gcc.files index 1d85f7b..7a2e682 100644 --- a/BaS_gcc/BaS_gcc.files +++ b/BaS_gcc/BaS_gcc.files @@ -216,3 +216,4 @@ video/offscreen.c video/vdi_fill.c video/videl.c video/video.c +tos/jtagwait/Makefile diff --git a/BaS_gcc/flash_scripts/flash_m548x_bas.bdm b/BaS_gcc/flash_scripts/flash_m548x_bas.bdm index 98f0516..3db5836 100755 --- a/BaS_gcc/flash_scripts/flash_m548x_bas.bdm +++ b/BaS_gcc/flash_scripts/flash_m548x_bas.bdm @@ -54,7 +54,7 @@ sleep 10 #flash-plugin 0x1000 0xf000 flash29.plugin # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29 flash 0xE0000000 -flash-plugin 0x1000 0xf000 flashintelc3.plugin +#flash-plugin 0x1000 0xf000 flashintelc3.plugin # Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas) # diff --git a/BaS_gcc/flash_scripts/flash_m548x_dbug.bdm b/BaS_gcc/flash_scripts/flash_m548x_dbug.bdm index 5970061..eab7723 100755 --- a/BaS_gcc/flash_scripts/flash_m548x_dbug.bdm +++ b/BaS_gcc/flash_scripts/flash_m548x_dbug.bdm @@ -10,20 +10,20 @@ wait write-ctrl 0x0801 0x00000000 dump-register VBR -# Turn on MBAR at 0xFF00_0000 -write-ctrl 0x0C0F 0xFF000000 +# Turn on MBAR at 0x1000_0000 +write-ctrl 0x0C0F 0x10000000 dump-register MBAR -# Turn on RAMBAR0 at address FF10_0000 -write-ctrl 0x0C04 0xFF100007 +# Turn on RAMBAR0 at address 2000_0000 +write-ctrl 0x0C04 0x20000007 # Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently) -write-ctrl 0x0C05 0xFF101001 +write-ctrl 0x0C05 0x20001001 # -# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes) -write 0xFF000500 0xE0000000 4 -write 0xFF000508 0x00041180 4 +# Init CS0 (BootFLASH @ FF80_0000 - FFBF_FFFF 4Mbytes) +write 0xFF000500 0xFF800000 4 +write 0xFF000508 0x00100D80 4 write 0xFF000504 0x003F0001 4 # SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes @@ -52,27 +52,26 @@ sleep 10 # This seems to be related to large flash buffers and PC-relative adressing of the plugin #flash-plugin 0x1000 0xf000 flash29.plugin # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29 -flash 0xE0000000 -flash-plugin 0x1000 0xf000 flashintelc3.plugin +flash 0xFF800000 +#flash-plugin 0x1000 0xf000 flashintelc3.plugin -# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas) -# -# Caution: sector offset numbers need to be the ones from the x16 address range -# column and they vary in size - needs to be exactly as in the data sheet (p. 9) +# Erase flash from 0xFF800000 to 0xFFBFFFFF (reserved space for bas) # # contrary to documentation, it seems we need to erase-wait after each sector -#erase 0xE0000000 0x0 -#erase 0xE0002000 0x0 -#erase 0xE0000000 0x00004000 -#erase 0xE0000000 0x00005000 -#erase 0xE0000000 0x00006000 -#erase 0xE0000000 0x00007000 -#erase 0xE0000000 0x00008000 -#erase 0xE0000000 0x00009000 -#erase 0xE0000000 0x0000a000 -#erase 0xE0000000 0x0000b000 -#erase-wait 0xe0000000 -#blank-chk 0xE0000000 0x0 -load -v m5484lite_dbug_flash.elf +erase 0xFF800000 0 +erase 0xFF800000 1 +erase 0xFF800000 2 +erase 0xFF800000 3 +erase 0xFF800000 4 +erase 0xFF800000 5 +erase 0xFF800000 6 +erase 0xFF800000 7 +erase 0xFF800000 8 +erase 0xFF800000 9 +erase 0xFF800000 10 +erase 0xFF800000 11 +erase 0xFF800000 12 +erase 0xFF800000 13 +load -v m548xlite_dbug_flash.elf wait diff --git a/BaS_gcc/if/driver_vec.c b/BaS_gcc/if/driver_vec.c index 84ddcdf..d3526bd 100644 --- a/BaS_gcc/if/driver_vec.c +++ b/BaS_gcc/if/driver_vec.c @@ -127,7 +127,7 @@ static struct pci_bios_interface pci_interface = static struct pci_native_driver_interface pci_native_interface = { .pci_read_config_longword = pci_read_config_longword, - .pci_read_config_word = pci_read_config_longword, + .pci_read_config_word = pci_read_config_word, .pci_read_config_byte = pci_read_config_byte, .pci_write_config_longword = pci_write_config_longword, .pci_write_config_word = pci_write_config_word, diff --git a/BaS_gcc/include/driver_vec.h b/BaS_gcc/include/driver_vec.h index a441219..a50193a 100644 --- a/BaS_gcc/include/driver_vec.h +++ b/BaS_gcc/include/driver_vec.h @@ -283,7 +283,7 @@ struct pci_native_driver_interface int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter); int32_t (*pci_unhook_interrupt)(int32_t handle); - struct pci_rd (*pci_get_resource)(int32_t handle); + struct pci_rd * (*pci_get_resource)(int32_t handle); }; union interface diff --git a/BaS_gcc/include/pci.h b/BaS_gcc/include/pci.h index f3218e1..618b970 100644 --- a/BaS_gcc/include/pci.h +++ b/BaS_gcc/include/pci.h @@ -22,12 +22,12 @@ */ #include -#include "util.h" /* for swpX() */ +#include "util.h" /* for swpX() */ -#define PCI_MEMORY_OFFSET (0x80000000) -#define PCI_MEMORY_SIZE (0x40000000) /* 1 GByte PCI memory window */ -#define PCI_IO_OFFSET (0xD0000000) -#define PCI_IO_SIZE (0x10000000) /* 128 MByte PCI I/O window */ +#define PCI_MEMORY_OFFSET 0x80000000 +#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */ +#define PCI_IO_OFFSET 0xD0000000 +#define PCI_IO_SIZE 0x10000000 /* 128 MByte PCI I/O window */ /* * Note: the byte offsets are in little endian format, so you can't use them @@ -81,32 +81,32 @@ /* * bit definitions for PCICSR lower half (Command Register) */ -#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */ -#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */ -#define PCICSR_MASTER (1 << 2) /* if set: device is master */ -#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */ -#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */ -#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */ -#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */ -#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */ -#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */ -#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */ +#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */ +#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */ +#define PCICSR_MASTER (1 << 2) /* if set: device is master */ +#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */ +#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */ +#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */ +#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */ +#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */ +#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */ +#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */ #define PCICSR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */ /* * bit definitions for PCICSR upper half (Status Register) */ #define PCICSR_INTERRUPT (1 << 3) /* device requested interrupt */ #define PCICSR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */ -#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */ -#define PCICSR_UDF (1 << 6) /* UDF supported */ -#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */ -#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */ +#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */ +#define PCICSR_UDF (1 << 6) /* UDF supported */ +#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */ +#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */ -#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */ -#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */ -#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */ -#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */ -#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */ +#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */ +#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */ +#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */ +#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */ +#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */ /* Header type 1 (PCI-to-PCI bridges) */ #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ @@ -134,7 +134,7 @@ struct pci_rd /* structure of resource descriptor */ unsigned long length; /* length of resource */ unsigned long offset; /* offset PCI to phys. CPU Address */ unsigned long dmaoffset; /* offset for DMA-transfers */ -} __attribute__ ((packed)); +}; typedef struct /* structure of address conversion */ { @@ -186,43 +186,43 @@ typedef struct /* structure of address conversion */ /* PCI configuration space macros */ /* register 0x00 macros */ -#define PCI_VENDOR_ID(i) swpw((uint16_t)(((i) & 0xffff0000) >> 16)) -#define PCI_DEVICE_ID(i) swpw((uint16_t) ((i) & 0xffff)) +#define PCI_VENDOR_ID(i) swpw((uint16_t)(((i) & 0xffff0000) >> 16)) +#define PCI_DEVICE_ID(i) swpw((uint16_t) ((i) & 0xffff)) /* register 0x04 macros */ -#define PCI_STATUS(i) ((i) & 0xffff) -#define PCI_COMMAND(i) (((i) >> 16) & 0xffff) +#define PCI_STATUS(i) ((i) & 0xffff) +#define PCI_COMMAND(i) (((i) >> 16) & 0xffff) /* register 0x08 macros */ -#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24) -#define PCI_SUBCLASS(i) ((swpl((i)) & 0xffff0000) >> 16) -#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8) -#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff)) +#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24) +#define PCI_SUBCLASS(i) ((swpl((i)) & 0xffff0000) >> 16) +#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8) +#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff)) /* register 0x0c macros */ -#define PCI_BIST(i) ((swpl((i)) & 0xff000000) >> 24) -#define PCI_HEADER_TYPE(i) ((swpl((i)) & 0x00ff0000) >> 16) -#define PCI_LAT_TIMER(i) ((swpl((i)) & 0x0000ff00) >> 8) -#define PCI_CACHELINE_SIZE(i) ((swpl((i)) & 0x000000ff)) +#define PCI_BIST(i) ((swpl((i)) & 0xff000000) >> 24) +#define PCI_HEADER_TYPE(i) ((swpl((i)) & 0x00ff0000) >> 16) +#define PCI_LAT_TIMER(i) ((swpl((i)) & 0x0000ff00) >> 8) +#define PCI_CACHELINE_SIZE(i) ((swpl((i)) & 0x000000ff)) /* register 0x2c macros */ -#define PCI_SUBSYS_ID(i) (((i) & 0xffff0000) >> 16) -#define PCI_SUBSYS_VID(i) (((i) & 0xffff)) +#define PCI_SUBSYS_ID(i) (((i) & 0xffff0000) >> 16) +#define PCI_SUBSYS_VID(i) (((i) & 0xffff)) /* register 0x34 macros */ -#define PCI_CAPABILITIES(i) ((i) & 0xff) +#define PCI_CAPABILITIES(i) ((i) & 0xff) /* register 0x3c macros */ -#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24) -#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16) -#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8) -#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff) +#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24) +#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16) +#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8) +#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff) -#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0 -#define IS_PCI_IO_BAR(i) ((i) & 1) == 1 -#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1) -#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc)) -#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0)) +#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0 +#define IS_PCI_IO_BAR(i) ((i) & 1) == 1 +#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1) +#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc)) +#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0)) extern void init_eport(void); extern void init_xlbus_arbiter(void); @@ -238,9 +238,9 @@ extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data); /* * match bits for pci_find_classcode() */ -#define PCI_FIND_BASE_CLASS (1 << 26) -#define PCI_FIND_SUB_CLASS (1 << 25) -#define PCI_FIND_PROG_IF (1 << 24) +#define PCI_FIND_BASE_CLASS (1 << 26) +#define PCI_FIND_SUB_CLASS (1 << 25) +#define PCI_FIND_PROG_IF (1 << 24) extern uint32_t pci_read_config_longword(int32_t handle, int offset); extern uint16_t pci_read_config_word(int32_t handle, int offset); @@ -340,14 +340,14 @@ extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_AD extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer); extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer); -#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \ +#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \ ((bus) << 16) | \ ((device << 8) | \ (function)) -#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7))) -#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10) -#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3) -#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7)) +#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7))) +#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10) +#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3) +#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7)) #endif /* _PCI_H_ */ diff --git a/BaS_gcc/pci/pci.c b/BaS_gcc/pci/pci.c index 7e26622..647fc6a 100644 --- a/BaS_gcc/pci/pci.c +++ b/BaS_gcc/pci/pci.c @@ -33,7 +33,7 @@ #include "interrupts.h" #include "wait.h" -#define DEBUG_PCI +//#define DEBUG_PCI #ifdef DEBUG_PCI #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #else diff --git a/BaS_gcc/sys/init_fpga.c b/BaS_gcc/sys/init_fpga.c index 6e9088e..714fa74 100644 --- a/BaS_gcc/sys/init_fpga.c +++ b/BaS_gcc/sys/init_fpga.c @@ -50,8 +50,8 @@ extern uint8_t _FPGA_CONFIG_SIZE[]; * been loaded through the onboard JTAG interface. * init_fpga() will honour this and not overwrite config. */ -extern bool _FPGA_JTAG_LOADED; -extern int32_t _FPGA_JTAG_VALID; +extern uint32_t _FPGA_JTAG_LOADED; +extern uint32_t _FPGA_JTAG_VALID; #define VALID_JTAG 0xaffeaffe void config_gpio_for_fpga_config(void) @@ -94,10 +94,10 @@ bool init_fpga(void) volatile int32_t time, start, end; int i; - dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID); - if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG) + xprintf("FPGA load config...\r\n"); + if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG) { - dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n"); + xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n"); /* reset the flag so that next boot will load config again from flash */ _FPGA_JTAG_LOADED = 0; diff --git a/BaS_gcc/sys/sysinit.c b/BaS_gcc/sys/sysinit.c index ad96192..88aa9ea 100644 --- a/BaS_gcc/sys/sysinit.c +++ b/BaS_gcc/sys/sysinit.c @@ -939,8 +939,6 @@ void clear_bss_segment(void) void initialize_hardware(void) { - bool coldboot = true; - /* Test for FireTOS switch: DIP switch #5 up */ #ifdef MACHINE_FIREBEE if (!(DIP_SWITCH & (1 << 6))) { @@ -1056,7 +1054,7 @@ void initialize_hardware(void) init_slt(); init_fbcs(); - coldboot = init_ddram(); + init_ddram(); #if defined(MACHINE_M5484LITE) xprintf("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000); @@ -1117,8 +1115,6 @@ void initialize_hardware(void) } #if MACHINE_FIREBEE - if (coldboot) /* does not work with BDM */ - ; fpga_configured = init_fpga(); init_pll(); diff --git a/BaS_gcc/tos/jtagwait/sources/jtagwait.c b/BaS_gcc/tos/jtagwait/sources/jtagwait.c index 6253eee..ec8324d 100644 --- a/BaS_gcc/tos/jtagwait/sources/jtagwait.c +++ b/BaS_gcc/tos/jtagwait/sources/jtagwait.c @@ -7,8 +7,8 @@ #include "MCF5475.h" #include "driver_vec.h" -extern long _FPGA_JTAG_LOADED; -extern long _FPGA_JTAG_VALID; +extern uint32_t _FPGA_JTAG_LOADED; +extern uint32_t _FPGA_JTAG_VALID; #define VALID_JTAG 0xaffeaffe @@ -22,7 +22,6 @@ extern long _FPGA_JTAG_VALID; #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") long bas_start = 0xe0000000; -volatile uint32_t *_VRAM = (uint32_t *) 0x60000000; void wait_for_jtag(void) @@ -66,15 +65,16 @@ void wait_for_jtag(void) while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load started */ xprintf("waiting for JTAG configuration to finish\r\n"); - while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */ xprintf("JTAG configuration finished.\r\n"); - _FPGA_JTAG_LOADED = 1; /* indicate jtag loaded FPGA config to BaS */ - _FPGA_JTAG_VALID = VALID_JTAG; /* set magic word to indicate _FPGA_JTAG_LOADED is valid */ + _FPGA_JTAG_LOADED = 1; /* indicate jtag loaded FPGA config to BaS */ + _FPGA_JTAG_VALID = VALID_JTAG; /* set magic word to indicate _FPGA_JTAG_LOADED is valid */ /* wait */ xprintf("wait a little to let things settle...\r\n"); for (i = 0; i < 100000; i++); + xprintf("reset and restart..."); __asm__ __volatile__( " jmp (%[bas_start])\n\t" @@ -87,7 +87,7 @@ void wait_for_jtag(void) int main(int argc, char *argv[]) { printf("\033E\r\nFPGA JTAG configuration support\r\n"); - printf(" 2014 M. Froeschle\r\n"); + printf("\a9 2014 M. Fr\f6schle\r\n"); printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n" "and your Firebee will reboot once finished using that new configuration.\r\n"); diff --git a/BaS_gcc/video/video.c b/BaS_gcc/video/video.c index c4a9a56..feb052e 100644 --- a/BaS_gcc/video/video.c +++ b/BaS_gcc/video/video.c @@ -315,7 +315,7 @@ void video_init(void) dbg("\r\n"); /* FIXME: we currently just return here because the PCI configuration of ATI cards does not (yet) work */ - return; + //return; do {