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disabled FPGA early until its initialized freshly.

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This commit is contained in:
Markus Fröschle
2012-11-17 21:05:12 +00:00
parent 70bfe34a99
commit b8eb3353db
4 changed files with 28 additions and 14 deletions
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2
sources/init_fpga.c
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@@ -85,6 +85,8 @@ void init_fpga(void)
}
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END));
xprintf("finished copying. Clocking\r\n");
if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)
{
for (i = 0; i < 4000; i++)

2
sources/startcf.S
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@@ -40,7 +40,7 @@ _rom_entry:
move.l d0,MCF_MMU_MMUCR
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,%d0 /* supervisor only */
move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1

10
sources/sysinit.c
View File

@@ -174,6 +174,16 @@ void init_gpio(void)
// ALLE DIR NORMAL INPUT = 0
MCF_GPIO_PDDR_FEC1L = 0b00011110; /* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */
#define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1)
#define FPGA_CONFIG (1 << 2)
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
/* pull FPGA config to low as early as possible */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
}
/*